System for indicating and controlling dispensing of beverages4237536Abstract The amount of beverage dispensed from each of a plurality of reservoirs in units at a plurality of remote locations, such as hotel rooms, is controlled and indicated. A central console, such as a hotel front desk, includes a keyboard for deriving data and command signals, as well as a data processor that responds to the data and command signals to derive addressing and command signals for the units. A display at the central console responds to the keyboard data and command signals to display the keyboard data signals, as well as data signals derived from addressed units. At each of the units, a liquid flow controller for each reservoir responds to an output of a data processor at the unit. The unit data processor responds to a customer input and command signals from the console to activate the flow controller. In response to a unit being addressed by the console, the unit data processor supplies signals to the console to indicate the amount of beverage dispensed from the reservoirs. Claims We claim: Description TECHNICAL FIELD
TABLE I
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A10 A11 MEMW MEMR
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1. 0 0 1 0 ENABLE PROM 117
2. 1 0 1 0 ENABLE PROM 118
3. 1 1 1 0 READ FROM
RAMs 121, 122
4. 0 1 1 0 READ FROM
RAMs 123, 124
5. 1 1 0 1 WRITE INTO
RAMs 121, 122
6. 0 1 0 1 WRITE INTO
RAMs 123, 124
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These signals are combined by decoder 125 to supply an enabling signal to the CS input pin of PROM 117, to enable the data stored at the address indicated by bits A0-A9 to be read out as a parallel 8-bit byte at pins 9-17. The operations associated with lines 3-6 of Table I are inhibited if the sensed voltage of power supply 21 is less than a predetermined value, in response to the binary zero level on lead 135. If the voltage of power supply 21 should drop below the predetermined level, a keep alive voltage level is supplied to RAMs 121-124 by re-chargeable battery 136. During normal operation, battery 136 is charged by the output voltage of power supply 21 through PNP transistor 137. In the event of the power supply voltage dropping below the predetermined level in response to a power line failure, battery 136 is isolated from power supply 21 and a keep alive voltage is supplied by the battery to DC power input pins 18 of RAMs 121. Normally, power supply pins 18 of RAMs 121 are supplied with a DC positive voltage that is fed to them through the collector of PNP transistor 137. PROMs 117 and 118 are pre-loaded with firmware program information necessary to execute the various operations which the apparatus of the present invention performs. RAMs 121-124 are supplied with and store data, such as read/write information, time, the total number of drinks which have been dispensed from all of the reservoirs 51-55 of the various units 14, the price of each drink from each reservoir, which of the reservoirs are empty, etc. Corresponding output pins of PROMs 117 and 118, as well as corresponding output pins of paired RAMs 121, 122 and 123, 124 are connected in parallel to data bus 100; the common connections of PROMs 117, 118 and RAMs 121-124 to bus 100 are via a buffer 141, including three state, 4 bit buffer chips 142 and 143 that are controlled in parallel to pass signals in either direction or to block signals. Each of buffer chips 142 and 143 includes a pair of input pins 1 and 15, respectively connected to be responsive to the output of address decoder 125 and the read from memory signal MEMR. Chips 142 and 143 respond to the signals applied in parallel to pins 1 thereof by address decoder 125 so that the buffers are normally disabled. With an enabling signal being applied to pins 1 of chips 142 and 143, signals can be read from PROMs 117 or 118 or RAMs 121, 122 or 123, 124 through buffer 141 to data bus 100. If enabling signals are simultaneously supplied to pins 1 and 15 of buffer chips 142 and 143 and to pins 1 of chips 142 and 143, signals can be read in the other direction from data bus 100 through buffer 141 into RAMs 121, 122 or 123, 124. A further control for coupling signals to various elements of data processor 24 is attained by selectively enabled, three input to eight output decoders 145 and 146, driven in parallel by address bits A4-A7 derived from microprocessor 111. Bits A4-A7 have different combinations of values during different intervals of each one microsecond operating cycle of the program executed by data processor 24. Each of decoders 145,146 includes an enable input pin 5, responsive to address bit A7, as well as three decoding input pins 1, 2 and 3, respectively responsive to address bits A4, A5 and A6. Input pins 4 of decoders 145 and 146 are respectively responsive to I/OR and I/OW signals derived from pins 25 and 27 of controller 116. Thereby, decoder 145 is activated to be responsive to address bits A4-A6 only while it is enabled by address bit A7 and the I/OR signal, while decoder A6 is enabled by address bit A7 and the I/OW signal. Each of decoders 145 and 146 includes eight output pins 7-15, only one of which has a binary one signal at a time; the output pin having the binary one level is dependent upon the values of address bits A4-A6. The output signals of decoders 145 and 146 are respectively denominated IN00-IN70 and OUT00-OUT70. As described in detail infra, signals IN00-IN40 and OUT00-OUT50 respectively cause data processor 24 to perform certain functions during different times within each 1 .mu.s (microsecond) operating cycle associated with (1) signals being supplied to the data processor, and (2) signals derived from the data processor. Two .mu.s operating cycles form a complete microprocessor cycle time, so that 2-8 bit data outputs of the microprocessor can be multiplied to buffers of the 16 bit display deriving two consecutive cycle times. Data bus 100 is responsive to the signals on 11-lead keyboard bus 31. Data bits D0-D5 of bus 100 are selectively responsive to the 6 coded bits B1-B6 which carry information from 21 "data" keys of keyboard 22. Data bits D0-D3 of data bus 100 are selectively responsive to the four function bits F1-F4 derived from function keys 39, 41, 47 and 48 of keyboard 22; all of the other keys are the data keys. Data bits D6 and D7 are selectively and respectively responsive to closure of key switch 28 and the strobe signal supplied by keyboard 22 to keyboard bus 31. Bits B1-B6 and the strobe signal of keyboard bus 31 and a signal from switch 28 are selectively gated to data bus 100 via tri-state buffer 644 and buffer 645, responsive to keyboard function bits F1-F4. Buffers 644 and 645 are controlled by the signals at pins IN20, IN30 and OUT50 so that signals at the input pins of each buffer are gated into the buffer and then read out from the buffer. The strobe signal is coupled to buffer 644 under the control of signal OUT50 that is supplied as an enabling signal to a reset input of D flip-flop 646, having a C input terminal responsive to the signal on the strobe lead of keyboard bus 31. Flip-flop 646 has a Q output terminal on which is derived a signal that is supplied to pin 13 of buffer 644 and is selectively supplied to the buffer output pin 7 and thence to data bit line D7 of bus 100. Each time a key of keyboard 22 is struck, a signal is supplied to the C input terminal of flip-flop 646, causing an enabling level to be supplied by the Q output terminal of flip-flop 646 to input pin 13 of buffer 644. Flip-flop 646 is reset slightly after the leading edge of the strobe signal supplied to the C input terminal of the flip-flop, in response to signal OUT50. Thereby, flip-flop 646 derives a signal having a predetermined duration each time a key of keyboard 22 is activated. Buffers 644 and 645 are respectively enabled by signals IN20 and IN30 to couple the signals at the data input pins thereof to the output pins thereof once, at different times, during each one ms. program cycle of data processor 24. In response to the leading edge of enabling signal IN20, buffer 644 is activated so the six keyboard bits B1-B6 are supplied from buffer input pins 2, 4, 6, 8, 11 and 17 to storage elements in the buffer. In response to the trailing edge of signal IN20, the signals stored in the buffer elements are read out to buffer output pins 3, 9, 12, 14, 16 and 18. Buffer 645 responds similarly to the leading and trailing edges of signal IN30 to gate the signals at pins 2, 4, 6 and 17 to pins 3, 14, 16 and 18. Signals supplied to data bus 100 are selectively supplied to 16 character, 16 segment LED display 23 under the control of signals OUT20, OUT30, and OUT40 via 8-bit latch chips 151, 152, 4 to 16-bit latch decoder 153, LED driver chips 154, 155, and common cathode driver chips 156, 157. In the preferred embodiment, chips 151 and 152 are 74LS273s, chip 153 is an MC14514B, chips 154 and 155 are 8816s, and chips 156 and 157 are 8863s. Latches 151, 152 and drivers 154, 155 respond to data bits D0-D7 to selectively activate the 16 segments of a single alphanumeric character of display 23, while decoder 153 and drivers 156, 157 control which of the sixteen characters of the display are to be activated with the character supplied to latches 151 and 152, during each 2 .mu.s cycle time of the microprocessor. Pins 3, 4, 7, 8, 13, 14, 17 and 18 of chips 151 and 152 are respectively driven by D0-D7 bits of data bus 100. Eight bit latch 151 is loaded in response to an enable signal OUT20, during one .mu.s cycle time of data processor 24, while latch 152 is loaded during a subsequent 1 .mu.s operating cycle of the microprocessor, in response to an enable signal OUT30. The signals stored in latches 151 and 152 are fed through LED driver chips 154 and 155 to control illumination of the 16 segments of LED display 23. Input pins 2, 3, 21 and 22 of latched decoder 153 are responsive to data bits D0-D3 of data bus 100, while load input pin 1 of the decoder is responsive to enable signal OUT40. Decoder 153 responds to data bits D0-D3 to translate these data bits into the 16 possible places where characters can be displayed on display 23. The timing of signals IN20, IN30, OUT20, OUT30, OUT40 and OUT50, as well as the connection of chips 154-157 to data bus 100 in such that alphanumeric controlling bits B1-B7 derived from keyboard 22 are supplied to drivers 154-157 at appropriate times to form displayed messages. The derivation times of these control signals are also such that enabling signals derived from pins 5 and 7 of buffer 144, as well as from pins 3, 14, 16 and 18 of buffer 145 are supplied to pins 7, 9, 11, 13, 16 and 20 of controller 116, to enable certain operations to be performed by microprocessor 111, which then derives signals to control memory chips 117, 118 and 121-124. Data bits D0-D7 on data bus 100 are selectively supplied to and derived from universal asynchronous receiver transmitter (UART) 161, preferably a National Semi-conductor 5303 chip. UART 161 is selectively a serial to parallel or parallel to serial converter which supplies signals between data bus 100 and lines 26 which are connected to connector 17 at console 11. Eight serial bits, forming a byte, coupled through connector 17 to lines 22, are supplied to serial input (SI) terminal 20 of UART 161 via line receiver 162. When properly enabled, UART 161 responds to the 8 serial bits at pin 20 to form an 8-bit parallel output signal RR1-RR8, that is coupled to the UART output pins 5-12 respectively. The signal at pins 5-12 is selectively fed through buffer 163 to data bits D0-D7 of data bus 100. In contrast, parallel data bits D0-D7 on data bus 100 are supplied to pins 26-33 of UART 161 and are converted by the UART into eight serial bits that form a serial data byte. The 8-bit serial byte (SO) is derived from output pin 25 of UART 161 and applied to line driver 164. In response to each binary one signal at pin 25 of UART 161, one shot 164 derives a binary signal having a predetermined amplitude and duration, which binary signal is fed to leads 20 and connector 17 at console 11. Clocking of signals between pin 20 and pins 5-12, as well as between pins 26-33 and pin 25 of UART 161, is in response to a 5 kHz signal derived from cascaded frequency dividers 165 and 166. Frequency divider 165 is responsive to a 2 mHz clock signal derived from pin 6 of oscillator and frequency divider 112; the 2 mHz signal at pin 6 of oscillator and frequency divider 112 has the same phase as the phase of the signal derived from pin 10 of the oscillator and frequency divider. The signal derived from pin 6 of oscillator and frequency divider 112 is supplied to a C input terminal of D flip-flop 167, which derives a one mHz output signal that is applied to an input pin of frequency divider 165. An output pin of frequency divider 165 derives a 10 kHz signal that is applied to an input of frequency divider 166, which in turn derives a 5 kHz clock input signal applied to UART 161. Control of signals coupled between the inputs and outputs of UART 161 is in response to enabling signals IN00, IN10, OUT00 and OUT10. Parallel bits D0-D7 on bus 100 are gated from pins 26-33 into the parallel to serial converter of UART 161 in response to enabling signal OUT00 being derived during each microsecond operating cycle of data processor 24. These eight binary signals are then converter into a signal that can be derived as eight serial bits from pin 25 in response to the OUT10 signal, as coupled through inverter 167 to input pin 21 of UART 161. After signal OUT10 has been supplied to pin 21 of UART 161, the eight parallel bits are read out in sequence in response to the next eight clock pulses supplied by frequency divider 166 to UART 161. Serial data bits coupled to pin 21 are read out as a parallel 8-bit byte from pins 5-12 in response to enabling signal IN00 that is applied to pins 4 and 18 of UART 161. Signal IN00 is also applied through NOR gate 168 to input pin 1 of tri-state buffer 163 (preferably a LS241), and through inverter 169 to input pin 19 of the buffer. Buffer 163 is activated so that the signal at its input pins 2, 4, 6, 8, 11, 13, 15 and 17 is coupled to the buffer storage elements in response to the leading edge of the output NOR gate 168, and the buffer storage and elements are read out in response to the trailing edge of the output of NOR gate 168. UART 161 includes 4 status bit pins 13, 14, 19 and 22 on which are respectively derived: (1) data available (DA) signal, (2) TBMT signal which indicates that a transmit buffer of UART 161 responsive to data bits D0-D7 is empty so that a new byte can be loaded into the UART input pins 26-33, (3) parity error (PE) error signal which indicates that the serial byte received at UART pin 20 has an incorrect parity, and (4) a framing error (FE) signal which indicates that a stop bit in the received serial signal is incorrectly located. The status bit signals derived at pins 13, 14, 19 and 22 are read out of UART 161 in response to enabling signal IN10 being supplied to input pin 16 of the UART. Signal IN10 is also applied through NOR gate 168 and inverter 169 to input pins 1 and 19 of buffer 163 to enable the four status bits to be coupled to the buffer output pins 3, 5, 7 and 18 of thence to data bits D0, D1, D6 and D7 of data bus line 100. To activate audio alarm speaker 27, decoder 146 responds to a flag stored at address bits A4-A7 in RAMS 121-124. In response to the flag being set while address bits A5-A7 have a predetermined combination of values, decoder 146 derives output signal OUT70. The OUT70 signal is a short duration pulse that is coupled to an input pin of timer 171, having capacitors 172 connected thereto. Timer 171 derives a one second duration rectangular wave in response to enable signal IN70. The one second rectangular wave output of timer 171 is applied by inverter 173, which is cascaded with amplifier 174, to speaker 27 so an audio alarm is sounded. The normal 1 .mu.s operating cycle of microprocessor 111 is interrupted when signals are (1) derived from keyboard 22, (2) are to be sent between console 1 and units 14, and (3) are to be supplied to display 23. In response to an interrupt, the normal sequencing of PROMS 117, 118 is terminated at different times depending on the interrupt. After the interrupt, microprocessor 111 includes a pointer to control PROMS 117, 118 so the program is restarted from the interrupted point. Microprocessor 111 is interrupted in response to a signal being derived from keyboard 23 so a binary one signal is fed to data bit D7 while buffer 44 is enabled by IN20 or in response to a signal from unit 14 being received so a binary one signal is fed to data bit D7 while the status word of UART 161 is enabled by IN10. The interrupt flag sets bit A7 while bits A4-A6 have values that enable decoder 146 to derive signal OUT60, i.e., the OUT60 signal is enabled if the interrupt bit flag is set while bits A4-A6 have one set of values during the 1 .mu.s cycle time. Signal OUT60 is coupled to a reset input of D flip-flop 175, having a C input terminal responsive to a 1 kHz output of frequency divider 166, as coupled through inverter 176. Flip-flop 175 has a Q output connected to the interrupt (INT) input pin 14 of microprocessor 111. In response to the interrupt flag being set, signal OUT60 causes flip-flop 175 to interrupt the operation of microprocessor 111 by supplying an enabling signal to terminal 114 of the microprocessor, whereby the microprocessor normal operation is interrupted and an interrupt subroutine, which usually takes about 150 microseconds, is executed. The executed interrupt depends on the nature of the signal from keyboard 23 or unit 14 that caused the interrupt. The leading edge of a 1 kHz output of frequency divider 166, as coupled through inverter 176, causes flip-flop 175 to be set so that the interrupt input to pin 14 of microprocessor 111 is removed and the microprocessor again is operated from the same point as it had when the interrupt occurred. In summary, control signal: OUT00 indicates the data is to be loaded into UART 161; OUT10 indicates that the UART is cleared; OUT20 indicates that display segments A-H are to be latched; OUT30 indicates that display segments I-P are to be latched; OUT40 indicates that the displayed character position is to be derived; OUT50 indicates that a clear keyboard flat has been set; OUT60 indicates clear interrupt flag from the 1 kHz cycle; OUT70 activates the alarm. IN00 enables readout of UART 161 to data bus 100, IN10 enables the UART status word, IN20 resets flip flop 646, IN30 enables buffer 644 and IN40 enables buffer 645. Reference is now made to FIG. 4 of the drawing wherein there is illustrated a circuit diagram of the electronic equipment included at unit 14 of room K. Data processor 101 includes microprocessor 181, oscillator and frequency divider 182, and controller chip 183, which are preferably interconnected and operated in the same manner as the corresponding elements of data processor 24. Thereby microprocessor 181 is clocked at a two megahertz rate by oscillator and frequency divider 182 to derive 12 binary bits A0-A11 and is selectively connected to data bits D0-D7 of data bus 184 via controller chip 183. Address bits A0-A9 are coupled in parallel to input pins of PROMS 185 and 186 which store a program to activate unit 14. Address bits A0-A7 of microprocessor 187 are also fed in parallel to address input pins of a static RAM 187. In the preferred embodiment, RAM 187 in a Fairchild 3539 chip and PROMS 185 and 186 are of the same type as PROMS 117 and 118 of data processor 24. Each of the PROMS 185 and 186, as well as RAM 187, includes eight output bits which are selectively coupled to data bits D0-D7 of data bus 184. Selective activation of PROMS 185, 186 and RAM 187 is in response to address bits A10 and A11 of microprocessor 181, as wall as MEMR, MEMW and I-OR signals derived by a controller chip 183 on leads 24-26. One of PROMS 185 and 186 is selectively enabled in response to chip select (CS) signals respectively supplied by decoder 188 to pins 20 thereof. RAM 187 is selectively enabled in response to chip select signals CS1 and CS2 being respectively applied to terminals 10 and 14 thereof. Data are read out of RAM 187 in response to an enable signal being applied to R/W pin 12 of RAM 187. Selection of PROMS 185 and 186 is performed with PROM chip select decoder 188 while RAM 187 is enabled to its various states in response to signals from logic networks 189 and 190 and in response to signals derived directly from address bit A11 of microprocessor 181 and the MEMW signal derived at pin 26 of controller chip 183. PROM chip select decoder 188 selects one of PROMS 185 and 186 in response to address bits A10 and A11, as well as signal MEMR. PROMS 185 and 186 can be read out only in response to signal MEMR being enabled, while PROM read out selection is determined by whether address bit A10 or address bit A11 is enabled. To activate RAM 187, either into the read or write state, the MEMR and MEMW output signals of controller chip 183 are combined in logic network 190, including NOR gate 191, having an output which is fed through inverter 192 to CS1 input terminal 10 of the RAM. Thereafter, address bit A11 is applied by microprocessor 181 to CS2 input terminal 14 of RAM 187. To write information into RAM 187 in response to data bits D0-D7 on line 184, the MEMW signal on output pin 26 of controller 183 is enabled, after the CS1 and CS2 terminals have responded to enabling signals. To read signals from RAM 187 to data bits D0-D7 of data line 184, the MEMR signal at pin 24 of chip 183 is enabled simultaneously with enabling of address bit A11, as detected in logic network 189 that includes inverter 193 and NAND gate 194 that derives pin 13 of RAM 187. Certain functions associated with reading information into and writing information out of RAM 187 are performed by two input to four output decoders 195 and 196, as well as by logic network 197, in response to the status of address bits A0-A3, as well as in response to signals I/OR and I/OW, as derived from pins 25 and 26 of controller chip 183. Decoders 195 and 196 are enabled in response to enabling signals being applied to G input pins 1 and 15, respectively, thereof. Pin 15 of decoder 196 is directly responsive to the I/OW output signal of controller 183, on pin 27, while pin 1 of decoder 195 is responsive to the I/OR output signal at pin 25 of controller 183 and address bit A2, as derived from microprocessor 181; the I/OR signal and bit A2 are combined in NAND gate 198, having an output that drives the G input pin 1 of decoder 195. Both of decoders 195 and 196 include A and B input pins, respectively driven in parallel by bits A0 and A1 of microprocessor 181. Each of decoders 195 and 196 responds to a two-bit parallel input signal to activate one of four output pins having a decoded value of 0-3. The 0-3 output signals of decoder 195, at decoder output pins 4-7, are respectively referred to as signals IN00-IN03, while the 0-3 output signals of decoder 196, at the decoder output pins 2-9 are respectively referred to as signals OUT00-OUT03. Logic network 196 responds to address bit A2 and the I/OR signal at pin 25 of controller 183 to derive signal IN04. Data bits D0-D7 on data bus 184 are coupled to transmit pins (TR1-TR8) and to receive pins (RR1-RR8) 5-12 of universal asnynchronous receiver transmitter (UART) 201, which is identical to UART 161 at data processor 24 of console 11. Signals coupled into pins TR1-TR8 by data bus 184 are converted into an 8-bit serial signal SO is coupled from pin 25 of the UART to line driver 202, having output pins that are connected to connector plug 17. Serial binary signals received by connector 17 from console 11 are supplied to input pins of line receiver 203, and thence as SI input signals to pin 20 of UART 201. UART 201 is activated to be responsive to the 8-bit serial bytes at pin 21 to derive an 8-bit parallel output signal that is coupled by pins 5-12 to data bus 184, as data bits D0-D7. The signals on data bus 184 are coupled to (SO) pin 25 of UART 201 and the signal at SI pin 20 of the UART is connected to data bus 184 in a two-step operation. Signals at pins 26-33 are loaded into a buffer register of UART 201 in response to an enable signal being derived at terminal OUT00 by decoder 196, as coupled to DS input pin 23 of the UART. The parallel signals loaded into the buffer and read out in response to clock signals supplied to TRC and RRC pins 17 and 40 of UART 201, at the 5 kHz rate, while an enable signal is being derived by decoder 196 on lead OUT01, and supplied to XR pin 21 of the UART via inverter 204. Data are used into a buffer of UART 201 from SI pin 20 at the 5 kHz rate in response to decoder 195 deriving an IN00 enable signal that is coupled in parallel to RDE and RDA input pins 4 and 18 of UART 201. After the 8 binary bits in the signal at SI pins of UART 201 have been loaded into the UART, the eight bits are read out to data bus 104 in response to signal IN00 enabling the UART via RDA and RDE pins 18 and 4. Five kHz clock signals are supplied to TRC and RRC pins 17 and 40 of UART 201 via a cascaded arrangement of D flip-flop 205, frequency divider 206, and frequency divider 207. Flip-flop 205 in responsive to clock signals derived from oscillator and frequency divider 182, in the same manner as D flip-flop 167 in responsive to the output of oscillator and frequency divider 112. UART 201, like UART 161, includes status bits DA, TBMT, PE, and FE, respectively derived on pins 19, 22, 13 and 14, once each 1 .mu.s operating cycle of the unit microprocessor in response to signal IN01 being derived from decoder 195. The FE, PE, TBMT and DA signals derived from UART 201 are respectively applied to data bit lines D0, D1, D6 and D7 of data bus 184. Signal D4, when enabled, is coupled to microprocessor 181 via controller 183, to active the microprocessor to indicate that data to be processed is available at the input of the UART. Microprocessor 181 responds to the DA signal and its next address to activate decoder 195 to enable signal IN00 which is coupled to pins 4 and 18 of UART 201, causing 8 parallel bits to be read out from the UART to data line 184. Enabling of signal TBMT indicates that the transmit buffer of UART 201 is empty and that a new byte can be loaded into the UART for coupling to SO pin 25 and thence to console 11. The enabled TBMT signal is coupled through controller chip 183 to microprocessor 181, to cause the next address output of the microprocessor to activate decoder 196 so that signal OUT00 is derived by the decoder. Signal OUT00 is coupled to DS pin 23 of UART 201, enabling the UART to be laoded with a parallel 8 bit byte from data bus 184. An enabled PE signal on pin 13 indicates that there is a parity error in the signal received by UART 201, which parity error is fed into microprocessor 181 via data bit D1 and controller 183. The parity error signal activates microprocessor 181 to prevent loading of RAM 187 with the byte containing the parity error. An enabled signal FE at pin 14 is coupled via data bit D0 through controller 183 to microprocessor 181 to indicate that a stop bit in the frame is in the incorrect place, and advises the microprocessor to ignore the byte including the framing error. Data bus 184 is responsive to signals generated by unit 14 in response to activation of push buttons 61-65, resistance sensor 71-75, unit select source 103, calibrate switch 105, enable switch 106, and tamper switch 107. The selective closure of switches 61-65 is coupled, once each 1 .mu.s operating cycle, to data bits D0-D4 via buffer 208 that is activated in response to an enable signal being coupled to IN04 lead by logic circuit 197. Buffer 208 includes five input pins 4, 8, 11, 15 and 13, respectively connected to contacts 61-65, and five output pins 16, 12, 9, 5 and 7 respectively coupled to data lines D0-D4 of data bus 184. In response to the leading edge of signal IN04, the input pin of buffer 208 are responsive to binary signals indicating closure of contacts 61-65. In response to the trailing edge of signal IN04, the signal stored in buffer 208 is read out from pins 16, 12, 9, 5 and 7 to data lines D0-D4 of data bus 184. Buffer 209 has eight input pins responsive to an 8-bit binary signal indicative of the number of the unit installed in room K. The 8-bit signal is derived from a source 103 having eight individual switches responsive to three decimal keys for the 128 different units and a further key which sets the most significant bit to a binary one if multiple units are installed at the same location. The 8-bit binary signal coupled to the eight input pins of buffer 209 are fed into the buffer in response to the leading edge of signal IN03 derived from decoder 195 during a particular address of microprocessor 181. The trailing edge of signal IN03 activates buffer 209 to derive the 8-bit parallel signal as an output to bits D0-D7 of data bus 184. In response to an empty bottle condition being sensed by liquid detectors 71-75, enable signals are supplied to data lines D3-D7 of data bus 184. To this end, liquid detectors 71-75 are respectively connected to input pins of resistance detector circuits 211-215, each of which is enabled in response to the resistance supplied to its input pin being above a predetermined value, associated with no liquid being in contact with electrodes of the particular liquid detector. Enabling signals derived from resistance detectors 211-215 are applied to input pins of buffer 216, having three additional input pins responsive to the condition of switches 105-107. In response to any one of switches 105-107 being closed, an enabling signal is supplied to the input pins of buffer 216 which are connected to these switches. Buffer 216 includes an 8-bit output, whereby enabling signals resulting from the outputs of resistance detectors 211-215 are respectively applied to data bits D0-D4, while the signals resulting from activation of switches 105, 107 and 106 are respectively applied to data bits D5, D6 and D7 of data bus 184. Signals are supplied from input pins of buffer 216 to storage circuits of buffer 216 in response to the leading edge of signal IN02 and are read out of the buffer to data bus 184 in response to the trailing edge of signal IN02. Signals from data bus 184 are also used to activate: (1) solenoid valves 61-65, (2) empty bottle indicating LEDs 91-95, (3) legal hours LED 110, and (4) last call LED 111. Valves 61-65 are respectively activated in response to data bits D0-D4 being enabled during the interval while signal OUT03 is derived by decoder 196. Data bits D0-D4 are respectively applied to channels 221-225, each of which is identical, whereby a description of channel 221 suffices for the remaining channels. Channel 221 includes NAND gate 226 responsive to data bit D0 and the signal on lead OUT03, as coupled through inverter 227. The signal coupled through inverter 227 is applied in parallel to all of channels 221-225. NAND gate 226 has an output that is applied to a timer 228 including external circuitry which controls the length of time that a binary one signal is derived from the timer, thereby to vary the length of time valve 61 is opened, and to vary the number of ounces in each drink dispensed by reservoir 51 to a glass beneath the reservoir. Timer 228 includes an output pin that activates LED driver 229, having an output that is connected to light emitting diode 230 of electro-optical isolating element 231. Element 231 includes a light responsive silicon controlled rectifier 233 having an anode and cathode which are connected across diagonal pins of bridge 234. Bridge 234 includes another pair of diagonal pins which selectively connect pins 235 of a 120 volt AC source in series with coil 236 that actuates valve 61 in response to bridge 234 being energized into a conducting state by SCR 233 being responsive to light from LED 230. During the interval while signal OUT01 is derived by decoder 196, LEDs 91-95, 110 and 111 can be selectively activated into a latched-on condition. To this end, signal OUT01 is applied to a latch input of latch chip 237, having eight input signal pins responsive to data bits D0-D7. Latch chip 237, when activated by signal OUT02, supplies an enabling signal to an output pin corresponding with an input pin having an enabling pulse input supplied to it. The enabling level derived from the eight output pins of latch chip 237 are supplied to LED drivers 238, one of which is provided for each of LEDs 91-95, 110 and 111. The signals supplied to latch 237 cause LEDs 91-95 to be respectively activated in response to enabling signals being derived from resistance detectors 211-215. LED 110 is normally maintained in an energized condition, during legal hours, when alcoholic beverages can be dispensed from reservoirs 51-55, while LED 111 is activated for an interval immediately preceding the termination of legal hours, which interval is typically on the order of 15 minutes. The timing and arrangement of microprocessor 201 are such that enabling signals derived from buffer 216 are not applied directly to LEDs 91-95, but are coupled from the buffer to RAM 187 and thence are coupled back to the LEDs. Similarly, coils 236 of channels 221-225 are not directly responsive to energization of push buttons 61-65, but are activated in response to signals written into RAM 187, and thence read out of the RAM to channels 221-225. To summarize, control signal: IN00 indicates that data is to be supplied to UART 201; IN01 indicates that the status of UART 201 is to be determined; IN02 enables the empty status of dispensing reservoirs 61-65 is to be determined; IN-03 enables the addressed unit number to be determined; IN04 enables a determination to be made that a dispensing action has been executed at the addressed unit; OUT00 indicates that the UART is ready to transmit; OUT01 indicates that the UART is cleared; OUT02 enables the indicator lights to be activated; OUT03 indicates that a dispensing action has occurred. Before considering the detailed operations performed at console 11 and unit 14, consideration will be given to the format of data bytes transmitted in both directions between the console and stations. The signals transmitted from console 11 to units 14 are referred to as polls, each of which include five sequential bytes, each including eight parallel bits. Bytes 1 and 2 of each poll are identical, and are utilized for synchronizing purposes. Byte 3 of each poll is an address byte for the unit 14 being polled by console 11, and thus corresponds with the 8-bit binary signal supplied by unit select source 103 to each unit. The fourth byte in each poll is one of seven different commands which are transmitted from each console to an addressed station. The fifth byte in each poll is basically a parity byte, formed by an exclusive OR combination of all the bytes in the poll, whereby; (byte 5, bit i)=(byte 1, bit i).sym.(byte 2, bit i).sym.(byte 3, bit i).sym.(byte 4, bit i. Because synchronizing bytes 1 and 2 are identical in each poll, preferably having the value 00010110, the value of byte 5, bit i can be determined exclusively from: byte 3, bit i.sym.byte 4, bit i. The eight bits in command byte 4 have values indicative of the functions listed in TABLE II.
TABLE II
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0100 0000 LINE TEST
0100 0001 SEND DATA
0100 0010 CLEAR TOTALS
0100 0011 ENABLE OPERATION
0100 0100 DISABLE OPERATION
0100 0101 SET LAST CALL
0100 1000 RESET TAMPER
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All of units 14 are simultaneously connected to be responsive to the poll transmitted from console 11. However, only the addressed unit 14 responds to a poll, and such a response occurs only if: the poll contains a valid command byte 4 following address byte 3, and LRC or parity byte 5 is correct. The addressed unit responds to the poll approximately 10 milliseconds after receipt of byte 5 of the poll transmitted from console 11 to the units. However, no response is derived from the addressed unit if command byte 4 indicates that a line test is to be conducted or if data are to be transmitted from the console to the addressed unit. An addressed unit 14, when responding to a poll signal from console 11, except for the test line and send data polls, initially acknowledges receipt of the poll transmitted from the console by sending back to the console all of the five bytes of the original poll signal. The addressed unit 14 then transmits ten bytes, each including eight bits, back to console 11. Bytes 1 and 2 are identical synch bytes, each having a format of 0010111. Synch bytes 1 and 2 are followed by addresss byte 3, which indicates the address of the polled unit 14. Byte 4 is a status byte, having eight bits respectively representing eight different monitored parameters at the addressed station. The five least significant bits of status byte 4 respectively indicate whether or not reservoirs 51-55 are empty or not empty. The next three most significant bits of status byte 4 indicate the condition of switches 105-107, whereby the sixth least significant bit indicates whether or not calibrate switch 105 is opened or closed, the seventh least significant bit indicates whether enable switch 106 is opened or closed, while the most significant bit of byte 4 indicates whether tamper switch 107 is open or closed. Bytes 5-9 respectively indicate, in binary code, the number of times beverages were dispensed from each of reservoirs 61-65. Byte 10 is a parity byte, whereby each bit of byte 10 is formed by performing an exclusive OR function on the correspondingly numbered bits of the previous nine bytes forming the data poll signal transmitted from addressed unit 14 to console 11. In order for console 11 to test the line between it and any one of units 14, a 13-byte test signal is transmitted from the console to the addressed unit. Bytes 1 and 2 of a line test command are identical with the sync bytes normally transmitted from console 11 to units 14, while byte 3 indicates the address of the unit 14 over which the line is being tested. Byte 4 signals a line test command, as indicated by line 1 of Table II. Bytes 5-12 of the line test command are selected in accordance with statistical criteria to enable line testing to be performed. In a preferred embodiment, the sequence of bits for bytes 5-12 is indicated by:
TABLE III
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Byte No. Bit Values
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5 0 0 0 0 0 0 0 0
6 1 1 1 1 1 0 0 0
7 0 0 0 1 1 1 1 1
8 1 0 1 0 0 1 0 1
9 0 1 0 1 1 0 1 0
10 1 0 0 1 0 1 1 0
11 0 1 1 0 1 0 0 1
12 1 1 1 1 1 1 1 1
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After byte 12 has been transmitted from console 11 to the addressed station 14, a parity or LRC byte is supplied by the console to the line, with each bit of the LRC byte being formed as an exclusive OR of the correspondingly numbered bits of the other 12 bytes of the line test. The addressed station responds to the line test command by sending back an identical signal, except that the sync bytes 1 and 2 are 00010111, i.e., the same as the sync normally supplied from the addressed station to the console. Reference is now made to FIG. 5 of the drawing wherein there is illustrated a functional flow diagram of the operations performed by the appratus of FIG. 4, at unit 14. In general, each of the program operations illustrated in FIG. 5 is performed once during each millisecond program cycle time of data processor 101. However, certain initilization functions 241 are performed only after power is initially applied to unit 14. The initialization functions involve clearing certain portions of RAM 187 wherein there are: (1) counters which store the number of drinks dispensed from each of reservoirs 61-65; (2) flags which indicate the status of: (a) calibrate, (b) enable and (c) tamper switches 105-108, (d) the active state of unit 14, and (e) resistance detectors 211-215. In addition, each of buffers 208, 209, 216 and latch 237 is cleared so binary zeros are derived from the outputs thereof. To carry out the program at unit 14, certain one bit flags are selectively derived during 1 ms cycle time of data processor 101. These flags, stored at different predetermined bit positions in one byte of RAM 187, indicate if: (1) a message is pending for transmission from or reception at unit 14 (button pending), (2) any of buttons 61-65 is depressed (button pending), (3) unit 14 is active to be responsive to an address byte from console 11 (active), (4) unit 14 is the unit addressed by console 11 (local). The manner in which these flags are set is discussed in connection with FIG. 5. During execution of the program for unit 14, as well as console 11, many comparison operations are performed. The comparison operations are performed in the usual manner, by supplying two bytes from a portion of memory (either one byte from a designated RAM address and one byte from a designated PROM address, or two bytes from different designed RAM addresses) to exclusive or, comparison circuitry in the arithmetic register of the microprocessor. The arithmetic register responds to its inputs to derive an enable signal that sets a flag in the RAM or directs the stack pointer register of the microprocessor to an address in the PROM of the data processor. Certain addresses in RAM 187 can be considered as counters for indicating the number of drinks served from each of reservoirs 51-55. These counters of RAM 187 are arranged so that there are actually two redundant sets. One set of counters can be considered as active and directly responsive to signals indicative of the total number of dispensing operations performed for each of reservoirs 61-65. The other set of counters is responsive to output signals from the first set of counters. Counts stored in the second set of counters are added to the count on the first set when the console commands a counter interrogation. The first set of counters is cleared when each of the counters dumps its counters into the second set of counters during interrogation. The second set of counters is cleared only when console 11 acknowledges receipt of the number of drinks stored in each of the counters. This feature assures that the second set of counters stores the correct number of drinks dispensed from each of the reservoirs, regardless of whether a polling operation is performed on unit 14 by console 11 while one of buttons 51-55 is or is not activated. The first operation 242, except when a start sequence and initialization function 241 are required, involves determining the message pending flag. If operation 242 indicates that a message is not pending, the program stored in PROMS 185 and 186 is advanced to operation 243. During operation 243, a determination is made by examining the button pending flag to determine whether the status of one of buttons 61-65 is pending, i.e., was one of buttons 61-65 pressed since operation 243 was last performed or if a button is now being pressed. If the button pending flag is not set, operations 244-248 are executed in sequence. Operations 244-248 respectively involve interrogating the addresses of RAM 256 where the status of buttons 61-65 is stored; the status of buttons 61-65 is fed to the RAM under the control of signal IN04. If operations 244-248 indicate that none of buttons 61-65 is set, the program executes a DO loop and operation 243 is again performed to determine if a button is pending. In response to one of buttons 61-65 being set, RAM 187 supplies an enable signal to data bits DO-D4 during operations 244-248, respectively, whereby coil 236 of the appropriate channel 221-225 is activated during one of operations 251-254, whichever one of these operations is reached during the operating cycle being considered. The sequential performance of operations 244-248, with a possible program branch after each prevents activation of more than one of coils 236 at a time. After one of operations 251-254 has been executed, a count of one is added to one of five counters in RAM 187 that stores the number of dispensing operations associated with reservoirs 51-55 respectively. After any one of operations 255-259 has been executed, the button pending flag is set during operation 261. The flag set during operation 261 is examined during interrogation operation 243. If operation 243 indicates that the button pending flag is set, interrogation operation 262 is executed. Operation 262 involves determining if the pending button was released within the last 1 ms program cycle time of data processor 101. The operation is performed by feeding the set pending flag (set during operation 261) and the pending button flag status of the immediately preceding cycle from predetermined addresses in RAM 187 to exclusive or (comparison) circuitry in the arithmetic unit of microprocessor 181. In response to operation 262 indicating that the button has been released, the button pending flag is reset during operation 263 so that when operation 243 is next performed there is a no answer. If button released interrogation operation 262 indicates that the button was not released, the program returns to interrogation operation 242, enabling a determination to be made as to whether a message is or is not pending. In response to interrogation operation 242 indicating that a message is pending, operation 264 is executed. During operation 264 message bytes received by unit 14 from console 11 are read. The first step involved in reading a message byte from console 11 into unit 14 involves determining if the active flag has been set at the unit, interrogation 265. In response to interrogation operation 265 indicating that the active flag has not been set at unit 14, operation 266 determines if the 8-bit byte supplied by UART201 to data line 184 is a synchronization byte. In response to operation 266 indicating that the eight bits received by UART201 do not form a synchronization byte, the program is returned to message pending operation 242. If, however, it is determined that a sync byte is applied to UART201, the active flag of unit 14 is set during operation 267. Following operation 267, a counter in RAM 187, that indicates the number of received bytes, is incremented from zero to a count of 1, during operation 268. Hence, the count of the counter is one less than the number of received bytes. After operation 268, microprocessor 181 activates PROMS 181 and 186 so that the program returns to operation 242. If operation 265 reveals that the active flag was set during operation 267, the program is advanced to interrogation operation 269, during which the count of the byte counter is examined to determine if it is a one or some other number. If operation 269 determines that the byte count is one, indicating the second received byte, the program proceeds to interrogation operation 270, at which time a determination is made as to whether the second received byte is, in fact, a sync byte. It is to be recalled that the second byte is normally a sync byte, but in certain instances, there may be errors on the line or the byte counter may erroneously be set to a count of one, whereby operation 270 results in a no. A no result from operation 270 causes the active flag for station 14 to be reset during operation 271. After operation 271, the program returns to operation 242. If interrogation operation 270 determines that the second byte was, in fact, a sync byte, the program is advanced so the byte counter is incremented by a count of 1, during operation 272. After the byte counter has been incremented by a count of one by operation 272, the program returns to message pending interrogation operation 242. If interrogation operation 269 indicates that the byte counter count is not one, the program is advanced to interrogation operation 273, during which the byte counter is examined to determine whether the count stored therein is two, as occurs in response to the third (address) byte being transmitted from console 11. In response to the byte counter storing a value of two, the program is advanced to interrogation operation 274 during which a determination is made as to whether the address byte now being received at unit 14 is the same as the address of the local or particular unit 14. Hence, all of the foregoing operations are carried out by each of stations 214 in response to bytes 0, 1 and 2 being transmitted from console 11 to all of the units. In response to operation 274 indicating that the address at the particular unit 14 differs from the address tranmsitted from console 11, the active flag at the particular unit is reset during operation 271 so the particular unit is decoupled during the remainder of the poll being transmitted from console 11. If, however, the address of unit 14 is the same as the address transmitted from console 11 during the third byte, the local flag at the particular station 14 is set during operation 275. During operation 275 the bits in byte 2 are supplied to the exclusive or circuitry in the arithmetic register of microprocessor 181, to initiate accumulation of the LRC signal, which is utilized for parity check purposes. If interrogation operation 273 indicates that the byte count is not two, the program is advanced to operation 276, during which a determination is made as to whether the local flag is set; the local flag is set only if the first, second and third bytes have been correctly received and the address of the particular station coincides with the address transmitted from the console 11. In response to operation 276 indicating that the local flag is not set, the program advances to interrogation operation 277, during which the byte counter is examined to determine if it has a count of 5, which indicates that the poll from console 11 to the addressed unit 14 has been completed. In response to the byte counter having a count of 5, the program advances to operation 271, during which the active and local flags are reset. In response to interrogation operation 277 indicating that the byte count is not 5, the program advances to operation 277, during which the byte counter is incremented by a count of 1. Operation 272 is thereby performed in all of units 14, except the addressed unit which responds to the fourth (command) byte and the fifth (LRC) byte in the poll from console 11 to units 14. In response to interrogation operation 276 indicating that the local flat is set, operation 278 is performed. During operation 278, the received third, fourth or fifth byte from console 11 is fed to a designated address of RAM 187. In addition, the received byte is applied to the exclusive or circuitry in microprocessor 101, and accumulated in a register of the microprocessor arithmetic unit. Of course, operation 278 is performed only at the station 14 having an address that is the same as the address transmitted from console 11. After operation 278 has been performed, the program is advanced to interrogation operation 279, during which the byte counter is examined to determine if it has a count of five, i.e., all of the five bits of the poll from console 11 have been received. Operation 279 is also reached after operation 275 has been performed. If operation 279 indicates that the byte count is not 5, the program is advanced to operation 272, during which the byte counter is incremented by a count of 1. If, however, operation 279 indicates that the byte count is 5, operations are performed that are related to determining if the poll signal transmitted to the particular station 14 is correct and certain commands associated with byte 3 are possibly executed. If operation 279 determines that the byte count equals 5, operation 281 is performed. During operation 281, all of the accumulated bits which have been exclusive ored together are examined to determine if each of them has a binary zero value. If each of the accumulated bits does not have a binary zero value, in indication is provided that there has been an incorrect transmission to or reception at unit 14, and the program proceeds to operation 271, whereby the active and local flags at the particular unit 14 are reset. If, however, operation 281 indicates that the accumulated, exclusive ored bits all have a binary zero value, a correct transmission between console 11 and the addressed unit 14 is assumed, whereby program is advanced to operation 282. During operation 282, a stored indication (01000001) of command byte 3 is compared with the received byte 3 to determine if the addressed unit 14 is to send data back to console 11. If operation 282 indicates that the particular station 14 has been commanded to send data back to console 11, a data message is sent back to the console during operation 283. The data message has the format described supra, including ten bytes, numbered 0-9; bytes 0 and 1 are sync bytes, byte 2 is the address of the addressed unit, byte 3 is a status byte for the addressed unit, bytes 4-8 indicate the number of servings respectively associated with reservoirs 51-55, and byte 9 is the LRC or parity byte. After the data message has been sent from UART 201 at the addressed unit 14 to console 11, the program at unit 14 is advanced to operation 271, during which the active and local flags are reset. If operation 282 indicates that the command byte transmitted from console 11 to the addressed unit 14 was other than a command to send data back to the console, the program is activated to operation 284. In operation 284, the original five byte poll is transmitted from the addressed unit 14 back to console 11 as an acknowledge message. As previously indicated, however, the sync bytes of the acknowledge messages that are transmitted from the addressed unit 14 back to console 11 are modified to be 00010111. After the acknowledge signal has been transmitted from unit 14, the program is advanced to operation 285, during which the function commanded during the fourth byte of the poll transmitted from the console 11 to the addressed unit is executed. In other words, during operation 285, one of the following functions is performed at the addressed unit 14: (1) the total of the number of dispensed drinks stored in RAM 256 is cleared or erased (2) the operation of the addressed unit 14 is enabled, (3) the operation of the addressed unit 14 is disabled, (4) last call indicating LED 111 is activated, and (5) a bit in RAM 187 which indicates that tamper switch 107 has been activated, is reset. After operation 285 has been performed, the program is advanced to operation 271, during which the active and local flags are reset. A complete operating cycle of station 14 has thus been described for all possible situations at the station, whether it be an addressed or unaddressed station. A detailed program listing of the program stored in PROMS 185 and 186, in the INTEL 1080A assemblers language is enclosed as a part of Appendix I. Consideration is now given to the program of data processor 24 at console 11, by referring to the flow diagram of FIG. 6. Before describing the detailed flow diagram of data processor 24, consideration will be given to certain registers of microprocessor 111 and the function of certain addresses in RAMs 121-124 and PROMS 117, 118. Certain of the registers in microprocessor 111 indicate the status of program pointers. In addition, microprocessor 111 includes a millisecond tikker register that is responsive to two MHz clock pulses derived from oscillator and frequency divider 112, and is utilized in connection with interrupt operations. When the tikker register indicates that one millisecond has elapsed, the program of data processor 111 is restarted, to establish a one millisecond program cycle including many of the 1 microsecond microprocessor cycles. The arithmetic register of microprocessor 111 includes exclusive or, comparison circuitry that determines the result of many interrogation operations in the same manner as discussed supra for microprocessor 161. Certain addresses in RAMs 121-124 store information that has been supplied to data processor 124 by keyboard 22; other addresses in the RAMs store information or data from an addressed unit 14; other addresses are utilized as station tables to keep track of: (1) the units 14 connected in the system, (2) the rates associated with the dispensing operations at the units, and (3) the status of each unit; other addresses store the sum of all drinks that have been served at all of units 14 since power has been switched on the system; other addresses store information regarding time in milliseconds, quarter seconds, minutes, hours, days of the week, days of the month, and month; other addresses are utilized in connection with keyboard queuing to keep track of the number of keys that have been activated at keyboard 23, but which have not been processed through the display, the size of a mask, the next memory cell where characters to be displayed can be stored in the queue, the oldest cell in the keyboard queue, and cells for storing the unprocessed keyboard data; other addresses store the beginning and end of legal hours (in minutes and hours) for all seven days of the week. In addition, RAMs 121-124 store signals associated with communicating between console 11 and units 14; these signals are: a state flag, a transmit count, an address for the unit 14 in communication with console 11, a command byte, a parity byte, and a count of the byte numbers in the transmission between console 11 and unit 14. RAMs 121-124 also store other signals relating to alphanumeric displays on dynamic, LED display 23; these signals indicate whether there is a display being generated, and the current character being displayed at each of the 16 display positions. PROMs 117, 118 store the firmware program, as well as signals to activate display 23 in response to certain direct keyboard entries, as well as in response to keyboard entries that are determined by the program to be incorrect. The displayed characters are stored as 16 bit entries, formed as two 8-bit bytes that are sequentially fed to data bus 100. The main program executed by data processor 24 in response to a program sequence read out of PROM 118 in response to pointers from microprocessor 111 is broadly indicated in the flow diagram of FIG. 6A. After the system has been turned on, operation 301, addresses in RAMs 121-124 for queing keyboard 22 are cleared during operation 302. Immediately thereafter, the program is advanced to operation 303 which involves clearing the registers in UART161 and buffers 644 and 645. Immediately thereafter, the one millisecond tikker is cleared during operation 304. After all clearing operations 302, 303 and 304 have been performed, the interrupt service is enabled during operation 305, as described in detail in connection with FIG. 6B. Then buffer 163 and the communication buffers in UART 161 are cleared during operation 306. A test is then made, during operation 307, to determine if there has been a system shut down. Such a test is made by determining if the voltage at lead 135, as supplied to address decoder 125, is above or below a threshold value associated with a binary one value. If the voltage is below the threshold, a power failure is presumed and a test is made to determine whether the contents of RAMs 121-124 can be considered as being reliable. The test involves performing an exclusive or function of the signals stored in RAMs 121-124 which is indicative of the sum of all dispensed drinks with a multi-bit parity byte that is accumulated as the sum of the drinks is stored. If this exclusive or function results in a sum of zero, it is assumed that the power loss caused a change in the memory, whereby it is necessary to clear the scratch pad and station table addresses in RAMs 121-124; such clearing is performed during operation 308. If, however, operation 307 indicates that the power shutdown did not alter the signals stored in RAMs 121-124, the program proceeds to operation 309, during which clock pulses are supplied once every millisecond to designated addresses in RAMs 121-124, which addresses are considered to form a soft clock. The soft clock stores time in milliseconds, quarterseconds, seconds, minutes and hours and initially has all zeroes in it; and is thereafter incremented as described in connection with FIG. 6B. After the soft clock has been started, polling of units 14 is initiated during operation 310. Then, timing functions, as illustrated by FIG. 6D, are performed during operation 311. The program is then advanced to operation 316, during which the stored keyboard queue, indicated by FIG. 6E, is unloaded. Then, during interrogation operation 317, a determination is made as to whether the keyboard queue is empty. If the keyboard queue is not empty, the keyboard instructions in the keyboard queue are performed during operation 318, and, as illustrated in FIG. 6E. During operation 318, the various command functions which have been entered into the keyboard are performed in accordance with the flow diagrams on FIGS. 6F-6N. If, however, operation 317 indicates that the keyboard queue is empty, the station polling operations indicated by FIG. 6P are performed during operation 319. Upon completion of operation 319, the main program is recycled back to operation 311. Thus, during the normal operation of data processor 24, (when there is no interrupt) operations 311, 316, 317, possibly operation 318, and operation 319, are sequentially performed, with return from operation 319 to operation 311, without performance of operations 302-310. Interrupt operation 305, however, is performed on demand in response to activation of keys from keyboard 22, in response to the elapse of certain time intervals, and when signals are being transmitted between console 11 and unit 14 in both directions. The interrupt operations are illustrated in detail in the flow diagram of FIG. 6B. When the interrupt service is initially entered, operation 321 is performed; operation 321 involves saving the state of the program of data processor 24 when the interrupt instruction occurred. This operation involves shifting the signals stored in the various registers of microprocessor 111 into designated memory locations of RAMs 121-124. In particular, the signals stored in each of the registers of microprocessor 111 are fed to designated locations in RAMs 121-124. These registers are: (1) the program status word register, (2) the stack pointer register, (3) the 16-bits stored in the microprocessor BC registers, (4) the 16-bits stored in the microprocessor DE registers; and (5) the 16-bits stored in the microprocessor HL registers. Then the 1 millisecond tikker register in microprocessor 111 is cleared, during operation 322. If the interrupt is to service the time of the day counter or clock, which occurs once every millisecond, such servicing is performed during operation 323. During operation 323, five bytes of RAMs 121-124 are selectively activated. The five bytes indicate milliseconds, between 0 and 249, quarter seconds between 0 and 3, seconds between 0 and 59, minutes between 9 and 59, and hours within the day, between 0 and 23. The millisecond byte is incremented once every millisecond. In response to the millisecond counter in RAMs 121-124 exceeding a count of 249, the quarter second counter in RAMs 121-124 is incremented by a count of one. Similarly, the second counter in RAMs 121-124 is activated in response to a count of three being exceeded by the quarter second counter, while the minute and hour counters are activated in response to the second and minute counters respectively exceeding counts of 59. The quarter second, second, minute and hour counters are advanced in response to comparison operations performed in microprocessor 111. To increment the quarter second counter, a signal indicative of 249 milliseconds is supplied from a designated address in PROM 118 to one input of the exclusive OR, comparator circuit of microprocessor 111 immediately before the millisecond counter is incremented. After the millisecond counter has been incremented, the millisecond counter address in RAMs 121-124 is read out to the other input of microprocessor comparator. If the comparison operation indicates that the maximum 249 count of the millisecond counter has been reached, an increment pulse is supplied to the quarter second counter in RAMs 121-124. Similarly, the second, minute and hour counters in the RAMs are advanced. After the clock counters in RAMs 121-124 have been serviced, operation 324 determines if any new keys of keyboard 22 have been struck during the one millisecond operating cycle under consideration. This determination is made by examining data bit 7 of data bus 100, which has a binary one level in response to an enable signal being supplied to lead IN20 by decoder 145. If operation 324 indicates that a new key has been struck, the new key or keys are queued during operation 325. The keyboard queue includes twelve 8-bit bytes of RAMs 121-124. The first, second, third and fourth bytes respectively indicate: (1) the number of keys that have not been processed, (2) the size of a 7-byte mask indicating the number of key signals that can be stored, (3) the memory cell number where the next character can be stored in the queue, and (4) the cell number of the oldest keyed character, i.e., the key which is next in line to be processed. The remaining 8-byte locations in the keyboard queue indicate the values of the characters that are awaiting processing. The queuing technique is a standard technique, such as described in the book "Queuing Systems," written by Leonard Kleinrock. After operation 325 has been performed, or if there are no new keys as determined by operation 324, display 23 is refreshed during operation 326. The display refresh operation is well known to those skilled in the art and involves standard light emitting diode display multiplexing techniques. Display refreshing is performed with a modulo 16 position counter in RAMs 121-124 that controls where a particular character is to be displayed. In addition, a display table containing 16-bit entries selects the segments of display 23 which are to be illuminated in response to the code for the character. This table is stored in PROMs 117 and 118 and fed to latches 151 and 152 under the control of an enable signal on lead OUT30, as derived from decoder 146. The position counter of RAMs 121-124 supplies signals to latch decoder 153 in response to an enable signal being supplied to lead OUT40 by decoder 146. After operation 326 has been performed, operation 327 determines whether the communication flag is set to zero. If the flag is set to zero, there is to be no communication between UART 161 and units 14 in either way; if the flag is not set to zero, there is to be communication to and/or from the UART. The communication flag is set to zero if a parity error (PE) or framing error (FE) is indicated by UART 161 in response to an enabling signal being supplied to lead IN10 by decoder 145. If the data available (DA) signal at terminal 19, or the transmit buffer of UART 161 is enabled, the communication flag is not set to zero and the communication service program 328, illustrated in detail in FIG. 6C, is executed. After operation 328 has been performed or interrogation operation 327 indicates that the communication flag is set to zero, operation 339 is executed, during which the signals which were transferred from microprocessor 111 to RAMs 121-124 during operation 321, are transferred back to the microprocessor. After operation 329, enable interrupt operation 330 is performed in response to flip-flop 175 supplying a signal to the INT lead which is coupled to INT input terminal 14 of microprocessor 111. Microprocessor 111 and PROMs 117, 118, then continue their 1 ms operating cycle at the same place as when the interrupt occurred. The maximum time required to execute the interrupt cycle is 150 microseconds, a relatively small percentage of the one millisecond total operating cycle time of data processor 24. Reference is now made to FIG. 6C of the drawing wherein there is illustrated a flow diagram for the operations involved in servicing the communication cycle, indicated by operation 328, FIG. 6B. Associated with the communications service procedure are addresses in RAMs 121-124 which indicate: (1) the state of the communications flag, (2) a counter for the byte number of the message being transmitted from console 11 to unit 14, (3) the address of unit 14 to which the next message is to be transmitted, (4) a byte 3 command signal for the unit, and (5) an accumulated indication of the parity or LRC bit. In addition, PROMs 117 and 118 store the synchronizating bytes which are always transmitted with a poll from console 11 to units 14. RAMs 121-124 also include storage locations to indicate the byte number of the message being received from unit 14 at console 11, the two sync bytes in the received poll, the address of the unit 14 communicating with console 11, the command to which unit 14 is responsive, nine locations for a variable length message, a cell for indicating when the message was received, and a cell for storing the parity bit transmitted from the station to console 11. Twenty-three, 8-bit bytes addresses are provided in RAMs 121-124 for the communication. The state flag in RAMs 121-124 for the communication service includes one byte having individual bit locations that indicate: (1) the state (active or idle) of the communication flag, (2) whether the communication service is in a receive state, (3) whether the communication service is in a sync search condition (the normal, idle position of console 11), (4) whether UART 161 is ready, and (5) whether the communication service is in an idle state. The first step, operation 332, in the service communications subroutine 328 involves determining whether the state flag is set to receive. Normally, the state flag is not set to receive, and the program is advanced to interrogation operation 333, during which the state flag is again examined to determine if it is set to a sync search condition. If no transmission or reception is occurring, the state flag has previously been set to a sync search position, and the program is advanced to interrogation operation 333, which determines whether or not UART 161 is ready, as determined, in response to the TBMT signal at terminal 22 of the UART. If the UART 161 is ready, the program advances to operation 335, during which the character to be transmitted is read from an address in RAMs 121-124 to data bus 100 and thence to input terminals 26-33 of UART 161. Virtually simultaneously, the present time-out counter is reset to zero. After operation 335 has been performed, operation 336 determines from the state flag if synchronization has been achieved. If operation 336 indicates that synchronization has not been achieved, the program advances to operation 337 and the state flag is set to a sync search condition. Following operation 337, the number of received bytes counter in RAMs 121-124 is cleared to zero. After operation 338, the communications service subroutine is exited. If, however, operation 336 indicates that the state flag is set to sync, the program proceeds to operation 339, during which the received byte counter is bumped, i.e., incremented, by a count of one. After incrementing operation 339 has been performed, the received byte counter in RAMs 121-124 is examined during operation 341 to determine if the counter has a count of one; a count of one indicates that the second sync byte is being processed. If operation 341 indicates that the second sync byte is not being processed, the communication subroutine is exited. If, however, operation 341 indicates that the second sync byte is being processed, the state flag is set to receive during operation 342 which is followed by an exit of the communication service subroutine. If interrogation operation 334 indicates that UART 161 is not ready to transmit information, the program proceeds to operation 343, during which a 150 millisecond time-out counter in RAMs 12-124 is decremented by a count of one. Operation 343 is followed by operation 344, during which the time-out counter is examined to determine if it has a zero value. If the time-out counter does not have a zero value, the communications service subroutine is exited. If, however, the time-out counter count is zero, the communications service subroutine returns to operation 327, when the communication flag is again sensed to determine if it is set. If the communication flag is set, i.e., is not zero, the communications service subroutine is again performed, starting again with an examination of the state flag to determine if it is set to receive, as indicated by operation 332. If operation 332 indicates that the state flag is set to receive, the program proceeds to operation 345, during which the DA signal on terminal 19 of UART 161 is sensed to determine if UART 161 is ready to receive a byte from data bus 100. If operation 345 indicates that UART 161 is not ready, the program advances to operation 343 whereby the time-out counter is decremented and the program then continues as described above. If, however, operation 345 indicates that UART 161 is ready, the program advances to operation 346, during which an 8-bit, received byte is read out from UART 161 terminals 3-12 through buffer 163 to data bus 100 and is appropriately stored in RAMs 121-124. As a character is being read out from UART 161 to RAMS 121-124, the time-out counter is reset to zero. Upon the completion of operation 346, the number of received byte counter in RAMs 121-124 is incremented by a count of one during operation 347. Then, during operation 348, the count stored in the received byte counter is compared with the number of bytes in a poll from units 14 to console 11. If operation 348 indicates that further bytes are to be received during the poll, the communications subroutine is exited. If, however, operation 348 indicates that the last byte has been received, i.e., the parity of LRC byte has been received, the accumulated exclusive ORed bits of the received poll are calculated during operation 349. The accumulated exclusive ORed signals are sensed during operation 350 to determine if each of the exclusive ORed bits has a correct value. If operation 350 indicates that the exclusive ORed bits do not have a correct value, the communication flag subroutine is again re-entered, as indicated by operation 327. If, however, operation 350 indicates that the exclusive ORed bits have the correct value, the state flag is set to idle, during operation 351. Previously, consideration has been given to the operations performed if interrogation operations 332 and 333 indicate that the state flag is in a receive condition and the state flag is in a sync search condition. If, however, operation 333 is reached while the state flag is not in a sync search condition, the program advances to operation 352, which involves determining whether UART 161 is ready. If UART 161 is not ready, the communication subroutine is immediately exited. If, however, operation 352 indicates that UART 161 is ready, there is an implication that a byte is to be transmitted from console 11 to the addressed unit 14. The next character is transmitted during operation 353, which involves feeding a byte from addresses in RAMs 121-124 to data line 100 and UART 161 terminals 26-33. After the byte has been loaded into terminals 26-33, the byte is read out in series from UART 161 SO terminal 25 and transmitted to the addressed unit 14. After operation 353 has been performed, the transmit byte counter in RAMs 121-124 is incremented by a count of one, during operation 354. After the transmit byte counter has been incremented, the transmit byte counter is examined during operation 355 to determine if the last transmitted byte count of 4 has been reached. If the highest transmitted byte count has not been reached, the communications subroutine is exited. If, however, the last transmitted byte count has been reached, the program advances to operation 337 so that the communications service subroutine can again search for sync bytes. The transmit byte counter is then cleared, during operation 338 and the communications service subroutine is exited. Consideration is now given to the operations involved in timers subroutine 311, as illustrated by the flow diagram of FIG. 6D. The initial operation 411 of subroutine 311 involves reading the previous second of time from a designated memory location of RAMs 121-124. During operation 412, a test is then made to determine if the previous seconds stored in RAMs 121-124 is the same as the presently read second. If the present and previous seconds are the same, the timing subroutine is immediately exited. If, however, the previous second differs from the present second, the new second is transferred to the location in RAMs 121-124 previously occupied by the previous second, operation 413. After operation 413 has been performed, the program is advanced to operation 414, at which time a flag in the i-bit flag byte of RAMs 121-124 is interrogated to determine if an audio alarm is being sounded by speaker 27; this flag is termed system bleep. If the flag interrogated during operation 414 indicates that the system bleep is on, the program is advanced to operation 415, at which time the bleep flag is again maintained and a display recycle delay counter in RAMs 121-124 is incremented. The display recycle counter indicates a delay time, in seconds, between the last time a key of keyboard 22 was activated and the present time. If 30 seconds are counted by the recycle delay counter, it is assumed that the keyboard is unattended and the program is exited, as described infra. After operation 415 has been performed, or if operation 414 indicates that the system bleep is not on, a determination is made during operation 416 as to whether a new minute has been reached. The new minute determination is made by examining the second counter and determining if it last had a value of 59. If interrogation operation 416 indicates that a new minute has been reached, the minute counter is incremented. Then, during operation 317, the hour counter is examined to determine if it last had a value of 59; if so, the hour counter is incremented. If operation 417 indicates the hour counter is incremented, a midnight determination is made during operation 418 by sensing the hours clock to see if it last had a value of 23. Because operation 418 can only be reached if there is a new second, a new minute and a new hour, a prevous hour value of 23 | ||||||