Electronic postage meter having memory write access second chance hard timer means5438519Abstract A postage meter control system includes a microcomputer having a programmable microprocessor. The microcomputer is in communication with a decoder integrated circuit (Decoder IC). The Decoder IC has a first write control flip-flop and a second write control flip-flop, as in the preferred embodiment there are redundant non-volatile memories. Each control flip-flop has an output to a respective AND gate. The Decoder IC includes a dual timer which has an output to the control flip-flops. As a result, when the microcomputer enters write routine, the timer releases the control flip-flops to allow the system to be write enabled. If the write routine encounters a error, resulting in the timer timing out, the timer resets the control flip-flop and communicates with the microcomputer to try a retry. A more detailed description, and other features and advantages will become apparent in conjunction with the detailed description of the preferred embodiment. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE I
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OUTPUTS
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ROM# : SELECT FOR EXTERNAL PROM MEMORY
RAM# : SELECT FOR EXTERNAL RAM MEMORY
SEL1 : FOR GENERATING THE SELECT FOR EXTERNAL NVM#1
SEL2 : FOR GENERATING THE SELECT FOR EXTERNAL NVM#2
CNTRL-S : SELECT FOR INTERNAL CONTROL FLIP-FLOP BLOCK
INTR-S : SELECT FOR INTERNAL INTERRUPT CONTROLLER
STAT-S : SELECT FOR INTERNAL STATUS BLOCK
TIMER-S : SELECT FOR INTERNAL DUAL-TIMER BL4DCK
ECHO-S : SELECT FOR INTERNAL ECHOPLEX BIDCK
SERIAL-S : SELECT FOR INTERNAL SERIAL I/O BLOCK
PARALLEL-S
: SELECT FOR INTERNAL PARALLEL I/O BLOCK
ECHO/VOID#
: SELECT FOR EXTERNAL ECHOPLEX BLOCK OR SPARE
DECODE SIGNAL WHEN UNUSED MEMORY SPACE IS
SELECTED (OR NEITHER)
IO : ACTIVE WHEN ANY I/O SELECTS ARE ACTIVE
IOREAD : ACTIVE WHEN ANY OF THE INTERNAL SELECTS ARE
ACTIVE
DVOID : ACTIVE WHEN "ExtDec " IS INACTIVE AND WHEN
NONE OF THE SELECT OUTPUTS ARE ACTIVE
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OUTPUT SIGNAL ADDRESS RANGE(S SIZE
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ROM# 0000 - 7FFF 32 KBYTES
RAM# C000 - C7FF 2 KBYTES
SEL1 D000 - D7FF 2 KBYTES
SEL2 E000 - E7FF 2 KBYTES
ECHO-S FFD8 - FFDF 8 BYTES
STAT-S FFE0 - FFE1 2 BYTES
INTR-S0 FFE2 - FFE1 6 BYTES
PARALLEL-S FFE8 - FFEB 4 BYTES
SERIAL-S FFEC - FFEF 4 BYTES
TIMER-S FFF0 - FFF7 8 BYTES
CNTRL-S FFF8 - FFFF 8 BYTES
IO FFD8 - FFFF 48 BYTES
IOREAD FFD8 - FFFF; IF "EXTECHO " INACTIVE
FFE0 - FFFF; IF "EXTECHO " ACTIVE
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It will be noted that in accordance with the invention, an active DVOID output is provided from NAND gate 74 when none of the system's blocks are selected. It will also be clear to one skilled in the art that the address bits, when appropriately decoded as in the illustrated circuit by NAND gates 76, 78, 80, 82, 84, and 86 and inverters 88, 90, 92, 94, and 96 provide an "active" output IO whenever any of the I/O functions is selected and an "active" I/O read output whenever any of the internal circuit functional blocks are selected. Address bits A3 and A4 are applied to 2-to-4 demultiplexer 98 and decoded with other low order address bits for providing output signals as defined in Table I for selecting the appropriate blocks. It will be understood that the signal DVOID is not necessarily limited to its previously described function. For instance, in the illustrated embodiment, a signal VINT from the control flip-flop block further described below may be used to convert this DVOID signal to another decode output. This signal shown as "ECHO/VOID" in FIG. 3(a) is available if the circuits internal ECHOPLEX block 42 is utilized. Alternatively, it will be seen that if an external "echoplex" section is utilized, that is, when the signal "EXTECHO" is "active" the "ECHO/VOID#" output becomes the "select" signal for the external block and the "select" signal for the internal echoplex section, "ECHO-S" is disabled. As mentioned previously, the Control Flip-Flop section 32, more particularly shown in FIG. 5, generates four control output signals and their complements for controlling the generation of an illegal address interrupt signal to the processor, to provide an independent enable/disable for the access to two separate NVM storage devices, to enable and disable meter postage printing and access to non-volatile storage. As best seen in FIG. 5, the low order address signals A0, A1, and A2 are fed to a 3-to-8 Line Decoder Multiplexer 102 equivalent to a 74HC138 available from RCA to set and reset flip-flops 104, 106, 108, and 110. The processor strobe signal WR and the select signal CNTRL-S are applied to the enable inputs of decoder 102. As illustrated, it is apparent that the control flip-flops are selectively controlled when both these signals are "active". The decoder reset signal RST and EXT-INTP (a pulse signal generated at the activation of the illegal memory access interrupt signal) are "NAND'D" at "NAND" gate 112, inverted at inverter and applied to each of the flip-flops 104 and 110. Table II shows the preferred decoded control signals in response to the appropriate addresses.
TABLE II
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OUT-
A0-2 DECODED CNTRL FLIP-FLOP PUT
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0 VINT-CLR VINT IN-
ACTIVE
1 VINT-EN VINT ACTIVE PRESET
2 WR2-RESET WR2-EN IN- PRESET
ACTIVE
3 WR2-SET WR2-EN ACTIVE
4 WR1-RESET WR1-EN IN- PRESET
ACTIVE
5 WR1-SET WR1-EN ACTIVE
6 UNLOCK-SET UNLOCK ACTIVE
7 UNLOCK-CLR UNLOCK IN- PRESET
ACTIVE
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The outputs from flip-flop 104 designated UNLOCK are preferably active to enable postage printing and for NVM access. For best results, the preset value is inactive to prevent printing and NVM access. The signal WR1-EN and WR2-EN are "active" for write access to respective NVM devices #1 and #2. Again, for best results the preset values are "inactive". The output VINT which as previously discussed is fed to the decoder section 28 is active to enable an interrupt generation whenever an illegal memory access is attempted. It will be appreciated that this is preferred since in the "inactive" state it may be used to reset the generated interrupt signal or to disable the interrupt so that it may be used as a spare decode output. The VINT preset signal is "active" to enable the interrupt. The illegal address control block 38 is shown more particularly in FIG. 6. This circuit is used to provide an indication of when access to unused memory space is attempted. The DVOID decoded signal output from the decoder section 28 is nanded at NAND gate 106 with the Q output from a D Flip-Flop 198. The processors read strobe RD and write strobe WR are NAND'D at NAND gate 110, inverted and applied to the clock input of the D flip-flop 108. The decoder reset signal is NAND'D with the "VINT" signal from the control flip-flop section 32 at NAND gate 112 and applied to the RESET input shown as CLR in the Figure. Thus, depending upon the status of the signal VINT as discussed previously, the decoded void memory space indication will be latched at the lead edge of either the read or the write strobe of the microprocessor to provide the output INT-VOID from the Q terminal of flip-flop 108. In accordance with the invention, the INT-VOID signal is provided to the system microprocessor as an interrupt signal. Preferably, this indication will remain latched until reset by the reset signal from the microprocessor. Conveniently, as seen in FIG. 2(a), the output is inverted at inverter 116 and supplied at 118 at INT-VOID . For best results, this INT-VOID output pin in open-drain so as to permit any of a number of open-drain outputs wire-ored to this pin to activate the output signal. This output pin is then suitably tapped as the input signal EXT-INT which is furnished to the Status and Control Block. There, this signal is provided as a status port bit and upon its actuation, a 1 clock period pulse is generated on signal EXT-INTP . This EXT-INTP is provided from the status and control section to reset the control flip-flop and parallel I/O sections to their default (safe) states when the INT-VOID output pin is activated. Turning now the FIG. 7, the NVM Output Control Block 36 is shown in greater detail. In order to insure secure accounting in the NVM, the WRITE access to the two independent NVM devices is independently enabled and disabled under software control. The NVM OUTPUT CONTROL will block the microprocessor write strobe WR unless either of the NVM decoded select signals SEL1 and SEL2 is available and the appropriate write enable signal from the control flip-flops are available at NAND gates 118 and 120. The output of these gates are inputs to NAND gate 122 whose output is applied to NAND gate 124. The output of this gate is inverted and supplied to NAND gate 126. The other signals applied to NAND gate 124 are the decoded select signals NVM1, NVM2, ROM, RAM and VOID are taken from the output drivers and applied to NAND gate 124, with NVM 1 and NVM2 being NOR'D at NOR gate 128 and inverted before being applied to 124. It will be appreciated that the write strobe WR is blocked if the appropriate memory space is not selected. It will also be appreciated that if both NVMs are selected simultaneously the write strobe will also be blocked. A further protection feature is provided in the event that the NVM write strobe output is shorted "active". The address enable strobe at 20 is applied as the clock signal to a D flip-flop 130. If the NVMWR is shorted active, the ALE signal clocks the Q output low to block both of the NVM device selection signals at NAND gates 132 and 134. FIGS. 8(a)-8(b) are schematics of the status and control block. The block comprises a status port to allow monitoring of the control flip-flop outputs. The outputs of the control flip-flop block 32 are applied to buffer 136 for output to data bus 138, see also FIG. 2(a). The system clock input from 140 (see FIG. 2) is used in conventional fashion for timing the internal reset output by counting through D flip-flops 142, 144, and 146 to provide signal IRST which is the control signal for resetting all of the flip-flops in the circuit and is applied along with the System Reset to AND gate 148, (see FIG. 2). The block select signal STAT-S for this block, the write strobe, read strobe, and lowest order address bit are decoded to clock the writing of data at octal flip-flop 150, for initiating a general decoder reset under the control of appropriate software commands and for setting a baud-rate divider circuit if desired. The EXTECHO signal from D flip-flop 152 is used as previously discussed for selection of an external communication device (not shown). The Interrupt Controller block 50 is shown in more detail in FIGS. 9(a)-9(f). The interrupt controller in accordance with the invention provides great flexibility in the servicing of the various interrupt signals to the microprocessor. The signal INT-VOID from the illegal address control block 38, signals INT-TO and INT-TI generated by the time-out of timers in timer block 44, signal INT-ECHO from the ECHOPLEX block 42 which is "active" to indicate the start of an echoplex message, signal INT-SERIAL from serial I/O block 46 which is "active" when new data is received or when the port is read for sending data, and signal INT-MOTOR from PARALLEL I/O block 48 which is preferably "active" when an illegal motor control output has been communicated are each input to the INTERRUPT CONTROLLER block 50. The status of each of these signals may be read out directly from buffer 154 when the RD-INTR signal is "active". Signal INTA from the system microprocessor is an interrupt acknowledge. It will be appreciated that if the INTA line is held or tied in the "inactive" state, each interrupt signal input applied through gates indicated generally at 156 and fed to NAND gate 158 will create an interrupt request signal INTR for communication to the system's microprocessor. Preferably, mask bits may be fed as data on data input bus 16 for providing masking bits to D-flip-flops 160 for latching. The latched outputs from 160 are applied to gates 156 so that the interrupt request will be generated whenever an unmasked device requests service. The particular device requesting service may be determined by reading the status buffer 154. The interrupt lines are also coded at the gates indicated generally at 162 for feeding to latch 164 which also provides similar information. Preferably, as shown, there is also included a vectored interrupt for the handling of service requests. As discussed previously, a non-masked interrupt results in the generation of an interrupt-request signal to the systems microprocessor. For best results, the microprocessor upon receiving this signal will transmit an interrupt acknowledge signal INTA . This signal places the contents of the opcode latch 166 onto the data bus. In accordance with the invention, the processor interprets this data as an opcode, normally a call instruction for the microprocessor. Upon execution of the instruction, the microprocessor generates another INTA pulse to enable the lower vector latch 168. The encoding of bits on this latch as described above. The vector thus generated, desirably reflects a predetermined code representing the highest priority interrupt. The next INTA pulse, in response to the call of this OPCODE, will place the data residing in latch 170, preferably the upper vector address data, onto the data bus 138. The INTR-S signal is utilized to select this block. The low order address signals A0 through A2 are used as illustrated to decode the various control signals on the gates indicated generally at 140. Echoplex circuits suitable for use in block 42 are discussed in U.S. Pat. No. 4,301,507 incorporated by reference herein. Serial I/O and parallel I/O port circuits are well known and will not be discussed further herein. FIG. 10 and FIG. 11 are timing diagrams showing the interrelationship of signals previously discussed. The designated parameters and preferred timing are shown in TABLE III. It is believed that these diagrams will be readily understood by those skilled in the art so they will not be further described except with regard to the operation of the circuit.
TABLE III
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SYMBOL
PARAMETER MIN
MAX UNIT
NOTE
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.sup.t ALE
ALE STROBE WIDTH 75 ns CONDITION
.sup.t AHS
AB-15 SET-UP TIME
50 ns CONDITION
.sup.t ALS
AD0-7 SET-UP TIME
40 ns CONDITION
.sup.t ALH
AD0-7 HOLD TIME 30 ns CONDITION
.sup.t ARW
ALE TO RD OR WR STROBE
125 ns CONDITION
.sup.t RDW
RD STROBE WIDTH 225 ns CONDITION
.sup.t WRW
WR STROBE WIDTH 220 ns CONDITION
.sup.t WS
WRITE DATA SET-UP TIME
50 ns CONDITION
.sup.t INW
INTERRUPT PULSE WIDTH
125 ns
.sup.t ACC
ALE TO VALID DATA 300 ns
.sup.t ALD
ALE TO VALID A0-7 50 ns .sup.t ACCMAX -250ns
.sup.t (CE)PD
A8-15 TO:
ROM ENABLE STROBE 50 ns .sup.t ACCMAX -250ns + .sup.t AHMIN
RAM ENABLE STROBE 50 ns .sup.t ACCMAX - 250ns + .sup.t AHMIN
NVM1 ENABLE STROBE
60 ns .sup.t ACCMAX -250ns + .sup.t AHMIN
NVM2 ENABLE STROBE
60 ns .sup.t ACCMAX -250ns + .sup.t AHMIN
ECHO/VOID STROBE 70 ns .sup.t ACCMAX -250ns + .sup.t AHMIN
.sup.t DS
INPUT PORT DATA
SET-UP TIME 50 ns
.sup.t WH
WRITE DATA HOLD TIME
75 ns
.sup.t NWD
WR TO NVMWR DELAY 35 ns .sup.t WHMIN - .sup.t NWDMAX
.sup.t NVMH
WRITE DATA HOLD TIME
AFTER NVMWR 50 ns .sup.t WHMIN - .sup.t NWD
.sup.t DO
WR TO OUTPUT PORT
DATA VALID 75 ns .sup.t WHMIN
.sup.t RH
A0-7 HOLD TIME AFTER RD
0 ns
.sup.t RDH
DATA HOLD TIME AFTER RD
0 50 ns
.sup.t RWI
RD OR WR TO INTR 90 ns
.sup.t DMLT
DMLDIS TO A0-7 FLOAT
25 ns
.sup.t EXT
EXTDEC TO CE's FLOAT
25 ns
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The operation of the circuit has been particularly described with respect to each of the functional units. Broadly, however, the circuit 10 in accordance with the invention receives and decodes the periodic address signals communicated from the microprocessor and received at decoder block 28 and control flip-flop block 32. The address signals are decoded to provide an "active" selection signal for each of the various blocks of the circuit 10 and the memory devices of the electronic postage meter depending upon the communication of the appropriate addresses for the particular device. In the event, that an illegal address is communicated either because of a microprocessor or software failure or because of a failure in the instant circuit, the DVOID signal from the decoder block 28 goes "active" causing the output of gate 106 (FIG. 6) to go high and latching the Q output off flip-flop 108 active. Thus, a latched interrupt signal is sent to the interrupt control block 50 for communication to the microprocessor which responds as previously described above in conjunction with FIGS. 9(a)-9(f) whenever an illegal access is attempted. As discussed previously, further protection is provided in the event that both non-volatile memories are selected. As seen in FIG. 7, if both the NVM1 and the NVM2 signals are active the output of gate 128 is high. This output is inverted and applied to gate 124 whose output is then held high so long as both devices are selected. The output of 124 is inverted and the low input to gate 126 blocks the microprocessor's write strobe WR to the NVM. It will also be appreciated that an additional interlock exists on the write access to each NVM by way of control flip-flops WR1-EN and WR2-EN. Under software control, write access is provided to NVM1 only when WR1-EN is set. Similarly, write access is provided to NVM2 only when WR2-EN is set. Protection is also provided during system power up with the use of the unlock control flip-flop signal. It is a master control of access to the NVM's and postage printing which will disable these functions until the software operating system is ready to enable them. In order to assure that signal NVMWR , the output from gate 126 is not shorted active and so to assure that writing to the NVM is being commanded by the microprocessor, the selection of a non-volatile memory is blocked if NVMWR is held active. The output write enable signal NVMWR is fed to latch 130 (FIG. 7) which is clocked by the address-latch-enable signal (ALE) from the microprocessor. The Q output from the latch which is normally high is used to enable gates 132 and 134. If NVMWR is active when the ALE signal becomes active, the Q output of latch 130 goes high and blocks the output of gates 132 and 134. Thus, in order for a non-volatile memory to be selected there must be a periodically active non-volatile memory write enabling signal and selection of only one non-volatile memory to assure that the microprocessor is providing the appropriate data to the appropriately selected NVM. Schematically shown in FIG. 12 is the CPU, Decoder IC, Reset IC and NVMs. As earlier noted, the VOID-INT pin of the Decoder IC is open drain. This pin may be connected to the TO-INT open drain pin of the Decoder IC. The TO-INT pin is connected to the internal interrupt pin of the CPU (refer to FIG. 1B). As now connected, when the microcontroller CPU enters the standard write routine, the dual timer 44 (also refer to FIG. 2C) is programmed to count the time that the write routine function should not exceed and then dual-timer 44 is activated. The write proceeds as afore described, however, the timer 44 is now in communication with the reset pin R of the flip-flops. Upon exiting the write routine, the dual-timer 44 is disabled and set to an inactive condition. If the write procedure is not completed within the time T.sub.o the timer 44 times out actuating the reset of the flip-flops and thereby locking the flip-flops. The output of the timer 44 upon time-out is also directed to the inter INTA/ of the CPU which upon receiving this interrupt enters a conventional write retry. In the preferred embodiment it is appreciated that the time T.sub.o is at less 50% less that the timer of the reset timer. Alternatively, the pin VOID-INT may remain open. In this case, a conventional software timer may be employed. When a software timer is employed, as the software enters a write routine line ST goes active releasing the flip-flops 1 and 2, for the write procedure as afore described. If the write procedure is not completed within the allotted software time the software causes line ST to go active resetting the flip-flops and causing the software to enter a retry. It will be understood that the claims are intended to cover all changes and modifications of the embodiment herein chosen for the purpose of illustration which do not constitute departures from the scope and spirit of the invention.
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