Digital scale with antifraud features4159521Abstract Improved electronic apparatus for weighing and computing the value from the weight and price per unit weight, for each of a plurality of successive weighing operations. An integrated circuit microcomputer is supplied with the article weight from a load cell and an analog-to-digital converter. The price per unit weight is supplied from a manual keyboard. The microcomputer includes as an arithmetic logic unit, data registers and sequence controller which is programmed to correct for scale errors, to check for no motion of the scale, to compensate the measured gross weight for any tare weight, to check various interlocks, and to compute an article value for each successive weighing. Null or zeroing and tare interlocks, checks, and safeguards are provided to reduce the possibility of fraud. Claims What we claim is: Description REFERENCE TO BACKGROUND PATENT APPLICATIONS AND PATENTS
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Count Q.sub.E1 Q.sub.E2
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00,000 to 09,999 1 1
10,000 to 19,999 0 0
20,000 to 29,999 1 0
30,000 to 39,999 0 1
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During the third count to 10,000 by counter stages A, B, C, D, and E a low "turn on" voltage is applied to conductor 229 which turns on the field effect transistor 215. During the fourth count of 10,000 by the stages A, B, C, D, and E a low voltage is applied to conductor 230 which causes the field effect transistor 216 to be turned on. At the end of the count of 40,000 (i.e. 00,000 to 39,999) by the counter stages A, B, C, D, and E, the fifth counter stage E will return to its initial state thus resetting the entire counter to zero. A 10 count circuit 237 is provided in the integrated circuit 224 to permit time for switching so that switching transients do not adversely effect the operation of the integrated circuit 224. In operation, the counters of the integrated circuit 224 count clock pulses from the clock circuit 221, which pulses are amplified by amplifier 222. The clock 221 runs continuously as do the counters of the integrated circuit 224. The technique of analog-to-digital conversion employed by the exemplary embodiment utilizes the Dual Slope Integration method which involves integrating an unknown current directly related to the unknown voltage for a fixed period of time, followed by the integration of a standard current until the integrator output returns to zero. In order to more readily understand the operation of the analog-to-digital converter comprising the integrating circuit 218 and 219 and the threshold circuit 220, it is more convenient to start the description during the third count to 10,000 (i.e. 20,000 to 29,999 counts) of the counter stages A, B, C, D, and E. As pointed out above, during this third count to 10,000 a "turn on" low voltage is applied to conductor 229 to turn on the transistor 215. The transistor 215 connects resistor 238 around the integrating capacitor 219 thus discharging this capacitor. Then during the next or fourth count of 10,000 (i.e. 30,000 to 39,999 counts) by the counter stages A through E inclusive, a "turn off" voltage is applied to conductor 229 to turn off the field effect transistor 215 and a low "turn on" voltage is applied to conductor 230 turning on the field effect transistor 216. The low "turn on" voltage on conductor 230 is obtained from the NAND gate 225 because at this time the two outputs Q.sub.E1 and Q.sub.E2 of the fifth counter stage E will be in their one state or high logic level thus activating this NAND gate to apply a low "turn on" voltage to the conductor 230. The low voltage on conductor 230 at this time prevents an output from the NAND circuit 239 as discussed more fully below. With the field effect transistor 216 turned on, the integrating circuit and in particular capacitor 219 is charged to a voltage which is a function of the charging time and the voltage of the output of the preamplifier 112. The charging time of this capacitor 219 is a fixed or constant time which is determined by the time required for the counter stages A through E inclusive to count 10,000 clock pulses. Thus the voltage or charge on capacitor 219 is now a function of the load on the scale 110. In addition, the counter stages A through E are all set to zero at the end of this fourth count of 10,000 clock pulse. The reset transfer flip-flop 246 is also set to zero so that it will be in condition to respond to the next transfer pulse. With the output Q.sub.E1 and Q.sub.E2 returned to their zero states during the first count of 10,000 (i.e. 00,000 to 09,999) the low or "turn on" voltage on conductor 230 is replaced by the "turn off" voltage so that the field effect transistor 216 is turned off with the result that the capacitor 219 is not charged further at this time from the output of the preamplifier 112. In addition, application of the "turn off" voltage to conductor 230 conditions the gate 239 so that it will respond when a voltage is applied to its upper terminal as more fully described below. The resetting of the fifth counter stage E causes the application of a "turn off" voltage to conductor 230 which permits a low or "turn on" voltage to be obtained from the NAND circuit 227, which voltage is applied to conductor 228 with result that the field effect transister 217 is turned on. As a result the integrating capacitor 219 is discharged at a fixed rate by the preset potentiometer 214 and resistor 209, which potentiometer and resistor are used to adjust this rate and thus control a span of the scale output. This potentiometer is located under the scale cover so it can only be adjusted by maintenance or service personnel. This discharge continues during the first of the counts of 10,000 (i.e. 00,000 to 09,999 counts) by the counters A through E and at the end of this time the first stage of the counter E is set to its one state with the result that the low output voltage of NAND circuit 227 is maintained on conductor 228 so that field effect transistor 217 remains conductive and the discharge of the integrating capacitor 219 continued. When the capacitor 219 is discharged to approximately zero volts during either the first or second count of 10,000 clock pulses, i.e., when the voltage of this capacitor crosses the threshold value of the threshold amplifier circuit 220, the output of this amplifier changes. As a result, when the next clock pulse from clock circuit 221 is applied to the AND circuit 223 an output pulse will be obtained from this circuit and cause the flip-flop comprising the circuit 240 and 241 to change state and apply a signal to the upper terminal of circuit 239. The output signal of circuit 239 is inverted and applied to the transfer lead 236 of the integrated circuit 224. This circuit is so arranged that upon receipt of the leading edge of this transfer signal, the setting of the counting stages A, B, C, D, and E are transferred substantially simultaneously to the latches 231, 232, 233, and 235. Thus the setting of the latches now represents the weight upon the scale 110. The transfer signal may take place any time during the first and second counts of the counter stages A through E inclusive of 10,000. At the end of the second count to 10,000 of the counter stages A through E inclusive, a "turn off" voltage will be applied to conductor 228 thus turning off the field effect transistor 217. In addition, a "turn on" voltage will be again applied to the conductor 229 thus turning on the field effect transistor 215 which, as described above, causes the integrating capacitor 219 to be discharged. In addition, a voltage representing a one signal is applied to the T1 conductor extending to the multiplexing interface units between the analog-to-digital converter of FIG. 2 of the computer of FIG. 6. This voltage is maintained on the T1 conductor during the time it is required for the counter stages A through E to count 10,000 clock pulses from the clock circuit 221. Voltage on this conductor T1 indicates that a bona fide conversion representing the weight on the scale in digital form is available from the five, 4-bit latches 231, 232, 233, 234, and 235. During this time the computer through the interface circuits described hereinafter causes the various digits representing the weight to be transferred from the latches 231 and 235 to the registers within the computer as will be described hereinafter. The value of each of the decimal digits is represented by binary code and transmitted over four conductors to the multiplexing unit. The blanking control circuit 242, the scanner circuit 243 and the multiplexer 244 all cooperate with each other and with the five 4-bit latches 231, 232, 233, 234 and 235 so that when a zero signal is on the digit B, digit C, digit D, and digit E conductors, the conditions of the four bit latch 231 will be transmitted by the multiplexer 244 to the WT1, WT2, WT4 and WT8 output conductors. Thereafter, when a step signal or pulse is received over conductor 245 by the scanner circuit 243, this circuit will advance one step and cause a "one" signal to be transmitted over the output DIG B conductor and zero signals over the other DIG C, DIG D, and DIG E conductors. In addition, the binary coded decimal digit stored in the four bit latch 232 will be transmitted from the multiplexer circuit 244 over the WT1, WT2, WT4 and WT8 conductors. In a similar manner, when the next step signal or pulse is received over conductor 245, the scanner again advances and causes the blanking control circuit 242 to apply a one signal to the DIG C conductor. At this time, a zero signal will be applied to the DIG B, DIG D, and DIG E conductors. Thus, upon the receipt of a step signal or pulse on conductor 245, the scanner is advanced one step and a different one of the four bit latch output conductors are connected through the multiplexer 244 to the output conductors WT1, WT2, WT4, and WT8. During any reading cycle, five step pulses or signals are applied to the conductor 245 by the computer as will be described hereinafter which cause signals representing the binary coded decimal digit stored in the respective four bit latches 231 through 235 to be transmitted through the multiplexer 244 in succession to the output conductors WT1, WT2, WT4, and WT8. The manner in which the various elements of the computer 116 are interconnected is shown in FIG. 6. These elements are interconnected through the incoming multiplexing circuit shown in FIG. 3. These multiplexing circuits comprise an interface between the analog-to-digital converter shown in FIG. 2 and the computer 116 shown in FIG. 6. In addition, the various elements of the computer are connected through the circuits of FIG. 4 to the front and back display circuits and tubes of FIG. 5. As indicated above, while the present invention is not limited thereto, the exemplary embodiment of the present invention employs an Intel Microcomputer Model MCS4 manufactured by the Intel Corporation of Santa Clara, Calif. As shown in FIG. 6, the computer 116 comprises a central processing unit CPU 610 together with a random access memory RAM 611 and a group of five read only memories ROM's 612, 613, 614, 615, and 616. In the exemplary arrangement described herein the CPU 610 is an Intel type 4004 integrated circuit. The RAM 611 is an Intel type 4002 integrated circuit and the ROM's 612 through 616 inclusive are Intel type 4001 integrated circuits. However, other commercially available integrated circuit microcomputers or other types of commercially available computers will operate equally well in accordance with the principles of the present invention described herein. These various circuits are described in the User's Manual for this computer published by the Intel Corporation. This User's Manual is incorporated herein by reference. The various CPU, RAM and ROM units are interconnected in the manner shown in FIG. 6 as required in order for these units to cooperate one with another as required by the circuit configurations of these standard commercially available units. The connections are clearly described in the User's Manual for the MCS4 microcomputer and published by the Intel Corporation. Briefly, the ROM's, the RAM and the CPU are all connected in parallel by the date bus system shown at the top of FIG. 6. These connections permit the cooperation between the ROM's, RAM and CPU. Thus, the CPU will transmit an address over the bus system which defines a storage space in one of the ROM's for example. The ROM having this storage space has internal control circuitry which will respond to this address and in turn cause information stored at the designated address to be transmitted back over the data bus system to the CPU which then responds to this information in the usual or intended manner. The RAM 611 in addition to comprising a random access memory which is readily controlled by the CPU 610 also includes four I/O ports which, in the exemplary embodiment of the invention described herein, are arranged to operate as output ports so that output control information from the CPU unit 610 may be transmitted from these output ports. In the exemplary embodiment described herein, the information transmitted from these ports is employed to control the multiplex decoding equipment of FIG. 3 and to apply stepping pulses over the step conductor 245 to the analog-to-digital converter described above. Each of the ROM's 0 through 4 is also provided with four ports. The four ports of ROM 0 are employed as input ports and receive the value of the various decimal digits of the weight from the analog-to-digital decoder and other input information. The ports of the remaining ROM's are all employed as output ports. The ports of ROM's 1 and 3 are employed to control or select the various display digits. The ports of ROM 2 are employed to control the respective display digits so that they will display the correct value of the corresponding digit. Rom 4 is employed to control the display lamps indicating the graduations and other information relative to the operation of the scale. In addition, certain of the ports of the ROM's are employed to control other features and apparatus as will be described. The various ports of the ROM's and RAM provide interface and latching circuitry so that the output information will be obtained from the ports until it is changed by the central processing unit of the computer. In addition, the output ports are provided with amplifiers which further isolate the various output devices and the computer and to provide sufficient power to adequately control the various devices. The input decoding multiplex equipment is employed as an interface between the analog-to-digital converter, the switches and the computer as shown in FIG. 3. This equipment comprises four 8-line to 1-line decoders. The output is transmitted to ROM 0 as an input. The operation of each of the decoders is controlled by the output of the first three leads from the RAM 611. These 8-line to 1-line decoders are represented in the drawing at 310, 311, 312, and 313. These devices are well-known in the art and readily obtainable commercially. The keyboard switches are represented at 314 and include a key for each of the decimal digits 0 through 9. They also include a key for a quarter and a key for a half. In addition, a zero key 315 designated Z in the drawing is provided to permit the operator or attendant to null or zero the scale as will be described hereinafter. A verification key 316 is provided to permit the operator or attendant to check or verify the circuits of the various display segments to insure that some of them are open or burned out and that none of them are shorted or always turned on. Also, a tare key 317 is provided to permit tare to be entered in the scale in a manner to be described hereinafter. A group of mode or function switches 318 is provided to control the mode of operation of the scale and display. Which switches are usually located below the cover of the scale and not available to the operator. These switches are usually set when the scale is installed and maintained in this condition. However, when the scale is serviced or its mode of operation changed then these switches may be correspondingly changed. Switch SW1 is not used and must be in the "OFF" position. Switch SW2 (designated 630 on FIG. 6) is designated tare optional and when OFF, entry of a tare is required before a price can be entered. When ON the tare entry is optional but if entered it must be done before the price is entered. Switch SW3 is mandatory price/unit. When this switch if OFF display of fractional pricing is allowed. When the switch is ON however, price per quarter unit or per half unit will be displayed as price per unit. That is, even though a price may be entered as a price per quarter unit or half unit, the price will be displayed as a price per unit computed from the entered price per quarter unit or half unit. The switch SW4 is the two digit price interlock switch. When this switch is ON a weight display of greater than 10 positive increments is inhibited until two or more price digits are entered. When OFF the weight will display regardless of price entry. Switch SW5 is the 10 increment auto clear switch. When this switch is ON, price and tare will be cleared automatically from the scale when the net weight returns to below 10 positive increments after having been above this value for more than 1.5 seconds. When OFF tare may be cleared via the operation of the numerical zero key followed by operation of the tare key within the prescribed time limit. Entry of tare weight always clears the price entry so that price per unit value must be again entered after tare is entered. Switch SW6 is the capacity select number 1 switch and SW7 is capacity select number 2 switch. The settings of these switches are combined to select the scale weighing capabilities or capacities as follows:
TABLE A
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Capacity SW 6 SW 7
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15.00 lb .times. .01 lb
OFF OFF
7.000 kg .times. 5g
OFF ON
6.000 lb .times. .005 lb
ON OFF
3.000 kg .times. 2g
ON ON
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Switch SW8 is the motion blank switch. When this switch is ON the weight display the total price display will display zeros while the indicated weight is changing, that is the scale platform or platter is in motion. When the switch is OFF the weight display and the total price display do not blank out during motion, instead the weight and total price displays are continuously updated when the platter is both in motion and at rest. Switch SW9 is the keyboard tare enabling switch. When this switch is ON either a manual tare or a keyboard tare entry is allowed. When the switch is OFF only a manual tare entry is allowed. Switches SW10 and SW11 are provided for testing and checking purposes. Switch SW10 is the automatic zero disabling switch. When this switch is ON the auto zero function is disabled so that the operation of the scale mechanism may be more readily checked. The switch SW11 is the raw weight display switch. When this switch is ON the raw weight as obtained from the analog-to-digital converter is expanded and displayed thus facilitating the servicing, testing, and adjusting of the scale. When these switches are OFF, the scale operates in the normal manner. All of the keyboard and mode switches except SW2 are interconnected with the computer of FIG. 6 through the multiplexing decoders 310, 311, 312, and 313. In addition, four NAND circuits 319, 320, 321, and 322 and two NOR circuits 323 and 324 are provided to interconnect the T1 lead from the analog-to-digital converter, the quarter graduation and the half graduation switches of the keyboard switches, the number nine switch of the mode switch and the one bit line from ROM 3, with the multiplexing decoders 310 and 311 and through these decoders to the computer shown in FIG. 6. The ports of ROM's 1 through 4 inclusive as stated above are arranged to operate as outputs and control the display lamps and seven-segment decimal indicators. As shown in FIG. 5, a set of numerical indicators are provided for a front display 514 and another set 515 for the rear display. Usually the front display is for the customer and the rear display for the clerk or operator of the scale. In the exemplary embodiment of the invention described herein, each of the front and back displays compise a five-digit weight display, a four-digit price-per-pound display and a four-digit total price or value display. Since the seven-segment indicators should be operated alternately one digit at a time, the output ports of ROM 1 are employed to control the B digits or denominational orders in both the front and back displays through the respective seven-segment decoders and drivers 510 and 512. Similarly the output from ROM 3 is employed to control the A and C digits or denominational orders of the indicators through the seven-segment decoders and drivers 510, 511, 512, and 513 are controlled through the transistors 518 and 519 and these transistors in turn are controlled by conductor 520 and NAND gate circuit 418 from the output of ROM 2 as shown in FIG. 4. The seven-segment decoders 510, 511, 512, and 513 supply cathode current to the various segments of the various decimal digits or denominational orders of the front and back displays. The anode current for these various segments of the respective digits is obtained from the driver circuits shown in FIG. 4. These circuits comprise buffer amplifiers 411 through 417, 421 through 427, and 431 through 437. There are seven such amplifiers, shown in FIG. 4, provided for the decimal digits of the front and back displays. These drivers are controlled by the binary coded decimal to decimal decoder and driver 410 which decoder is in turn controlled by the output obtained from the output ports of ROM 2. As shown in FIG. 4, a gate circut 438 is provided which gate circuit is controlled by the output of ROM 3 to provide a blanking signal to the seven-segment decoders and drivers 510, 511, 512, and 513. A set of lamps 430 is provided for both the front and rear displays. The net lamp for both front and rear displays is controlled from driver 429 which is in turn controlled by one of the outputs from ROM 2. The remaining lamps of the display are controlled by the lamp driver 428 which in turn is controlled by the output from the ROM 4. The blanking gate circuit 438 is controlled by the output from ROM 3 as shown in FIG. 4 and in turn controls the seven-segment decoder drivers 510, 511, 512, and 513 to blank the output as will be described herein. The various gate circuits as well as the 8-line to 1-line decoder, the seven-segment decoder, drivers, the various lamp and display drivers are all commercially available and operate in their usual and well understood manner. FIG. 8 shows the information stored at the various locations in the random access memory RAM. Information stored in the read only memory referred to herein as ROM's comprises fixed data and also a series of control orders or instructions for controlling the operating sequence of the computer 116. As is well understood by persons of ordinary skill in the programming and computer art, these series of orders and instructions are employed by the computer 116 and more particularly by the central processing unit 610. These orders and instructions are permanently stored in the ROM's at the time of manufacture in accordance with the desired sequence of operations. If it is desired to change any of the orders or sequence, it is necessary to obtain new ROM's since the original ROM's cannot be changed. The various sequences of orders are sometimes called routines which are familiar to persons skilled in the programming and computer art. In obtaining these routines, a series of flow charts defining the various sequence of operations is usually prepared. These flow charts may then be readily translated into the computer language as required by the particular microcomputer and as set forth in the instructions in the User's Manual for the respective computers. A program listing for performing the operations specified in the flow chart shown in the drawing is attached as an Appendix to this specification. Such a program is in the language required for the MSC-4 microcomputer employed in the exemplary embodiment of this invention as specified in the User's Manual for such MCS-4 microcomputer set. When different computers are employed in combination with the present invention the flow charts will be translated in other computer language specific to the specific computer employed. As indicated in FIG. 8 the RAM is provided with four memory register areas. Each of these register areas is arranged to store four binary digit words which, in the exemplary embodiment described herein, usually are coded to represent a decimal digit. Each of the memory areas is arranged to store 16 of these four binary digit words or other informaion. The RAM 611 also includes four status registers shown in the lower part of FIG. 8. Each of these status registers has an address similar to the corresponding memory register area as indicated above for the status registers. The rectangles in the status registers represent a storage space for a single bit, thus each of the status register may store four 4-digit words. In addition, each of the digits or bits of each of the words may be employed to store a binary bit, which is independent of the other binary bits of the particular word at the particular address. In other words, as indicated, the auto zero sign register 820 is used to store the sign of auto zero correction. While many different arrangements may be employed to store the different information in the register spaces and status registers of the RAM, FIG. 8 shows one suitable arrangement which is employed in the exemplary embodiment of the present invention described herein. Thus the first five words in the register spaces 810 in the first register space (register .phi..phi..phi..phi.) are employed to store the 5 binary coded decimal digits of the raw weight received from the weighing apparatus and are designated raw weight register. The next 5 four bit register word spaces 811 in the first register space are employed to store the five binary coded decimal digits of the previous weight which is employed to determine whether or not the scale platform is in motion or not. The next register space 812 is employed to store the identity of any key of the keyboard which may be found to be depressed or operated. The last 5 four bit word spaces 813 of the first register space .phi..phi..phi..phi. are employed to store the auto zero correction factor. The other portions of the register spaces are similarly employed to store the information as indicated in FIG. 8. The various status register spaces at the bottom of FIG. 8 are similarly designated with the name of the bit or bits employed to record the various information required to provide the various features of the present invention as described herein. Thus the Z key timer 838, together with the control thereof, including the various routines of the program as described herein, comprise timing means for timing the operation of the Z key. As described herein, if the Z key is not held operated sufficiently long, the scale will not be zeroed and placed in condition for operation. Again the Z done flag 839, together with the control thereof, as described herein, provides means for preventing the entry of the unit price and the operation of the scale until Z key and timer have zeroed the scale. This flag also permits the entry of the unit price and operation of the scale system after the Z key has been held operated sufficiently long to zero the scale. The digit timer 830, together with the control thereof, provides means for timing the operation of the digit keys. If these keys are not operated sufficiently rapidly wrong values may be entered. In order to prevent this, the digit timer 830 provides means for insuring that the digit keys are operated in the proper manner to cause the proper entry of information into the scale system. The motion flag 831, together with the control thereof, including the routine sequence of orders, described here, provides means for detecting and registering either motion or no motion of the scale platform. The zero light flag 819, and the control thereof, provides means for turning on or off the zero light. Similarly the other registers, storage spaces and flags provide means for providing the various novel features, operations, and indications described and claimed herein. FIGS. 9A through 9L, show a flow diagram for an exemplary operation sequence for the computer system 116 shown in FIG. 1 which computer system is shown in greater detail in FIG. 6. The flow charts which are diagrammed as shown in FIGS. 9A through 9L consist of a series of blocks having different shapes. The rectangular blocks represent routines of orders for the computer for performing various functions stated in the rectangles. Diamond-shaped blocks represent an order or series of orders for performing a decision or answering a question either by "yes" or "no". Depending on the answer to the question the operating sequence proceeds in either one or the other of two different directions. The hexagonal figures represent a more comprehensive routine such as shown on some one or the other of the FIGS. 9A through 9L. The trapezoidal figures represent input and output operations of the computer equipment. The ovals represent a return to the next order of the main program or routine. All of these operations are common and well known in the computer and computer programming art. In addition, the circles above and to the left represent positions and places for entry into the various operating sequences from other places or positions of the flow charts. The circles to the bottom and to the right represent exit positions or transfer positions to which the sequence of operation is transferred from a circle to a designated circle above or on the left in the same or a different figure. In addition, to the various input and output locations are designated with labels listed in the exemplary program comprising an appendix hereto. The following table B lists various legends as shown on the flow chart and at the end of the list of program orders or instructions stored in the ROM's as shown in the appendix hereto. For convenience in describing and understanding the operation of the exemplary embodiment of the present invention described herein, the flow charts have been divided up into FIGS. 9A-9L.
TABLE B
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ACLCK Auto Clear Check
ADD Label Within SUBTR Denoting Addition Loop
ARICL Arithmetic Work Area Clear Routine
BLNKl Label Within Blank
CAPCK Scale Capacity Check
CKDLY 4 Millisecond delay performed by no Auto Zero
Correction
CKMTN Check for Presence of Motion
CKRCP Check Recompute Flag
CKTl Check for Tl Signal True
CLRSB Clear Memory Field Routine
CLRT Clear Tare Subroutine
CMPUT Compute Total Price
CPBTP Clear Price, Blank Total Price
CRTAZ Correct Auto Zero One Increment
CZTIM Clear Zero Key Timer
DFLT2 Label After DGFLT
DFLT3 Label After DGFLT
DGFLT Output Digital Filter
DLAY4 4 Millisecond Delay Routine
DNORM Normal Display Path
DPSCN Display Scan Loop
DSPLK Link from keyboard to Display
DSPLY Display Routine
DVFY Display Verify Path
D1 Label Within DSPLY
EWSGN Enter Raw Weight Sign and Substract
FINDF Find Factor For Scale Capacity Routine
FTABL Factor Table Used by FINDF
GWMCK Gross Weight Minus Check
HLFCK Check for per 1/2 Key
IDLE Idling Loop Waiting for T1 Signal
IDLLK Link to IDLE
INCZL Increment Zero Lamp Flag Toward O
(Zero Lamp On)
KB0 Label Within Keyboard Routine
KB1 Label Within Keyboard Routine
KB11B Label Within Keyboard Routine
KB11C Label Within Keyboard Routine
KB11D Label Within Keyboard Routine
KB17 Label Within Keyboard Routine
KB18 Label Within Keyboard Routine
KB2 Label Within Keyboard Routine
KB4 Label Within Keyboard Routine
KB5 Label Within Keyboard Routine
KB6 Label Within Keyboard Routine
KB6A Label Within Keyboard Routine
KB6B Label Within Keyboard Routine
KB6C Label Within Keyboard Routine
KB7 Label Within Keyboard Routine
KB7A Label Within Keyboard Routine
KB8 Label Within Keyboard Routine
KSCAN Keyboard Scan Subroutine
LDMEM Load Memory Character Routine
LTMAX Less Than Maximum Auto Zero Value
MANTR Manual Tare
MAXAZ Maximum Auto Zero Check Routine
MCRET Magnitude Check Subroutine Return
MFCTR Multiply Scale Factor Times Raw Weight
MGCHK Magnitude Check Subroutine
MINMI Minuend Minus in SUBTR
MOV4 Move Four Digits Routine
MOV5 Move Five Digits Routine
MTFCK Manual Tare Flag Check
MULT Multiply Routine
MULT1 Label Within Multiply Routine
MULT2 Label Within Multiply Routine
MULT3 Label Within Multiply Routine
MULT4 Label Within Multiply Routine
MULT5 Label Within Multiply Routine
MULT6 Label Within Multiply Routine
NIXZL Set Zero Lamp Flag to Turn Off Zero Lamp
NMOTN No Motion
NOTEQ Not Equal Zero
NOTOT Not 0 Key Followed by T Key
PRCMP Price Computation
PRXWT Multiply Price Times Weight
QSCAN Quick Keyboard Scan
QTRCK Check for Per 1/4 Key
RDINP Read Input
RDT1 Read T1 Signal Routine
RESET Reset Scale
RETN Return From Routine Labels
RETRN Return From Routine Labels
RNDOF Round Off Routine
RNDWT Round Off Final Weight
RNDW1 Label in Round off Final Weight
RNDW2 Label in Round off Final Weight
RNDX5 Round off by 5
ROFF1 Label within RNDOF
ROFF2 Label within RNDOF
RSTLK Link to Reset
SDONE Substact Routine Done
STARE Subtract Tare
STMIN Set Output Weight Minus Sign Routine
STRSB Store Result Routine
SUB Label Within SUBTR Denoting Subtraction Loop
SUBAZ Subtract Auto Zero From Raw Weight
SUBTR Subtract Routine
SUB1 Label in Sub Loop
SUB2 Label in Sub Loop
SWSGN Set Raw Weight Sign and
Update Raw Weight Routine
TARCK Check for Tare Key
UDMTN Update Motion Flag
UDTGT Update Motion Target (previous weight)
VBLLK Link to VBLNK
VBLNK Total Price (value) Blank
VFCKA Label After VFYCK
VFYCK Check for Verify Key
WBLNK Weight Blank
WMGCK Weight Magnitude Check Routine
WREAD Weight Read
WTOUT Weight Output Register Update Routine
XIDLE Expand .times. 10 routine idle with T1 false
ZCAPT Zero Balance Capture
ZLITE Zero Light Update
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OPERATION OF THE SYSTEM Assume now that power has been applied to the scale and the entire arrangement with the result that the load cell and strain gages will generate an output voltage which is applied through preamplifier 112 and the gate circuit 216, to the analog-to-digital converter. The analog-to-digital converter will then start to convert the analog signal to a digital output signal. In addition the power is simultaneously supplied to the computer 116 and to the various input and output circuits cooperating therewith. In addition power is applied to the terminals 622 and 623 of the mono-pulser 621. The application of power to terminal 623 causes capacitor 625 to charge through the charging resistor 624. As a result the upper terminal of capacitor 625 starts to charge to a positive voltage. However, during the charging time of this capacitor, a lower voltage is supplied to the right hand input of mono-pulser 621 and this lower voltage together with the power applied to terminal 622 causes mono-pulser to apply an output voltage or pulse to the base of transistor 626 which transistor in turn causes a reset and clearing pulse to be applied to the clear and reset bus 627 of the computer 116. As a result the various registers, circuits and other elements of the computer are all reset to their initial state and the central processing unit 610 conditioned to read the first program order. During the charging time of the capacitor 625 the diode 628 is back biased so that it does not short circuit or alter the charging resistor 624. However, should power be interrupted, even for a very brief moment, the diode 628 will become conducting and will rapidly discharge the upper terminal of capacitor 624 so that upon the reapplication of power to the system, mono-pulser 621 applies a pulse through the transistor 626 to the clear and reset conductor 627 in the manner described above with the result that the computer circuits are all reset to their initial condition and the central processing unit 610 is again directed to the first order in the zero ROM. The first series of orders or routine to which the central processing unit CPU 610 responds is a reset routine or series of orders called RESET which routine is represented in the flow chart of FIG. 9A beginning in the upper left hand corner of the drawing. Thus the main control is transferred by the pulse on the clear and reset conductor 627 to the input A1 at the top of FIG. 9A. The first rectangle 900 represents the operations to the computer to initialize the various constant pointers or registers and storage spaces in the CPU perform the reset operations. The rectangles 901 and 902 represent the series of ordes or routines within the reset routine which are employed to clear the various register spaces within the RAM 611. Thus the tare weight storage space 814, shown in FIG. 8, is cleared by entering zeros in all of the storage spaces within this tare register. The tare done flag space 815 in the status register space 816 is cleared by recording a zero in this register space. Likewise zeros are stored in the manual tare flag space 818 and in the net lite flag register 817. Likewise the price register 821 and the total price or value register 822 are cleared by recording zeros in all of their register spaces. Also zeros are recorded in the 1/4 register space 824 and in the 1/2 register space 825, in the two digit price flag 827 and in the autoclear flag register space 826. Thereafter the control sequence advances to the routine KSCAN represented by block 904 in FIG. 9A. The KSCAN is employed to scan the keyboard keys to determine which ones if any are operated or depressed. This routine is shown in FIG. 9I. KSCAN ROUTINE The first block 908 of the KSCAN routine directs that the pointers are initialized by transferring the appropriate constants to the registers of the central processing unit so that the various keys 314 except the Z key 315 shown in FIG. 3 will be scanned to determine whether or not any of these keys are depressed. After the pointers are initialized the control is transferred to block 909 which is employed to check key identity register 812 of FIG. 8. Under the assumed conditions this register will be zero so that the control will be advanced to block 910 where the address word identifying the first 4 keys of the keyboard keys 314 is obtained from the memory and then in accordance with block 911 these keys are tested to see if any of the first four keys 0-3 is operated. Assume that none of these keys is operated so that the control sequence then advances to block 912 where it is determined whether or not all of the keys have been checked. On the first cycle of checking, four keys are checked so that all fourteen keys will not be checked with the result that the control is then transferred via transfer 13 back to block 910 where the address word for a second set of the four keys is read out of memory and the keys then tested. This loop is repeated four times to determine whether any one of the fourteen keys 314, except the Z key, 315, is depressed. Under the assumed conditions, none of the keys will be depressed and all of the keys will have been checked by repeating this loop four times with a result that the control advances to block 913 where the key hit register 829 is cleared by entering zeros in all of the register spaces of this register. Thereafter, control is transferred via transfer L11 to the display routine DSPLY. In accordance with the first block 914 (FIG. 9L) of this routine the verifying key 316 is checked. Under the assumed condition this key will not be depressed so that the control is then transferred via L17 to DNORM sequence. The first block 915 of this sequence is employed to check the various flag registers so that the corresponding lamp will be controlled in accordance with the stored information. Then in accordance with block 916 the weight, price, and total price or value will be transmitted to the corresponding displays shown in FIG. 5. Under the assumed conditions zeros will be displayed by all of these displays. Next the output lamps shown at the top of FIG. 4 will be set in accordance with block 917. Under the assumed conditions where zeros were entered in the various registers as described above in accordance with the blocks 901 and 902. The lb. lamp, which is controlled by the motion flag, 831, will be turned on while the net lamp, the 1/4 lamp and the 1/2 lamp will be turned off or remain off. Thereafter the control of the CPU 610 is advanced to block 918 and since no key has been depressed the zero is still recorded in the key hit register 829 so control then is returned to the main program as indicated in block 919. In other words the control then returns to the next operation, block 905 of the main program shown in FIG. 9A. Block 919 causes the control sequences to return to the next operation of the main program which is block 905. This block causes a 5.2 millisecond delay. This time is measured by counting cycles of operation of the CPU unit 610 in the registers within this control unit. At the end of the 5.2 millisecond delay the control sequence advances to block 906 where switches SW6, SW7 and SW9 and the condition of the T1 lead are read into the central control unit 610. Next the control advances to block 907 where the condition of the T1, read by block 906, is determined. If the T1 lead has a zero signal on it indicating that the analog converter has not fully determined a bonified digital output the control is transferred back to block 904 via transfer A4 and the above cycle through the IDLE sequence beginning with block 904, is repeated. That is the above described routines through blocks 908, 909, 910, 911, 912, 913 as well as through the display DSPLY and DNORM routine of blocks 914, 915, 916, 917, 918, and 919 are repeated. This cycle which also includes blocks 905, 906, 907, is then repeated until the analog-to-digital converter has completed a weight conversion, at which time a one signal is applied by the analog digital converter to the T1 conductor. When this signal is recognized by central control unit CPU 610 in accordance with clock 907 the control sequence then advances to block 920 whih causes the CPU 610 to again advance through the KSCAN routine described above. Still assuming that none of the keyboard keys are operated or depressed so the sequence advances to block 919 and then the control is transferred back to the next operation of the main program which will be the operations specified by block 921. In accordance with this block the various settings of the mode or function switches 4, 8, 5, 3, 7, 11, 10, and 1 are determined and stored in the corresponding status registered spaces shown in FIG. 8. The next operation as shown by block 922 is to determine whether or not the digital timer, which employs the register space 830, is performing a timing operation or running. Under the assumed condition the digital timer will not be running so operation is transferred via A15 to blocks 926, 927, 928, and 929 which causes the digital weight signals represented by the five digit weight indications from the analog-to-digital converter to be obtained from the analog-to-digital converter and stored in the raw weight register 810 shown in FIG. 8. As indicated by block 930 the previous raw weight stored in the register 811 of FIG. 8 is then subtracted from the present raw weight register 810. Block 930 causes the CPU 610 to be conditioned to update the motion flag register 831 by storing 14 in a CPU register. Then block 932 then determines whether the result of the subtraction of block 930 is stored in raw weight is greater than 5 counts. Assume that the result is greater than 5 counts since under the assumed conditions when power is first applied all zeros will be recorded in the previous raw weight register 811, consequently the control is transferred to the updating motion sequence via B3 transfer to the block 933 of FIG. 9B. In accordance with block 933 the motion flag register 831 is set to indicate motion by storing 14 in this motion flag register space 831 in RAM 611. In addition, in accordance with block 933, the recomputed flag register 837 is set to order a recomputation. This flag comprises the four status register spaces 837 shown in FIG. 8. From block 933 the control advances to block 9086 which directs the digital timer register to be set to 3. Then control advances to block 934 which causes the present raw weight to be transferred to the previous raw weight register 811. From block 934 control is then advanced to block 935 which causes the initial digital weight to be set to 500 counts. Thereafter the control is advanced to block 939 which determines whether the scale is employed for 15 lbs. or 7 kg and if it is the control is transferred to block 938 via transfer B9. If the scale is not set for 15 lbs. or 7 kg the control advances to block 937 which changes the initial weight to 900 counts and thereafter the control advances to block 938 which causes the digital weight to be subtracted from the raw weight. Next the control advances to block 939 and since the scale is not operating in the expand mode control advances to block 940 via transfer C3. As indicated by block 904 of FIG. 9C the status of the Z key 315 is determined and since it is assumed that this key is not pressed the control is transferred via C11 to block 941 which causes the Z key timer register space 838 to be cleared or set to zero. From block 941 the control advances to block 942 which directs that the keys are again scanned by the key scan KSCAN of FIG. 9I and then control transfers to the display routines of FIG. 9L in the manner described above. The control is then transferred back to the next operation of the main program which is indicated by block 943. In accordance with this block the automatic zero correction stored in the register space 813 is subtracted from the weight stored in the raw weight register. From block 943 control is advanced to block 944 and since the scale is not operating in the auto-zero inhibit mode control then advances to block 947. In accordance with block 947 the CPU 610 determines if the weight recorded in the raw weight register 810 is less than or equal to 4 counts as heretofore processed from the analog-to-digital converter. Assuming that this weight is not less than 4 counts, the zero increment flag is updated by recording .phi. in the zero increment flag register 834 and then the control advances to block 945. Then since the raw weight is greater than 4 counts when the control sequence advances from block 945 to block 946, the control then transfers via transfer D1 to block 960 which causes a 4 ms delay and then control transfers to the KSCAN as indicated in block 956. After the KSCAN and the display routines as described above control returns to block 957 of the main program which transfers control to the FINDF routine. FINDF ROUTINE The Find Scale Factor FINDF routine is provided to first determine which of the four possible capacities is operative for the scale and second to determine the different factors required for this capacity of the scale. The routine is shown in FIG. 9H. The routine sets up a four bit word (with bits designated 8-4-2-1) in which bit 8 is zero, bit 4 is set (i.e. 1) if switch 6 is operated, bit 2 is set (i.e. 1) if switch 7 is operated, and bit 1 is zero. This value is then added to the lower half of an eight bit address which was initially set to the value FTABL (Scale factor table). The pointer may now point to any one of the places in the scale factor table FTABL as shown in the following Table C.
TABLE C
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SW Condition
SW7 Condition
Pointer Value
Scale Capacity
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OFF OFF FTABL 15 .times. .01 lb.
OFF ON FTABL+2 7kg .times. 5g
ON OFF FTABL+4 6 .times. .005 lb.
ON ON FTABL+6 3kg .times. 2g
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The factor word at the pointer address is read out and stored in the various register of the central control unit and the prior address value incremented and the next factor read out and entered in another of the central processing unit registers. These digits or words represent the various constants the computer requires for proper control of the weight output display and for descisions required for proper function and limits of operation. The factors are written in ARI Register shown at 840 in FIG. 8 from the registers in the CPU as shown in the following Table D.
TABLE D
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Scale Capacity
R6 R7 R0 R1 ARI
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15 .times. .01 lb.
1 5 1 1 11015
7kg .times. 5g
7 0 5 2 52070
6 .times. .005 lb.
6 0 5 3 53060
3kg .times. 2g
3 0 2 0 20030
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The FACTOR is employed to multiply the raw weight to obtain the proper display weight, it is employed to determine over capacity of the scale, it is employed again to determine if the raw weight is less than 10 increments for use in the auto clear feature. The factor is also used to determine whether the final raw weight register value should be rounded to zero or five as in the 7 kg or 6 lb. mode or an even number in the 3 kg mode or not rounded for the 15 lb. capacity scale. The factor is also employed to determine the location of the decimal point depending upon the capacity of the scale. It is also used to make sure that a keyboard tare entry is in proper scale increments. In other words the least significant digit is 0 to 5 for the 6 lb. or 7 kg capacity scale. The least significant digit of the keyboard tare entry must be even for the 3 kg capacity of the scale and may be any value for the 15 lb. capacity scale. The tare is accepted as a tare entry only if it meets these conditions of the least significant digit. The flow chart for the FINDF routine is shown in FIG. 9H. In accordance with the first rectangle 9077 the address of the location of the first entry in the factor table stored in the memory of the computer is obtained. Next in accordance with rectangle 9078 a four bit word using the option or mode switches numbers 6 and 7 is formed with the setting of the switches 6 and 7 in the second and third places in this four bit word. Then in accordance with rectangle 9079 this four bit word is added to the address of the first entry of the location of the factor table. The factor table and address and information recorded therein in binary form is shown in the following Table E together with the explanation of this information.
TABLE E
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CPU Registers
Which Receive
Address Stored Information
Information
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FTABL 00010101B 15 lb. .times. .01
R6=1 R7=5
FTABL+1 00000001B FCTR=10 R0=0 R1=1
FTABL+2 01110000B 7kg .times. .005
R6=7 R7=0
FTABL+3 01010010B FCTR=50 R0=5 R1=2
FTABL+4 01100000B 6 lb. .times. .005
R6=6 R7=0
FTABL+5 01010011B FCTR=50 R0=5 R1=3
FTABL+6 00110000B 3kg .times. .002
R6=3 R7=0
FTABL+7 00100000B FCTR=20 R0=2 R1=0
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Then in accordance with block 9080 CPU 610 is directed to indirectly fetch, in accordance with the address determined as above, the information recorded at the address in the factor table. This information is then stored in the computer registers R6 and 7 as indicated in the above Table E. This information is the capacity of this scale. Next in accordance with block 9081 the address or pointer is incremented by one. A second indirect fetch is made by the computer which then in accordance with block 9082 stores the information from the next position of the factor table in registers R0 and R1. This information is the factor by which weight must be modified or corrected to obtain the correct weight output indication, also to check the 10 increment value and over capacity when required as described herein. Then in accordance with rectangle 9083 the information recorded in the registers R0, R1, R6, and R7 is recorded in the ARI register space 840 shown on FIG. 8 in the manner shown in FIG. 10. Thus, the information in register R1 is stored in the first register space in the ARI register. The information in register R0 in the CPU is recorded in the second register space in the ARI register. The information stored in R7 in the CPU is transferred to the fourth register space in the ARI register and the information in register R6 is stored in the fifth space in the ARI register. The information stored in the ARI register space is in the form of binary coded decimal information and is used at later times for determining the over capacity of this scale, the weight output indication, and other weight limits as described herein. For example, for a 15 lb. capacity .phi..phi..phi.1 will be recorded in the first register space in the ARI register space which is the binary coded decimal representation of one. .phi..phi..phi..phi.will be recorded in the second register space in ARI register representing .phi.. .phi.1.phi.1 will be recorded in the fourth register space in the ARI register representing the binary decimal digit 5 and .phi..phi..phi.1 will be recorded in the fifth register space in the ARI register space representing the decimal digit one. For the 7 kg scale capacity .phi..phi.1.phi.recorded in the first register space in the ARI register space which is the binary coded decimal representation of 2. .phi.1.phi.1 is recorded in the second register space in ARI register representing the decimal digit 5. .phi..phi..phi..phi.is recorded in the fourth register space in the ARI register representing .phi. and .phi.111 is recorded in the fifth register space in the ARI register representing 7. In accordance with the block 9084 address pointers are then set up for the information recorded in the ARI register space. These address pointers are shown in FIG. 10 adjacent to the corresponding register spaces in the ARI register space and comprising address numbers 11 through 15. This information is recorded in the memory register 2 and the CPU unit so that this information may be readily obtained when desired. Next in accordance with the block 9085 the control is returned to the next order of the main program after the order directing the transfer to the FINDF routine. Thus control advances to block 958. If the scale capacity is 6 lb. or 7 kg control transfers via transfer 6D to block 962. If the scale capacity is not 6 lb. or 7 kg control transfers first to block 959 and then to block 962. Block 959 causes four millisecond delay which time is determined by counting cycles of the CPU. In accordance with block 962 the raw weight stored in the raw weight register 810 is multiplied by the proper scale factor to obtain the proper output weight. This output weight is then restored in the raw weight register. Control then advances to block 948 where the result of the multiplication is checked to determine if there has been a carry in the sixth more significant digit place. If there has been such a carry, then control transfers via transfer F16 to blocks 9090 and 9091 where the weight output register 836 has blanks stored in it (i.e. 15 or each digit) and the total price register 822 is cleared (i.e. has 0's stored in it). If such a carry does not occur control advances to block 963 where the control again advances through KSCAN routine of FIG. 9I as described above and then through the output routine of FIG. 9L in the manner described above. Next, in accordance with block 949 control advances through the FINDF routine of FIG. 9H in the manner described above. Then the control is returned to the next operation of the main program which operation is designated by block 964. Since the raw weight is not over capacity the control then advances to block 965. In block 965 it is determined whether or not the "zero done flag" has been set. Since, under the assumed conditions, this flag has not been set control then advances via transfer D21 to block 9034 where the price per lb., the fraction factor done flag, the per 1/2 and per 1/4 registers are cleared and the 2 digit price flag is also cleared. Also the total price register 822 has blanks entered in it. From block 9034 control then advances via transfer E1 to block 9097 where the manual tare flag is cleared and the tare subtracted from the raw weight recorded in the raw weight register. Under the assumed conditions the tare is zero. Thereafter the control advances to block 9098 where the CPU operates in accordance with the routine FINDF of FIG. 9H as described above. Thereafter control is returned to the next operation of the main program designated by block 9099. In accordance with block 9099 the CPU unit is conditioned to check if the raw weight is less than or equal to two counts. Control then advances to block 9100. Since the assumed raw weight is not less than 2 counts the control then transfers by transfer E11 to block 950 where the zero light flag register 819 has 14 stored in it which causes the zero light to be turned off. Next, since it is assumed that the raw weight is not less than or equal to ten increments, .phi. is recorded in the R.phi. register in the CPU 610 as indicated by block 954. Then in accordance with block 955 the carry in the CPU 610 is cleared since the auto clear register 826 does not have a 6 stored in it. Then control advances to block 969 and since the weight is assumed to be greater than 10 increments control transfers to block 968 via transfer E20. Since .phi. is assumed to be stored in the auto clear flag register 826 control advances from block 968 to block 970 where the value .phi. in the auto clear flag register 826 is incremented by 1 to 1. The control then advances to block 971 where the various operations of the KSCAN routine are again performed as shown in FIG. 9I and described above. The control then advances to the various display routines of FIG. 9L and then returns to the next operation of the main program designated by block 972 which causes the weight recorded in the raw weight register 810 to be rounded off to the proper value. That is, if the weight in this register is over a half of the least display increment the next higher display digit will be recorded in the raw weight register. Thereafter the control advances to routine 973 which causes the system to progress through various operations of the FINDF routine of FIG. 9H in the manner described herein. After these operations have been performed, the control is then returned to the next operation of the main program designated by block 974. Since the scale is assumed to be operating in a 15 lb. capacity the control then transfers via transfer F3 to block 975 which causes the final raw weight stored in the raw weight register 810 to be subtracted from the output weight stored in the output weight register 836. Next control advances to block 976 and since the motion flag register is now set and has 14 recorded in it the control is transferred via transfer F1.phi. to block 977 which causes the four most significant digits of the raw weight stored in the raw weight register 810 to be transferred to the output weight register 836. Next control advances to block 978 which causes the recompute flag 837 to be set again and the digital filter counter to be cleared by storing a .phi. in the register space 844. Then the control is transferred via transfer F19 to block 9092. Assume that the mandatory price/unit enable switch 3, FIG. 3, is not operated so the 2-digit price flag is clear. Consequently control transfers from block 9092 via F14 transfer to block 979 and, since motion blanking is not enabled, control is advanced via transfer G1 to block 980. Since the recompute flag register 837 is now set, control advances to block 981 and the KSCAN routine of FIG. 9I controls the operations of the CPU as described. This is followed by the sequences of the display routine as described above, since it is assumed that none of the keys are operated at the present time. After the sequences of the display routine have been performed control is then transferred back to the next operation of the main program which is block 982. In accordance with this block the recompute flag register 837 is cleared and control then advances to block 983 and then to block 984 and block 985. Since the output weight is not minus and the auto-zero inhibit mode switch is not actuated under the assumed conditions. Since the tare is assumed to not be mandatory, control is transferred via G8 to block 986 which causes the CPU to again advance through the FINDF routine to FIG. 9H. At the end of this routine control is turned to the next operation of the main program specified by block 987. Block 987 causes the total price pointers and weight decimal point location to be adjusted. Then control is advanced to block 989. Since the per 1/2 or per 1/4 switches are clear control then advances via transfer G14 to block 990. In accordance with this block the price is multiplied by the output weight and the result is rounded off. Block 991 then moves the result to the total price register 822. Under the assumed conditions with no unit prices entered the total price is zero so the control advances through block 992 and block 993 to block 906 via transfer A6. As described above in accordance with block 906 three of the mode switches SW6, SW7, and SW9 are read and also the condition of T1 lead and control advanced to block 907 which determines whether or not a one signal is present on the T1 lead. By the time the control has returned to block 907 in the manner described in T1 lead usually will have the one signal removed from it and will have a zero signal applied to it by the analog-to-digital converter of the FIG. 2. As a result the control transfers to block 904 via transfer A4 and the idle routine or loop repeated as described above until the T1 lead again has a one signal applied to it by the analog-to-digital converter of FIG. 2. When the analog-to-digital converter again applies a one signal to the T1 lead in the manner described above and when the control sequence advances to block 907 the one signal found on the T1 lead at this time causes the control sequence to advance to block 920 and then through the various routines described above with reference to the various blocks of the flow charts. When the control sequence advances to block 931, 14 is entered in the accumulator of the control unit CPU 610 in preparation for setting the motion flag register 831. Assume now that the result of subtracting the previous raw weight from the present raw weight is equal to or less than 5 counts. Consequently, the control sequence advances to block 948 via transfer B1. In accordance with block 948 the motion flag 831 is read and under the assumed conditions 14 will be stored in this storage space so that 14 is read into the accumulator of the CPU unit 610. Next, the control is advanced to block 949. Since the motion flag is not clear the control advances from block 949 to block 950 where the CPU 610 causes the number 14 stored in the CPU accumulator to be incremented by one so that a 15 is now stored in the accumulator. Then in accordance with block 933 the 15 is stored in the motion flag register 831. Thereafter the control sequence advances through the various routines described above and returns to block 904 via transfer A6. Then the sequences follow the idle routine or loop as described until a 1 signal is again applied to the T1 lead. Then the control sequence advances through block 920 and the subsequent blocks in the manner described above. On this cycle through the routine assuming that the weight signals received from the analog-to-digital converter of FIG. 2 have not changed by 5 counts the 15 is stored in the accumulator of the CPU as directed by block 948 will be incremented in accordance with block 950 to 16. However, since the register space 831 of the motion flag stores only 4 binary digits all zeros will be stored in this space in accordance with block 933 with the result that the motion flag is cleared since it has all zeros recorded on it. Consequently on the next sequence through the routine beginning with block 920 when the control sequence advances to block 949 the control is transferred via transfer B5 to block 934 with the result that zero or a clear signal remains stored in the motion flag register 831. If at any time after the no motion signal is obtained as specified by block 932, the raw weight obtained by the analog-to-digital converter differs from the previous raw weight by the predetermined amount which in the exemplary embodiment described herein is 5 counts, then the control sequence advances via transfer B3 to block 933 with the result that the 14 is again stored in the motion flag register space 831 indicating a set condition of this flag. So long as the weight signals received from the analog-to-digital converter vary more than 5 counts from the previous signals in accordance with the exemplary embodiment of this invention, 14 will be continued to be stored in the motion flag register space 831 in the manner described above. If the signals received from the analog-to-digital converter do not vary more than 5 counts during three consecutive cycles of the analog-to-digital converter then the motion flag will be cleared and zeros recorded in the register space 831 in the manner described above. KEY OPERATION Assume now that one of the keys of the keyboard is operated or pressed. Assume, for example, that the numerical 1 key is operated. Then the next time the control sequence advances to the KSCAN subroutine as described above as shown in FIG. 9I the various pointers are initialized as indicated in block 908. Then in accordance with block 909 the ID key identify register is scanned. This register is designated 812 in FIG. 8. Since under the assumed conditions this register will have zeros recorded in it, it will not be set. the control then advances through blocks 910, 911, 912 in the manner described above wherein the keyboard keys are scanned four at a time to determine whether or not any of the keyboard keys are pressed or operated. Under the assumed conditions, upon scanning of the first four keyboard keys, namely, 0, 1, 2, or 3 it will be determined that the one of these keys is operated with the result that the control sequence transfers from block 911 via transfer I8 to the block 9001. This block is employed first to clear the key flag of register 832 shown in FIG. 8. Since it is assumed that all zeros were recorded in these register spaces zeros will remain stored therein. In addition in accordance with block 9001 the various pointers are again initialized so that the keyboard keys will now be scanned one at a time to determine which one of the keys is operated. In initializing pointers, one of the registers of the CPU has stored in it location of the address words designating the various groups of keys. Another one of the registers in the CPU will be employed as a key counter to identify the keys as they are being tested. From block 9001 the control sequence then advances to block 9002 and since an address of the word identifying the first group keys has not been entered in the CPU registers, control will advance from block 9002 to block 9003 where a control word designating the address of the first four keys is entered into the CPU 610. Next control advances to block 9004 where the key count in the register space in the CPU is incremented to zero to indicate that the first or zero key is scanned to be determined whether or not this key is depressed. Under the assumed conditions and it is not depressed so that when control then advances to block 9005 the sequence transfers via transfer J2 to block 9008. Since all 14 keys have not been checked control is then transferred back to block 9002 via transfer I9. Since only one of the four keys designated by the first address word have been tested it is not necessary to read a new key address word into the CPU 610 consequently control transfers to block 9004 again via transfer I11. Block 9004 causes the key count to be incremented to indicate the number one key and then control advances to block 9005. Since it is assumed that the number 1 key is depressed control then advances to block 9006 and as a result the zeros recorded in the key flag register 832 are complimented or changed to one's thus setting the key flag register. Then the control advances to block 9007 and since the key flag is now set control advances to block 9009. In accordance with block 9009 the key hit register 831 is read out and since under the assumed conditions this register is now set to all zeros control then transfers via transfer J1 to block 9010 where the key hit register is set by entering 13 in these register spaces. In addition, the key count in the CPU is transferred to the key ID register 812 indicating that the number 1 key is operated. The control then advances to block 9008 and since all 14 keys are not checked the control then transfers via transfer I9 to block 9002. Since only two keys have been scanned there is no need to read a new key word and control therefore transfers via transfer I11 to block 9004 where the key count register in the CPU is incremented by 1 to indicate the third or number 2 key. This key is assumed not to be depressed so that when control advances to block 9005 control transfers to block 9008 via transfer J2. Since all 14 keys have not been checked control then transfers via transfer I9 back to block 9002. Since the first four keys have not all been checked a new address key word is not required so that the control then advances via transfer I11 to block 9004 where the key count register and the CPU is incremented to indicate the next key. Thereafter, the above described routine is repeated. On the next cycle or sequence checking the keys a new key word will be required and thus the control advances from block 9002 to block 9003 where such a word is obtained and then the control advances to block 9004 and the above key checking routine repeated. These routines are then repeated once for each of the remaining keys and after all fourteen keys have been scanned and only one key found to be depressed, the control advances from block 9008 to block 9011 and since the key flag has been set, as described above, in response to finding the number 1 key depressed the control will be transferred to block 9015 via transfer J7. Since the key hit register has 13 stored in it and not 14 the control then transfers to block 914 via transfer L11 with the result that the display routines are then employed as described above. However, when control advances to block 918 of the display routine of FIG. 9L the key hit register will have 13 recorded in it indicating that this is the first KSCAN which found a key operated. Consequently, control transfers back to the KSCAN again via transfer I1 and the keys are scanned again. Thus when control advances to block 909 the key ID register 812 will be set so the control is transferred to the individual scanning sequence via transfer I8 as described above. In accordance with this sequence the keys are scanned one at a time in the manner described above and upon finding number 1 key depressed when the control sequence is advanced to block 9005 when the number 1 key is scanned control sequence advances to block 9006 and 9007 to block 9009 in the manner described above. However, when the control sequences advance to block 9009 the key hit register 829 will not have a zero recorded in it as described above. Instead, it has 13 recorded in it with the result that the control sequence advances to block 9016. Since the number stored in the key hit register 829 is 13 and not 15, control advances from block 9016 to block 9017 where the number in the hit register 829 is incremented from 13 to 14. Next the number in the key count register in the CPU unit is compared with the number in the ID key identification register 812 and assuming that they are the same indicative that the same key is depressed, the control then transfers via transfer J2 to block 9008 and the remaining keys scanned one at a time in the manner described above. After all 14 the keys are scanned the control advances to block 9011 and then is transferred to block 9015 and since 14 is now stored in the key hit register 829 control advances to block 9019 and since a digit key, namely key 1, is assumed to be depressed the control the advances to block 9020. Under the assumed conditions the digit timer is not running, that is zeros are stored in the digit timer register space 830 of FIG. 8. Consequently the control sequence then advances to block 9021 where the price register 821 and the total price register 822 are cleared as well as the two digit price flag register space 827 and the per half and per quarter register space 825 and 824 in the status register are also cleared. Next the control sequence advances to block 9002 where the digit timer is started by entering 7 in the digit timer space register 830 of FIG. 8. Next block 9023 and 9024 are employed to enter the identity of the pressed key in the price register 821 and then the control is shifted to block 9025 since the price is not greater or equal to 00.10 the control advances to block 9026 where the two digit price flag is cleared by storing a zero in the two digit price flag register space 827. Then the control sequence is transferred via transfer L7 to block 9027 where the test flag is cleared by storing zero in the test flag register space 833 of FIG. 8 and then to block 9014 where the recompute flag is set by writing in one into the recompute flag register space 837 of FIG. 8. Thereafter, the control is transferred back to the main program via transfer A6 and the above cycles of operation repeated. However, the next time the control sequence is transferred to the KSCAN routine, assuming that the number 1 key is still depressed the above described operations of the KSCAN are repeated until the control sequence is advanced to block 9017 of FIG. 9I the key hit register 829 is incremented so that the 14 previously recorded in this register is incremented to 15. Consequently, when the control sequence advances to block 9015 of FIG. 9J 14 is no longer recorded in this register with the result that the sequence is transferred via transfer L11 to the display routine in the manner described above. Thereafter the control is returned to the main program as described. The next time the control is shifted to KSCAN routine and to block 9016, FIG. 9I, thereof, the number recorded in the hit register space 829 will be 15 with the result that the control is then transferred via transfer I18 to block 9018. Consequently, the key hit register 929 is not incremented so that it remains with 15 recorded in it. Thereafter, so long as the key remains operated the sequence control advances through the various routines in the manner described above. Each time the main program sequence advances to block 965, FIG. 9D as described above, which occurs approximately 5 times a second, the zero done flag 839 will not be set. As a result, the program sequence transfers via transfer D21 to block 9034 where the price register 821, the per half flag 825, the per quarter flag 824, and the two digit price flag 827 and the fraction factor done flag 843 of status register FIG. 8 are all cleared and blanks (i.e. 15) are stored in the total price register 822 so that the identity of the value of the key depressed while initially recorded in the price register 821 is cleared therefrom a small fraction of a second after it has been recorded. Thus, the above described sequences are repeated and as described it is impossible to enter any information from the keyboard after power is turned on and until the "Z" key is operated and maintained operated for a predetermined time. Also during this time it is necessary that the no motion condition of the scale platform or platter be maintained as will now be described. OPERATION OF THE "Z" KEY In order to use the scale it is necessary first to operate the "Z" key for a predetermined interval of time during which interval of time it is necessary that the no motion condition of the scale platform or platter be maintained. Such operation of the "Z" key zeros or nulls the scale and places it in condition for use and accurate weighing of anything placed on the platform or platter of the scale. Assume now that the "Z" key is operated and maintained operated for a period of time. Also assume that the next time a 1 signal is applied to the T1 lead by the analog-to-digital converter and the above described subroutine of block 906 and extending through block 932 is employed to control a computer. Assume also that when the control advances to block 932 the difference between the previous raw weight and present raw weight is less than or equal to the predetermined limit indicating no motion which in the exemplary embodiment described herein is 5 counts. As a result control is transferred via transfer B1 to block 948 and then to block 949. Assume further that the scale platform has been within the no motion condition sufficiently long so that the motion flag is clear. As a result when the control advances to block 949 the program transfers via transfer B5 to block 934. Thereafter the control advances from block 934 through block 939 in the manner described above. Since the system is not operating in the expand mode (i.e. mode switch 11, FIG. 3 is not operated), control is transferred via transfer C3 to block 940, which is the beginning of the zero balance capture sequence ZCAPT. Since under the assumed conditions the Z key is operated control is advanced to block 9027 from block 940. Since it also is assumed that the motion flag is not set, control advances from block 9027 to block 9028 and since the tare done flag is not set control advances from block 9028 to block 9029 where the zero key timer is incremented by 2. The zero key timer register space is designated 838, FIG. 8. Under the assumed conditions zeros were previously stored in the Z key timer so that upon the incrementing of this timer by 2, 2 is stored therein in accordance with block 9029 of the flow charts FIG. 9C. The control then advances to block 9030 and since the Z key timer register space 838 does not have zeros recorded in it, control then transfers via C12 to block 942 where control then transfers to the KSCAN as described above. Thereafter the control advances through the various blocks of the various subroutines of the KSCAN and display and then is transferred back to the main program. The control then advances through the main program as described above. It is noted that when the control advances to block 965, FIG. 9D, the Z done flag is still not set to control transfers via transfer D2, as described. The control then advances through the remainder of the main program as described herein. The control is then transferred by transfer A6 to the idle loop or routine comprising blocks 906, 907, 904, and 905 in the manner described above. The next time a 1 signal is applied to the T1 conductor by the analog-to-digital converter the control will advance to block 920 instead of being transferred to block 904 via the A4 transfer. At this time the Z key will still be depressed so that when the control advances to block 904, as described above, control will then advance to block 9027 and since it is assumed that the motion flag is still not set control will be advanced to block 9028 and then to block 9029. In accordance with this block the Z key timer register 838 is again incremented by 2 and then the control advances through the other block subroutines as described and ultimately again returned to the idle routine via transfer A6. Thus each time a one is received over the T1 lead from the analog-to-digital converter of FIG. 2, the Z key timer register 838 is incremented by two under control of the routines specified in block 9029. After 8 times of progressing through the various subroutines in the manner described above the key timer register space 838 will be incremented for the 8th time and returned to zero. However, if during any of these 8 cycles through the various subroutines described above, the motion flag is set due to the fact that the difference between the present and previous raw weight is not less than or equal to 5 counts as required by the subroutines of block 932. Then during such routines when the control is advanced to block 9027 control is transferred via transfer C11 to block 941 which causes the Z key register timer space 838 to be cleared, that is, to be returned to zero. As a result the timing starts over again. Similarly if the Z key is released before the end of the 16 counts recorded in the Z key timer 838, then when the control advances to block 940 control will be again transferred via transfer C11 to block 941 which causes the Z key timer register space 838 to be restored to zero, so that the count will have to be started over again when the Z key is reoperated. However, assume that during the entire 8 counts, that is during 1.6 seconds, the scale platter remains at rest so the motion flag is not set and that the Z key remains operated. As a result when the control advances to block 9030, FIG. 9C, and the zero key timer spaces advance from the 14 count to zero in response to the 8th count control is advanced to block 9031 and under the assumed condition the raw weight will be less than 240 increments so that the control then advances to block 9032 where the raw weight recorded in the raw weight register 810 is transferred to the auto zero register 813 and the sign of the raw weight is transferred to the auto zero sign register 820. Thereafter the control advances to block 9033 which causes the zero done flag to be set. That is a 15 is recorded in the zero done flag register space 839. In addition, the price, total price, the per-half and per-quarter and the fraction factor done flag as well as the two digit price flag are all cleared by recording zeros in these various register spaces to FIG. 8. The zero done flag can only be restored to zero by an interruption of power and then when the power is restored this register space as well as all of the other register spaces are returned to zero as described above. From block 9033 the control sequence advances to block 941 which causes the Z key timer register 838 to be reset to zero. Then control advances to block 942 where the KSCAN routine of FIG. 9I is employed to control the sequence of operations as described above. Control is then returned to block 943. In accordance with block 943 the weight recorded in the auto zero register 813 is subtracted from the weight recorded in the raw weight register 810 and the result, which should be .phi. restored in the raw weight register 810. Control then advances to block 944 and since the scale is not assumed to be operating in the tare zero inhibit mode control advances to block 947. Under the assumed conditions the raw weight is less than 4 counts because in accordance with block 9032 the value recorded in the raw weight register 810 is moved to the auto zero register 813, the previous value of the raw weight recorded in the register 810 being left in this register. Then in accordance with block 943 the value in the auto zero register is subtracted from the value in the raw weight register 810 thus leaving zero recorded in the raw weight register 810. Consequently, from block 947 control advances to block 945 where the zero graduation flag is updated by recording 8 in this register space 834. Control is then advanced to block 946. Since the raw weight recorded in the raw weight register 810 is zero, control transfers to block 960 via transfer D1. In accordance with block 960 a 4 ms delay is provided. Control then advances through the routines of the main program as described above. However, when control advances to block 965 FIG. 9D in the manner described above, the zero done flag will have been set at this time in the manner described above with the result that control is advanced to block 9035 instead of being transferred via transfer D21 to block 9034 and as a result the various registers which were cleared as described above by block 9034 are not cleared since the control does not advance to this block. Instead the control is advanced to block 9035, and since it is assumed that the motion flag is not set, control then advances to block 9036. Under the assumed conditions the zero increment flag will not be set so the control then advances to block 9037. Since the raw weight is equal to zero at this time the control advances from block 9037 to block 9038 which causes various pointers to be set up preparatory to moving the raw weight in the raw weight register 810 to the tare weight register 814. However, the weight in the raw weight register is not moved to the tare weight register at this time. Instead control advances to block 9039 and since the zero light is on at this time control advances to block 9040. In accordance with block 9040 pointers are set up in the CPU unit 610 to prepare for moving zeros in the tare register 814 back to this register. However, this operation does not take place at this time. Instead control advances to block 9041. Since the manual tare flag is not set control transfers via transfer E1 to block 9097 and then advances through the remainder of the routines of the main program. So long as the Z key is held operated the above routines are repeated, first the idle cycles are repeated until a 1 signal is received on the T1 conductor and then the various routines of the main program are repeated as described above. During the program cycle during which the zero done flag is set as described above, the raw weight stored in the raw weight register 810 will be less than 2 counts when control advances to block 9086 so the control then advances to block 9087. Since it is assumed that the scale is a 15 lb. scale control transfers via transfer E8 to block 966. On previous cycles of the main program the zero light flag register 835 was set by recording 14 in this register. Consequently, control advances from block 966 to block 9076. In accordance with block 9076 the zero light flag register is incremented by one from 14 to 15 and then control advances to block 954 via transfer E12 and then through the remainder of the cycle. On the next cycle of the main program, under the assumed conditions the zero light flag will be again incremented by 1 so zero is recorded in this register space thus causing the zero light to be turned on. Thereafter, if the Z key is held operated the various cycles of routines is repeated as long as this key is held operated. After the Z key is released then when control is advanced to block 940 control transfers to block 941 via transfer C11 in the manner described above and the scale is in condition for use. Now when one of the digit keys for example number 2 is operated and the control then transferred to the KSCAN the various routines of the KSCAN as described above are employed to scan the various keys and determine which one is operated. Then the identity of this key is entered in the key identify register 812 when the control is transferred to block 9010 FIG. 9J. Later when the control is advanced to block 9022 the digit timer is started by causing a one to be entered in the digit timer register 830. Then when control advances to block 9023 the value represented by the operated key is entered in the price register 821 in the manner described above. Still later when control has been returend to the main program and advanced to block 965 as described above the control is then advances to block 9035 since the zero done flag has been set by entering 15 in the zero done flag register 839. Thereafter at approximately 0.2 second intervals control is advanced to the block 922 when a one signal has been received on the T1 conductor with the result that control is advanced to block 9051 which causes the digit timer to be incremented by adding one to the value recorded in the digit timer register space 830. At the end of approximately 3.2 seconds this digit timer register space will have advanced to a number 15 and then on the 16th time this register space is incremented it will be returned to the zero since it is a four-digit binary register. If another key has not been operated during this 3.2 seconds then when another key is operated and the control advanced to block 9020, FIG. 9J the digit timer will not be running with result that control is advanced to block 9021 which causes price register 821 and also the tot | ||||||