Subclass 42	Subclass 43	Subclass 44
Including Automatic Teller Machine (i.e., ATM)

Monetary receipt and payment managing apparatus

4001568

Abstract

A monetary receipt and payment managing apparatus operates, when a teller transacts receipt and payment with respect to cash, checks, and bills to classify and operate on data applied according to the contents of the transaction, and to dispense cash necessary for the payment. The apparatus comprises buffer memories for storing the data classified and operated on for individual transaction and main memories for summing and storing the data thus operated on separately according to classification items for every transaction. The operation processing of data on one transaction is assigned to the buffer memories, while the summation and storage of subtotal data on transactions successively transacted are assigned to the main memories, whereby summation data especially important as stored data can be positively secured, and data necessary for automatically dispensing cash on the basis of the contents stored in the buffer memories can be readily and positively obtained.

Claims

We claim:

1. A monetary receipt and payment managing apparatus comprising:

a. transaction classification designating means for designating a transaction classification from among the transactions of monetary receipt, payment, exchange and change, for a transaction to be carried out;

b. transaction item designating means for designating a detailed transaction item for the transaction classification thus designated;

c. numerical data inputting means for inputting numerical data for the transaction item thus designated;

d. start commanding means for commanding starting of the apparatus for carrying out transactions based on input information inputted by said transaction classification designating means, transaction item designating means, and numerical data inputting means;

e. a buffer memory section coupled to said numerical data inputting means, said transaction classification designating means and said transaction item designating means and comprising a plurality of memory circuits which operate to store the numerical data inputted by said numerical data inputting means separately according to the transaction classification and transaction item inputted by said transaction classification designating means and transaction item designating means;

f. a main memory section coupled to said buffer memory section for storing the sum of transaction contents which have been stored in said buffer memory section;

g. money dispensing means in which money with a plurality of monetary denominations is stored, and for dispensing when necessary an amount of money according to the contents of said buffer memory section;

h. a program memory section for storing operation programs provided separately according to the transaction classifications; and

i. an operation control section to which said aforementioned means and sections are coupled for, when the starting of transaction is commanded by said start commanding means, operating to select a necessary operation program according to the contents of said transaction classification designating means, transaction item designating means, and buffer memory section, to effect a predetermined operation process according to the program thus selected, and for summing and renewing the contents of said main memory section on the basis of the contents of said buffer memory section, and for causing said money dispensing means to dispense a necessary amount of money when necessary,

whereby the apparatus collectively manages a variety of monetary transactions carried out by a teller with respect to cash and other than cash such as checks and bills.

2. An apparatus as claimed in claim 1, in which said operation control section comprises:

a. a program address signal forming circuit for temporarily storing information on the transaction classification and transaction item inputted by said transaction classification designating means and transaction item designating means;

b. a decision processing circuit which, based on the contents stored in said main memory section and buffer memory section, when transaction data to be transacted exists in said memory sections, operates to detect the presence of the transaction data;

c. a selection control section for successively selecting the programs required by said program memory section with the aid of outputs of said program address signal forming circuit and decision processing circuit; and

d. an operation control section for applying predetermined operating signals to operating circuits by reading program contents outputted by said program memory section.

3. An apparatus as claimed in claim 2, in which the number of buffer memory circuits correspond to the number of transaction item designating means and said transaction classification designating means is coupled to said buffer memory section and said operation control section for causing, with respect to transactions which cannot be handled simultaneously in one operation by a teller, different operation programs to be selected by signals from the same buffer memory circuits according to a transaction classification specified by said transaction classification designating means, whereby the number of memories can be reduced.

4. An apparatus as claimed in claim 1 which further comprises:

a. a line break protection system for detecting a line break and connecting a power source to devices in said apparatus to be protected; and

b. a data output system coupled to said memory sections and said line break detection system for producing the contents stored in said memories, so that upon occurrence of a line break the contents stored in said main memory are printed out.

Description

BACKGROUND OF THE INVENTION

This invention relates to monetary receipt and payment managing apparatuses which are suitable especially for the transactions of receipt and payment of cash, checks and bills which are transacted by tellers in banking facilities such as banks and also for the receipt of money which is transacted by clerks in monetary charge receiving points in stores.

In general, there are a variety of transactions which are transacted by a teller in, for instance, banking facilities. More specifically in the banking facilities many kinds of legal tender are transferred simultaneously in one transaction, and furthermore various transactions such as receipt and payment of money, money exchanging, and change paying are frequently transacted.

Accordingly, a monetary receipt and payment managing apparatus which deals with these transactions should be able to positively classify and store a varity of data which are applied thereto on the basis of the contents of the various transactions. In this connection, it is desirable that the data thus stored can be taken out and used when necessary. In other words, it is desirable that the data stored in this kind of monetary receipt and payment managing apparatus can be readily utilized for the case where, upon completion of one transaction the correctness of the monetary total of the transaction is certified or for the case where the result of a plurality of transaction transacted successively, that is, for instance the, result of casting the accounts in one day is audited.

Furthermore, it is desirable that in the case when cash is paid in a transactions, money can be automatically dispensed without lowering the classification function of the apparatus described above, from the point of view of improvement of service in the transaction or labor saving.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide a monetary receipt and payment managing apparatus which satisfies the above-described various demands.

More specifically, an object of the invention is to provide a monetary receipt and payment managing apparatus which has a function of classifying and totalizing input data corresponding to receipt and payment of legal tender, and a function of automatically dispensing cash money, thereby to give better service at the window.

Another object of the invention is to provide a monetary receipt and payment managing apparatus in which the number of buffer memories and accordingly the number of peripheral circuits of a memory device are reduced.

A further object of the invention is to provide a monetary receipt and payment managing apparatus which is simple in construction and is accordingly economical.

A still further object of the invention is to provide a monetary receipt and payment managing apparatus in which no interruption of command signals and accordingly re-application of the same is caused for a time period during which a money dispensing machine dispenses money.

A particular object of the invention is to provide a monetary receipt and payment managing apparatus in which data on results of transactions transacted can be positively printed on a journal.

A more particlar object of the invention is to provide a monetary receipt and payment managing apparatus in which data stored in memories is not erased by power troubles.

A specific object of the present invention is to provide a monetary receipt and payment managing apparatus in which in the case of compound transactions for paying money to a customer by the use of a money dispensing machine and handing money directly to him, the data on the transactions can be processed by a common data processing step.

The manner in which the foregoing objects and other objects are achieved by this invention will become more apparent from the following detailed description and the appended claims when read in conjunction with accompanying drawings in which like parts are designated by like numerals or characters.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram showing a preferred example of a monetary receipt and payment managing apparatus;

FIGS. 2 through 7 are also block diagrams illustrating various components of the apparatus shown in FIG. 1;

FIG. 8 is a diagram indicating the relationships in arrangement between FIGS. 2, 3, 4, 5, 6 and 7;

FIG. 9 is a block diagram provided for a description of a memory device shown in FIG. 5;

FIG. 10 is a block diagram illustrating in detail the construction of an address register provided for the selection of main operation branches which is shown in FIG. 4;

FIG. 11 is a table provided for a description of the operation of the address register shown in FIG. 10.

FIGS. 12, 14 and 15 through 21 are diagrams illustrating various forms printed by a printer;

FIG. 13 is a diagram provided for a description of the address operation of a ROM counter shown in FIG. 4.

FIGS. 22 through 27 are block diagrams illustrating in more detail the address register shown in FIG. 10;

FIG. 28 is a diagram indicating the relationship in arrangement between FIGS. 22, 23, 24, 25, 26 and 27.

FIGS. 29 through 32 are block diagrams illustrating in detail the construction of a branch controller shown in FIG. 4;

FIG. 33 is a diagram indicating the relationship in arangement between FIGS. 29, 30, 31 and 32;

FIG. 34 is a block diagram illustrating in detail the construction of a "T" control circuit shown in FIG. 3;

FIG. 35 is a block diagram illustrating a line break operation instruction circuit shown in FIG. 2;

FIG. 36 is a circuit diagram showing in detail the line break operation instruction circuit shown in FIG. 35;

FIG. 37 is a series of graphical representations of various signal waveforms which are utilized for a description of the operation of the line break operation instruction circuit shown in FIG. 36;

FIG. 38 is a block diagram showing one example of a dispensation counter shown in FIG. 6;

FIGS. 39A & B, 40 and 41 are block diagrams showing in detail the dispensation counter shown in FIG. 38; and

FIG. 42 is a series of graphical representations of various signal waveforms which are used for a description of the operation of the dispensation counter shown in FIGS. 39, 40 and 41.

For convenience in drawing, a variety of terms which appear frequently in the accompanying drawings are abbreviated as indicated in a table below when applicable.

    ______________________________________
    Term              Abbreviation
    ______________________________________
    cash receipt        C.R.
    our bank            O.B.
    another bank        A.B.
    money handling      M.H.
    receipt total       R.T.
    payment total       P.T.
    payment             P.
    dispensation        D.
    Total               To.
    exchange            E.
    change              C.
    collation           Co.
    check               Ch.
    receipt             R.
    ______________________________________

DETAILED DESCRIPTION OF THE INVENTION

One preferred example of this invention will be described with reference to the case where it is employed as an apparatus which can classify and totalize the receipt and payment of legal tender such as cash, checks and bills, and can automatically dispense money (the apparatus being referred to as a monetary receipt and payment managing apparatus hereinafter).

In this example, transactions which are transacted most frequently are classified into the following four (4) classification items, that is, transactions of monetary receipt (deposit), payment (withdrawal), exchange, and change transactions.

A. Receipt transaction

According to the kinds of legal tender in a transaction, the receipt transactions are further classified into four sub-classifications, that is,

a. Cash receipt in which cash money is received.

b. Receipt of checks on our bank in which checks and bills on our bank are received.

c. Receipt of checks on another bank 1 in which checks and bills received can be exchanged immediately by banks other than our bank or by a clearing house in which check-issuing banks join.

d. Receipt of checks on another bank 2 in which checks and bills cannot be exchanged immediately by the clearing house.

B. Payment transaction

The payment transactions are further classified into two (2) subclassification items; that is,

a. Cash handing payment in which only cash money is handed to a customer by a bank clerk, and

b. Automatic money payment in which money is paid to a customer by an automatic money dispensing machine.

The automatic money payment (b) described above includes two automatic money dispensation modes; that is,

b-1. A first automatic money dispensation in which money is dispensed separately according to monetary denominations, and

b-2. A second automatic money dispensation (hereinafter referred to as an LCV dispensation when applicable) in which a desired money amount is dispensed with a minimum number of pieces.

C. Monetary exchange transactions

In monetary exchange transactions, money brought by a customer is received, and the exchanged money is automatically dispensed to the customers according to denominations specified by the customer, that is, pieces of money with the denominations specified are automatically dispensed. After it has been detected that the total monetary value of the pieces of money dispensed is equal to that of the money brought, the exchanged money is paid to the customer.

D. Monetary change transactions

For instance in an agent business for collecting public fees, money brought by a customer is received, and the balance between the amount of money thus received and the amount of money to be collected is paid to the customer by the LCV dispensation.

The apparatus positively carries out the four kinds of business transactions (A), (B), (C) and (D) classified as above, and furthermore readily carries out various checking operations in monetary management such as certification printing, record printing and collation confirming operations separately according to the classification items described above.

The apparatus, as is shown in FIG. 1, comprises a command input system 1 which is operated by an operator to introduce data and instructions necessary for the transaction of various transactions such as receipt and payment transactions to a memory operation processing system 3 which stores the data applied by the command input system 1 and operates on the data according to programs provided corresponding to the various transactions, a program addressing system 2 which is adapted to transfer the data from the system 1 to the system 3 and to address a program to be executed for the system 3, an automatic money dispensing machine 4 for automatically dispensing money with denominations and numbers of pieces in response to an operation result of the memory operation processing system 3, and a data output system 5 which operates to display and/or print an operation result of the memory operation processing system 3. The command input system 1 and the program addressing system 2 form a data input system 8 in the apparatus.

1. Command input system 1

The command input system 1 carries out the introduction of classification data and registration data which are assigned separately to the transactions, and comprises the following elements.

1-1. Operation mode specifying device 11

An operation mode specifying device 11, as in shown in FIGS. 2 and 3, is provided with a plurality of key-switches G.sub.1 through G.sub.4 corresponding respectively to the transaction classifications.

The group of key-switches G.sub.1 are operated in the transaction of the receipt transaction, for classifying the receipt transaction (hereinafter referred to as a group of receipt business classifying key switches G.sub.1 when applicable), and comprises a "cash" switch 11A, an "our bank" switch 11B, an "another bank 1" switch 11C and an "another bank 2" switch 11D which correspond, respectively, to the kinds of legal tender brought by customers, that is, the subclassification items (a), (b), (c) and (d) in paragraph (A) above.

The group of key switches G.sub.2 is provided for classifying the payment transactions (hereinafter referred to as a group of payment business classifying key-switches G.sub.2), and are operated when cash is handed by a bank clerk to customers, and includes a "handing" switch 11E.

The group of key-switches G.sub.3 is operated for classifying the payment of money when money is to be dispensed by the first automatic money dispensation (hereinafter referred to as group of payment money classifying key-switches G.sub.3), and comprises a "10000-yen" switch 11F, a "5000-yen" switch 11G, a "1000-yen" switch 11H and a "500-yen" switch 11I which correspond to 10000-yen, 5000-yen, 1000-yen and 500-yen notes, respectively, in this example.

The group of key-switches G.sub.4 is provided for classifying supplementary transactions (hereinafter referred to as a group of supplementary transaction classifying switches G.sub.4 when applicable). These key-switches G.sub.4 are operated when the exchange and change transactions are transacted, and comprises an exchange switch 11K and a change switch 11L which correspond to the exchange and change transactions, respectively. These key-switches G4 further comprise a non-addition mode selection key-switch 11J (hereinafter referred to as a T switch 11J) which is provided for selecting a zero proof operation mode of the memory operation processing system 3 in the transaction of the exchange and change transactions. In this example of the apparatus, the memory operation processing system 3 is so designed that it will carry out an addition operation if the "T" switch 11 is not operated.

The groups of key switches described above are operated for every transaction so that the transactions are classified according to the sub-classification items, that is, the key-switch groups are operated separately according to the sub-classification items. As a result, an operation processing by the use of a buffer memory (hereinafter referred to as a buffer operation), such as writing, operating and rewriting of data in the buffer memory which is built in the memory operation system 3 can be carried out by the operations of the above-described key-switches, as will become apparent later.

The command input system further comprises groups of keyswitches G.sub.5 and G.sub.6, and circuit R.sub.11 and G.sub.7 in order to carry out an operation processing by the use of a main memory (hereinafter referred to as a main operation) which will be described later.

The group of key-switches G.sub.5 are provided for main memory instructions. These switches G.sub.5 are operated for every transaction to produce the results of the transaction transacted. More specifically, the group of key-switches G.sub.5 comprises classification item switches, that is, a receipt total switch 11M which provides a subtotal in one transaction in which monetary receipt is conducted, and a payment total switch 11N which provides a subtotal in one transaction in which payment is conducted. The group of key-switches G.sub.5 further comprises a payment (which term in this case is intended to designated the fact that money dispensed by the money dispensing machine is paid to a customer) key-switch 110 which is provided for starting the operation of the automatic money dispensing machine 4.

The group of key-switches G.sub.6 are provided for main memory operation instructions so as to produce a monetary total of transactions transacted to one day. The group of key-switches G.sub.6 comprises a "total/No." switch 11P (in which the symbol "No." means non-addition operation) and an "audit" switch 11Q which is a change-over switch connected in parallel to the switch 11P. In the case of producing a total money amount, the total/No. switch 11P is closed after the "audit" switch has been switched over to its contact ON, whereby the application of a total operation instruction is effected.

Reference character 11R designates a line break for instance, an interruption of the power supply operation instruction circuit. This circuit 11R is designed so as to receive a line break operation instruction (hereinafter referred to as an LB operation instruction) which produces a predetermined memory data of the main memory with the aid of a line break signal obtained by a line break protection circuit (which will be described later) when the electric source is turned off.

Reference symbol G.sub.7 designates a certification printing operation instruction circuit in which the application of a main operation instruction with respect to the printing of data on a certification printing slip is effected. In this example, if an output is produced by a certification printing slip insertion detector 11T which operates to detect the fact that the certification printing slip is inserted in a certification printing chute section (not shown) described later, a strobe signal generating circuit 11U generates a strobe signal (hereinafter referred to as a certification printing slip removal strobe generating circuit 11U when applicable) when the slip is removed from the chute section, this strobe signal is employed as an operation instruction which after the date has been printed on the certification printing slip, causes the same data to be printed again.

Furthermore, the receipt total and payment total switches 11M and 11N are so designed that if the certification printing slip is inserted, the application of "receipt total" on "payment total" operation instruction is effectd with the aid of the output of the detector 11T.

1-2. data read-in control circuit 12

A data read-in control circuit 12 for applying numerical data is provided with a ten-key device 12A comprising ten key-switches which correspond respectively to numerals 1 through 0 as is shown in FIG. 3. The outputs of the ten-key device 12A are transmitted through a key input circuit 12B. The ten-key device 12A is employed to achieve the registration of money amounts in the transaction of the receipt, payment, exchange and change transactions, and the registration is accomplished by selectively depressing the switches of the ten-key device 12A corresponding to the numerals which indicate a desired money amount. In this case, the depression of the key-switches should be started with a key-switch corresponding to the most significant digit of the money amount.

Similarly as in the case described above, the registration with respect to a date/serial number and an account number can be accomplished.

In connection with the ten-key device, a 000/. switch 12C is provided. The output of this switch 12C is applied through a decimal point shifting switch 12D to a three-shift control circuit 12E or a decimal point shifting control circuit 12F. When the armature of the switch 12D is on its contact 000, a registration data 000 is obtained. On the other hand, when the armature of the switch 12D is on the contact DP, an instruction output is obtained which operates to cause the decimal point of data registered by the ten-key device to be shifted by, for instance, two higher places in the printing of the data.

1-3. Buffer operation instruction control circuit 13

A buffer operation instruction control circuit 13 is provided to instruct the start of a buffer operation as to money amount data registered by the ten-key device. The circuit 13 comprises a + switch 13A which is an instruction key-switch for the execution of operation in an addition mode, and a - switch 13B which is also an instruction key-switch for a subtraction operation. The outputs of these switches 13A and 13B are transmitted as buffer operation start instructions through key input circuits 13C and 13D, respectively.

1-4. Management instruction control circuit 14

A management instruction control circuit 14 is provided to effect the application of instructions concerning operations which is necessary for monetary management, and comprises the following input elements.

A collation switch 14A is operated to check as to whether or not there is any mistake in registration operations and the like upon completion of one transaction. The output of the switch 14A, as is shown in FIG. 3, is transmitted as a collation instruction signal through a key input circuit 14B.

The control circuit 14 further comprises a date switch, or a keyswitch 14C, which operates to set a date and a serial number indicating a transaction number when the transaction is started for a day. In this example, the switch 14C, as is shown in FIG. 2, is provided in series with the contact OFF of the audit switch 11Q so that the audit switch 11Q and the total/No. switch 11P are used as input means. When the total/No. switch 11P is closed with the audit switch 11Q turned off, a set instruction signal for a date/serial-number is transmitted through a key input circuit 14D.

In order to apply an account number of a customer, there is provided an N switch 14E which is a key-switch. Similarly as in the case of the date switch 14C, the switch 14E is connected in parallel with the date switch 14C so that the audit switch 11Q and the total/No. switch 11P are employed as input means also. The keyswitch 14C is adapted to transmit a set instruction signal of an account number through a common key input circuit 14D. The date switch 14C and the N switch carry out mechanically opposite operations. More specifically, the N switch 14E is in the on state while the date switch 14C is in the off state for a normal time period during which the date/serial number date are not applied.

2. Program addressing system 2

This program addressing system 2 has a first function to transmit registration data in the data read-in control circuit 12 to the memory operation processing system 3 and a second function to transmit a program address signal for specifying a program corresponding to an operation mode which is specified by the operation mode specifying device 11 from among a number of programs which are fixedly stored in the system 3. The system 2 comprises the follow-elements.

2-1. Program address signal forming circuit 21

This program address signal forming circuit 21 receives the output of the operation mode specifying device 11 and produces a program address signal corresponding to the output thus received, thus to fulfill the second function described before. This circuit 21, as is shown in FIGS. 2 and 3, includes a plurality of memory groups.

One of the memory groups is a group of receipt classification item memories H.sub.1 corresponding to the group of receipt transaction classifying key-switches G.sub.1. That is, the memory group H.sub.1 comprises cash receipt, our bank, another bank 1 and another bank 2 memories 21B, 21C, 21D and 21E which are set through a key input circuit 21A with the aid of the outputs of the cash, our bank, another bank 1 and another bank 2 switches 11A, 11B, 11C and 11D. Classification item signals selected are produced from the memories thus set, respectively.

Another one of the memory groups is a group of payment transaction classification item memories H.sub.2 corresponding to the group of payment transaction classifying key-switches G.sub.2. This memory group is provided with a handing memory 21G, which is set through a key input circuit 21F with the aid of the output of the handing switch 11E.

Another one of the memory groups is a group of payment transaction classification item memories H.sub.3 corresponding to the group of payment transaction classifying key-switches G.sub.3. This group H.sub.3 comprises 10,000-yen note, 5,000-yen note, 1,000-yen note, and 500-yen note memories 21I, 21J, 21K and 21K, which are set through a key input circuit 21H with the aid of the outputs of the 10,000, 5,000, 1,000 and 500 switches 11F, 11G, 11H and 11I, respectively.

Another one of the memory groups is a group of supplement transaction classification item memories H.sub.4 corresponding to the group of key-switches G.sub.4 described before. This group H.sub.4 comprises T, exchange and change memories 21M, 21N and 21O (FIG. 3) which are set by the outputs of the T, exchange and change switches 11J, 11K and 11L. The exchange and change memories 21N and 21O are set by the output of the T memory when the latter is set. Furthermore, a zero proof operation instruction is produced from a T control circuit 21P with the aid of the output of the T switch 11J, and the outputs of the memories 21N and 21O are produced as classification item signals in the same manner as described above.

The T control circuit 21P is a peripheral circuit of the group of memories H.sub.4 and is adapted to transmit operation instructions and control signals T.sub.1, T.sub.2 and T.sub.3 which are necessary for the transaction of the supplementary transactions, that is, the exchange and change transactions, as is shown in FIG. 34.

In this example, the T, exchange and change memories 21M, 21N and 21O are flip-flop circuits. The T memory 21M is immediately set by the output TK of the T switch 11J through an input logical product gate circuit 211, and the set output of the T memory 21M is transmitted as a zero proof operation instruction T.sub.1.

The change memory 21O is set by the output CHAK of the change switch 11L through an input logical product gate circuit 212 under the condition of (CHAK).sup.. (EXC).sup.. (ICF) T.sub.1, and the set output of the exchange memory 21O is transmitted as an exchange classification item signal CHA.

The exchange memory 21N is set by the output EXK of the exchange switch 11K through an input logical product gate circuit 213 under the condition of (EXK).sup.. (ICF).sup.. T.sub.1, and the set output of the memory 21 is transmitted as an "exchange" classification item signal EXC.

In the above description, the reference character ICF designates a receipt item specifying signal which is delivered from a receipt item specifying signal forming circuit 111 (FIG. 31), and this signal is generated when operation instructions concerning the receipt items (that is, the outputs CAF - AB.sub.2 F of the cash receipt - another bank 2 memories 21B - 21E) are obtained during the buffer operation.

The T control circuit 21P has a signal forming circuit 214, which is a flip-flop circuit, for generating the operation instruction T.sub.2. This circuit 214 is set through an input logical product gate circuit 215, which is provided for the exchange transaction, when the T switch 11J is depressed again under the condition of (CHA).sup.. TK. Furthermore, the circuit 214 is set through an input logical product gate circuit 216, which is provided for the exchange transaction, when the T switch 11J is depressed again under the condition of (EXC).sup.. TK. The set outputs T.sub.2 of the circuit 214 are transmitted, as an addition operation instruction of the "collation" buffer memory B.sub.1 and a printing execution instruction of the data output system 5, to an instruction selection decoder 34F and a branch and step control circuit 34E in an operation instruction circuit 34 (FIG. 4) described later. This operation instruction T.sub.2 is employed as a reset signal for the cash receipt memory 21B.

The T control circuit 21P is provided with a signal forming circuit 217, which is a flip-flop circuit, for generating the control signal T.sub.3. This circuit 217 is set through an input logical product gate circuit 218 when the - switch 13B is depressed under the condition of (NK).sup.. T.sub.1, where NK is the key-out signal of the switch 13B. The set output T.sub.3 of the circuit 217 is applied, as a buffer operation start condition, to a buffer operation start circuit 34G (FIG. 4) described later, and is also applied, as an operation instruction which is adapted to read-in registration data with a negative sign, to an instruction selection decoder 34F. The signal T.sub.3 is furthermore applied, as a printing execution signal, to the branch and step control circuit 34E (FIG. 4).

The signal (T.sub.2) forming circuit 214 is reset through a resetting logical product circuit 219 by a paper feeding signal PF which is generated whenever one line of printing is accomplished by a printer 52. The signal (T.sub.3) forming circuit 217 is also reset by the paper feeding signal PF through a resetting logical product circuit 220 and is also reset by the output CHA of the change memory 210 or the output EXC of the exchange memory 21N.

The T control circuit 21P (in FIG. 34) operates as follows, on the basis of the fact that the key outputs TK, EXK and CHAK of the T, exchange and change switches 11J, 11K and 11L and the key-out output NK of the - switch 13B are successively applied thereto.

When the output TK of the T switch 11J is applied to the T control circuit 21P under the condition that the latter is in the reset state, the T memory 21M is set, and thereafter the output T.sub.1 of the T memory 21M is maintained until the latter is reset by a clear key output CK.

Thereafter, upon arrival of the output NK of the - switch 13B, the signal (T.sub.3) forming circuit 217 is set by the output NK through an input gate circuit 218, to produce the output T.sub.3.

Thereafter, upon arrival of the output CHAK of the change switch 11L (or the output EXK of the exchange switch 11K), the change memory 210 (or the exchange memory 21N) is set under the condition that the receipt item signal ICF (or ICF) has arrived through an input gate circuit 212 (or 213), and the change classification item signal CHA (or the exchange classification item signal EXC) is transmitted.

When under these conditions the output TK of the T switch 11J is applied again, the signal (T.sub.2) forming circuit 214 is set through an input gate circuit 215 (or 216), thereby producing the signal T.sub.2.

The signal forming circuits 214 and 217 thus set are reset by the paper feeding signal PF which arrives first after the circuits 214 and 217 have been set.

Thus, in the T control circuit 21P, the output T.sub.1 is produced for a period during which the change (or exchange) transaction is transacted. During this period, first, the output T.sub.3 is produced, and then the resetting operation is conducted by the paper feeding signal PF. Thereafter the change classification item signal CHA (or exchange classification item signal EXC) is produced, and then the output T.sub.2 is produced. Thereafter the resetting operation is conducted by the paper feeding signal PF.

The program address signal forming circuit 21 further comprises a group of main memory operation instruction memories H.sub.5 which correspond to the groups of key-switches G.sub.5 and G.sub.6 and the line break operation instruction circuit 11R. This group of memories H.sub.5 comprises: a receipt total memory 21R; a payment total memory 215 and a payment (which is, in this case, intended to designate that fact that money dispensed by the money dispensing machine is paid to a customer) memory 21T which are set through a key input circuit 21Q by the outputs of the receipt total; payment total and payment switches 11M, 11N and 11O, respectively; a total memory 21U which is set through the circuit 21Q by the output of the total/No. switch 11P, which output is obtained through the contact ON of the audit switch 11Q; and an LB memory which is set through the circuit 21Q by the output of the line break operation instruction circuit 11R. The payment memory 21T is set under the condition that the payment total memory 21S produces a set output.

The program address signal forming circuit 21 further includes a group of main operation instruction memories H.sub.6 which are provided for carrying out a confirmative printing on a journal after a certification has been printed on the certification printing slip. These memories H.sub.6 are provided in connection with a certification printing operation instruction circuit G.sub.7 and comprise a V (verification) receipt total memory 21W and a V payment total memory 21X which are provided for the printing operations of monetary receipt and payment, respectively.

The set outputs of these groups of memories H.sub.5 and H.sub.6 are applied to an instruction branch start circuit 21Y, which operates to apply a main operation start signal and a main branch selecting condition to the memory operation processing system 3. The main branch selecting condition is to select a proper main branch according to the contents of the set output applied to the instruction branch start circuit 21Y.

2-2. data read-in decoder 22.

This data read-in decoder 22, as is shown in FIG. 4, operates to convert into predetermined formats registration data obtained through the key input circuit 12B by the ten-key device 12A (FIG. 3) and also registration data obtained by the three-shift control circuit 12E, respectively, and to apply the conversion outputs thus obtained, as registration data and a decimal point signal, to the memory operation processing system 3, thereby to effect the first function described before.

3. Memory operation processing system 3

The memory operation processing system 3 operates to effect the storage and operation of data applied by the data read-in decoder 22 with the aid of the output of the program addressing system 21 and the outputs of the buffer operation instruction control circuit 13 and management instruction control circuit 14 in the command input system, and to transmit drive instructions and data to the money dispensing machine 4 and the data output system 5.

The memory operation processing system 3 comprises the following elements as is shown in FIGS. 4 and 5.

3-1. Memory device 31

A memory device 31 comprises: a buffer memory section BU which operates to store data applied in one transaction and to obtain a subtotal of the money amount for every classification item; and a main memory section MM which operates to store the results of additions of the data applied to the buffer memory section BU thereby to obtain a total money amount for every transaction classification at the time when the accounts are cast up. These memory sections BU and MM are constituted by, for instance, volatile memories.

The buffer memory section BU, as is shown in FIG. 9, is provided with a collation buffer memory B.sub.1 which is common for all of the classification items, and four buffer memories B.sub.2 through B.sub.5 which are adapted to store data separately according to the classification items (that is, the monetary denominations). Both data on the receipt of cash and data on the payment (LCV) by the first automatic money dispensation are applied to the buffer memory B.sub.2. Similarly as in the case of the buffer memory B.sub.2, data on the receipt of checks on our bank, data on the payment of 5,000-yen notes and data on the transaction of change money are applied to the buffer memory B.sub.3. Furthermore, data on the receipt of checks on another bank 1 and data on the payment of 5,000-yen notes are applied. Data on the receipt of checks on another bank 2 and data on the payment of 500-yen notes are applied to the buffer memory B.sub.5. In addition, data on the subtotal of one transaction is applied, for instance in a series mode, to the buffer memory B.sub.1 for every classification. For instance, a 1024-bit shift register can be employed as the buffer memories described above.

The data on the receipt of cash, the data on the payment by the first automatic money dispensation, the data on the payment by the second automatic money dispensation and the data on the transaction of change money are provided in duplicate to these buffer memories B.sub.2 - B.sub.5 provided for the respective classification items because these data are not processed at the same time.

The contents in the buffer memories are renewed upon application of the next data.

The main memory section MM comprises main memories M.sub.1 through M.sub.6 which operate to store the results of additions of data provided separately according to the classification items, respectively, and a date/serial number main memory which operates to store data on dates and serial numbers.

The data on the receipt of cash is applied to the cash receipt main memory M.sub.1. The data on the receipt of checks on our bank is applied to the our bank main memory M.sub.2. The data on the receipt of checks on another bank 1 is applied to the another bank 1 main memory M.sub.3. Similarly, data on the receipt of checks on another bank 2 is applied to the another bank 2 main memory M.sub.4. Data on the automatic money dispensation is applied to the automatic dispensation main memory M.sub.5. Data on the total of cash payments which are dispensed by the money dispensing machine and handed to customers by bank clerks is applied to the cash payment main memory M.sub.6.

In each of the main memories, when a transaction has been transacted, the contents stored therein are renewed only by the result of addition of a subtotal monetary data (stored in the collation buffer memory B.sub.1) for this transaction and the data which has been stored therein before the transaction. Otherwise, the contents of the main memories are never renewed.

The data in the main memory section MM and buffer memory section BU is as indicated below:

    ______________________________________
    Instruction Registration  Sign for
    word        data          decimal point
    ______________________________________

The instruction words include the classification item to which the registration data belong, an address to be stored in the memory device, and operation step selecting conditions.

3-2. Decision processing circuit 32

A decision processing circuit 32 operates to read and store the contents of the instruction word in the data stored in the memories of the memory device 31 and comprises a decision circuit 32A and a condition memory 32B.

The decision circuit 32A operates to decide whether or not instruction words are included in the contents stored in the memories. In the case where data are stored in the memories, the decision circuit 32A operates to transmit decision outputs separately with respect to the memories.

The condition memories 32B, as is shown in FIG. 9, comprise twelve flip-flop circuits JG.sub.1 through JG.sub.12 which are adapted to store the decision outputs of the decision circuit 32A (not shown in FIG. 9). When the data has been stored in the buffer memories B.sub.1 through B.sub.5, the condition memory 32B operates to transmit condition outputs jg.sub.1 through jg.sub.5 indicating the presence of data in the memories from the circuits JG.sub.1 through JG.sub.5, respectively. Similarly, when the data has been stored in the main memories M.sub.1 through M.sub.7, the condition memory 32.sub.B operates to transmit condition outputs jg.sub.6 through jg.sub.12 indicating the presence of data in the memories from the circuit JG.sub.6 through JG.sub.12, respectively.

3-3. Main operation branch selection address register 33

A main operation branch selection address register 33 (FIG. 10) operates to sequentially specify an operation program (that is, a main branch) corresponding to the contents of an instruction which has been specified by the program address signal forming circuit 21, by employing the condition outputs jg.sub.1 through jg.sub.2 of the decision processing circuit 32 as branch selection conditions and also employing as selection conditions the main branch selection signals of the program address signal forming circuit 21 (FIG. 2) and the position detection signal S.sub.14, S.sub.53, S.sub.13 and S.sub.52 which are provided separately according to the monetary denominations by the money dispensing machine 4.

The address register 33, as is shown in FIG. 10, is provided with a matrix circuit 33H having an address output circuit 33I which comprises output holding circuits 33A through 33G provided respectively for address selection output lines N.sub.1 through N.sub.7.

When main operation instructions whose contents represent respectively the receipt total, payment total, payment, LB, total, V receipt total and V payment total are applied to the circuit 33H from the instruction branch start circuit 21Y, as is indicated in FIG. 11 the selection output lines N.sub.1 through N.sub.7 are selected according to the outputs of the decision processing circuit 32 (that is, the contents stored in the memory device 31) in order to successively specify the operation program (that is, the main branches) to be executed by the main operation instructions.

One example of the address register 33 is shown in FIGS. 22 through 27. In this example, the matrix circuit 33H comprises an address selection circuit 311, a priority order setting circuit 312 and an address output circuit 33I.

The address selection circuit 311 operates to select a main operation main branch which is necessary for processing data according to the contents of transactions, by selectively specifying the address signal output lines N.sub.1 through N.sub.7. In this selection, the condition outputs of the decision processing circuit 32, the main branch selection condition signals of the program address signal forming circuit 21, and the predetermined position detection signals provided separately according to the denominations from the money dispensing machine 4 are employed as selection conditions.

The address selection circuit 311 comprises: condition circuits 323, 327, 331 and 334 (which are, for instance, logical product circuits) which are operated in the main operations concerning the receipt total and V recept total; and a condition circuit 324 which is operated in the main operations concerning the payment total and V payment total. The circuit 311 further comprises; condition circuits 322, 326, 330 and 333 which are operated in the main operation concerning the payment in the first automatic money dispensation; condition circuits 325, 329, 332 and 335 which are operated in the main operations concerning the total and LB; a condition circuit 321 which is operated in the main operation concerning the payment by the LCV dispensation; and condition circuits 323 and 328 which are operated in the main operation concerning the change. The conditiion circuits described above are similar in construction to one another.

In order to select the output line N.sub.1, the condition circuits 321 through 325 produce output signals h.sub.1 through h.sub.5, as address selection output, which are indicated by the fllowing logical expressions.

h.sub.1 = q.sub.1 (LCVF) (DIP) = (CHA) (jg.sub.2) (LCVF) (DIP)(1)

h.sub.2 = q.sub.1 (S.sub.14) (DIP) (LCVF) = (CHA) (jg.sub.2) (S.sub.14) (DIP) (LCVF) (2)

h.sub.3 = (q.sub.1 + q.sub.2) { (IAF) + (IVF)} = {(CHA) (jg) + (CHA) (jg.sub.2) (DIP)} = {(IAF) + (IVF)} (3)

h.sub.4 = (OAF) + (OVF) (4)

h.sub.5 = (jg.sub.6) {(TMF) + (LBF)} (5)

in order to selectively specify the output lines N.sub.2, the condition circuits 326 through 329 produces output signals h.sub.6 through h.sub.9, as address selection signals, which are indicated by the following logical expressions.

h.sub.6 = q.sub.3 (S.sub.53) (DIP) (LCVF) = (CHA) (jg.sub.3) (S.sub.53) (DIP) (LCVF) (6)

h.sub.7 = q.sub.3 {(IAF) + (IVF)}= (CHA) (jg.sub.3) {(IAF) + (IVF)}(7)

h.sub.8 = q.sub.4 (LCVF) = (CHA) (DIP) (jg.sub.3) (LCVF) (8)

h.sub.9 = (jg.sub.7) {(TMF) + (LBF)} (9)

in order to selectively specify the output line N.sub.3, the condition circuits 330 through 332 transmit output signals h.sub.10 through h.sub.12, as address selection signals, which are indicated by the following expressions.

h.sub.10 = (jg.sub.4) (DIP) (LCVF) (S.sub.13) (10)

h.sub.11 = (jg.sub.4) {(IAF) + (IVF)} (11)

h.sub.12 = (jg.sub.8) {(TMF) + (LBF)} (12)

in order to selectively specify the output line N.sub.4, the condition circuits 333, 334 and 335 operate to transmit output signals h.sub.13, h.sub.14 and h.sub.15, as address selection signals, which are indicated by the following logical expressions.

h.sub.13 = (jg.sub.5) (S.sub.52) (DIP) (LCVF) (13)

h.sub.14 = (jg.sub.5) {(IAF) + (IVF)} (14)

h.sub.15 = 'jg.sub.9) {(IMF) + (LBF)} (15)

in connection with the logical expressions described above, LCVF represents the output of an LCV flag circuit 37D, and IAF, IVF, TMF, LBF, OAF, OVF and DIP represent the set outputs of the receipt total, V-receipt total, total, LB, payment total, V-payment total and dispensation memories 21R, 21W, 21U, 21V, 21S, 21X and 21T, respectively. Furthermore, jg.sub.2, jg.sub.3, jg.sub.4, jg.sub.5, jg.sub.6, jg.sub.7, jg.sub.8 and jg.sub.9 represent the condition outputs which are obtained from the decision processing circuit 32 on the basis of the fact that the data has been stored in the buffer memories B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8 and B.sub.9, respectively, while CHA represents a control signal which is produced by the T control circuit 21P when the change memory 120 has been set. In addition, S.sub.14, S.sub.53 and S.sub.13 represent predetermined-position detection signals which are produced by a money dispensation control section 43 separately according to the denominations when a money dispensation mechanism reaches the money dispensing positions of the 10,000-yen, 5,000-yen, 1,000-yen and 500-yen note containers in the money dispensing machine 4 which will be described later.

Moreover, q.sub.1, q.sub.2, q.sub.3 and q.sub.4 represent the outputs of gate circuits 341 through 344 which are provided for obtaining the condition inputs of the output lines N.sub.1 and N.sub.2, respectively, and are indicated by the following logical expressions.

q.sub.1 = (CHA) (jg.sub.2) (16)

q.sub.2 = (CHA) (jg.sub.2) (DIP) (17)

q.sub.3 = (CHA) (jg.sub.3) (18)

q.sub.4 = (CHA) (DIP) (jp.sub.3) (19)

The selection outputs N.sub.1 through N.sub.4 produced by the address selection circuit 311 are applied to the priority order setting circuit 312.

With respect to the output lines N.sub.1 through N.sub.4, the priority order setting circuit 312 comprises input gate circuits 351 through 354 and output gate circuits 355 through 358 which are logical product circuits, input gate control circuits (flip-flop circuits) 359 through 362 provided for the input gate circuits 351 through 354, and output gate control circuits (inverter circuits) 363 through 365 provided for the output gate circuits 356 through 357.

The input gate control circuits 359 through 362 are set by a set signal S which is generated whenever one transaction has been transacted, and the set outputs BR.sub.1 through BR.sub.4 of the circuits 359 through 362 operate to maintan the input gate circuit 351 through 354 open, whereby the selection outputs N.sub.1 through N.sub.4 of the address selection circuit 312 are applied through the gate circuits 351 through 354 to the output gate circuits 355 through 358, respectively.

As a result, the following outputs G.sub.1 through G.sub.4 are obtained at the outputs terminals of the input gate circuits 351 through 354.

G.sub.1 = {(h.sub.1) + (h.sub.2) + (h.sub.3) + (h.sub.4) + (h.sub.5)} (BR.sub.1) (20)

g.sub.2 = {(h.sub.6) + (h.sub.7) + (h.sub.8) + (h.sub.9)} (BR.sub.2) (21)

g.sub.3 = {(h.sub.10) + (h.sub.11) + (h.sub.12)}(BR.sub.3) (22)

g.sub.4 = {(h.sub.13) + (h.sub.14) + (h.sub.15)} (BR.sub.4) (23)

the start instruction BRSS of the above-described instruction branch start circuit 21Y, the address routine completion signal ACS of a main operation branch execution completion decision circuit 35, which will be described later, are applied, as first gate condition signals, to the output gate circuits 355 through 358 through an input circuit 366.

The instruction branch start circuit 21Y, as is shown in FIG. 23, receives the outputs IAF, IVF, TMF, LBF, DAF, CVF and DIP of the receipt total, V receipt total, total, LB, payment total, V payment total and payment memories 21R, 21W, 21U, 21V, 21S, 21X and 21T and the output (DIP) (LCVF), to produce the branch start signal DRSS as a logical sum of these outputs. This start signal BRSS is stored in a memory cicuit 367 which is, for instance, a flip-flop circuit, and the output BRS of the memory circuit 367 is transmitted.

In addition, the outputs of the output gate control circuits 363, 364 and 365 are applied, as second gate condition signals, to the output gate circuits 356, 357 and 358 (with the exception of the output gate circuit 355). Although the operation of the control circuit 363 is based on the output G.sub.1 of the N.sub.1 input gate circuit 351, the control circuit 363 operates to open the output gate circuit 356 when the application of the output G.sub.1 is suspended. Similarly, although the operation of the control circuit 364 is based on the outputs G.sub.1 and G.sub.2 of the N.sub.1 input gate circuit 351 and N.sub.2 input gate circuit 352, the control circuit 364 operate to open the output gate circuit 357 when the application of these outputs G.sub.1 and G.sub.2 is suspended. In addition, although the operation of the control circuit 365 is based on the outputs G.sub.1, G.sub.2 and G.sub.3 of the N.sub.1 input gate circuit 351, N.sub.2 input gate circuit 352 and N.sub.3 input gate circuit 353, the control circuit 365 operates to open when the application of these outputs G.sub.1, G.sub.2 and G.sub.3 is suspended.

The priority order setting circuit 312 further comprises an N.sub.5 output gate circuit 370, an N.sub.6 output gate circuit 371, an output gate control circuit 372 which is common to the gate circuits 370 and 371, gate circuits 373 and 374 provided respectively for the gate circuits 370 and 371, and an input gate control circuit 375 which is common to the gate circuit 373 and 374.

The input gate control circuit 375 has the same construction as the control circuits 359 through 362 described above, and is set at the same time as the latter. The set output BR.sub.5 is applied to the N.sub.5 input gate circuit 373, and is applied through an inverter 376 to the N.sub.6 input gate circuit 374.

The N.sub.5 input gate circuit 373 is provided with first and second logical product circuits 377 and 378. The first logical product circuit 377 is adapted to transmit a logical output indicated by the following logical expression (24) to the N.sub.5 output gate circuit 370.

G.sub.5 = {(TMF) + (LBF)} (BR.sub.5) (jg.sub.10) (24)

The second logical product circuit 378 is adapted to transmit a logical output indicated by the following logical expression (25) to the N.sub.5 output gate circuit 370.

G.sub.6 = {(IAF) + (IVF) + (OAF) + (OVF} (BR.sub.5) (jg.sub.10) (25)

The operation of the N.sub.5 output gate circuit 370 is based on the outputs G.sub.1 through G.sub.4 of the gate circuits 351 through 354. The gate circuit 370 is opened by first and second gate condition signals, the former being the output of the control circuit 372 which is transmitted upon application of the outputs G.sub.1 through G.sub.4, the latter being the address routine completion signal ACS.

The N.sub.6 input gate circuit 374 comprises first and second logical product circuits 379 and 380 also. The first logical product circuit 379 operates to transmit a logical output indicated by the following logical expression (26) to the N.sub.6 output gate circuit 371.

G.sub.7 = {(TMF) + (LBF)} (BR.sub.5) (jg.sub.10) (jg.sub.11)(26)

The second logical product circuit 380 operates to transmit a logical output indicated by the following logical expression (27) to the N.sub.6 output gate circuit 371.

G.sub.8 = {(IAF) + (IVF) + (OAF) + (OVF)} (jg.sub.12)(BR.sub.5)(27)

similarly as in the case of the N.sub.5 output gate circuit 370, the operation of the N.sub.6 output gate circuit 371 is based on the outputs G.sub.1 through G.sub.4 of the input gate circuits 351 through 354. This output gate circuit 371 is opened by first and second condition signals, the former being the output of the control circuit 372 which is transmitted upon application of the outputs G.sub.1 through G.sub.4, the latter being the address routine completion signal ACS.

The priority order setting circuit 312 is provided with an N.sub.7 output gate circuit 381 as is shown in FIG. 7. This gate circuit 381 is opened by first, second and third gate condition signals, the first gate condition signal being the line break detection signal LBS which is transmitted when a line break protection circuit 6 described later has detected the interruption of the power line, the second gate condition signal being the set out LBF of the LB memory 21V described above, the third gate condition signal being the address routine completion signal ACS similarly as in the case of the other gate circuits.

As is shown in FIGS. 22 and 23, when the LB memory 21V has been reset by a reset circuit 396 under the condition of a logical sum of the paper feeding signal PF and the set output N.sub.6 of the output holding circuit 33G, and, furthermore, the state of the output holding circuit 33G has been changed from a set state to a reset state by the address routing completion signal ACS, the N.sub.7 output gate circuit 381 operates to transmit and output G.sub.9 indicated by the following logical expression.

G.sub.9 = (ACS) (LBF) (LBS) (28)

thus, the priority order setting circuit 312 transmits outputs F (N-1) through F(N.sub.7) indicated by the following logical expressions (29) through (35) for the output lines N.sub.1 through N.sub.7.

F(N.sub.1) = G.sub.1 {(BRSS) + (ACS)} = {(h.sub.1) + (h.sub.2) + (h.sub.3) + (h.sub.4) + (h.sub.5)} (BR.sub.1) {(BRSS) + (ACS)} (29)

f(n.sub.2) = g.sub.1 g.sub.2 {(brss) + (acs)} = (br.sub.1) g.sub.2 {(brss) + (acs)} = (br.sub.1) (h.sub.6 + h.sub.7 + h.sub.8 + h.sub.9) (BR.sub.2) {(BRSS) + (ACS)} (30)

f(n.sub.3) = g.sub.1 g.sub.2 g.sub.3 {(brss) + (acs)} = (br.sub.1) (br.sub.2) g.sub.3 {(brss) + (acs)} =(br.sub.1) (br.sub.2) (h.sub.10 + h.sub.11 +h.sub.12) (BR.sub.3) {(BRSS) + (ACS)} (31)

f(n.sub.4) = g.sub.1 g.sub.2 g.sub.3 g.sub.4 {(brss) + (acs)} = (br.sub.1) (br.sub.2) (br.sub.3) g.sub.4 {(brss) + (acs)} = (br.sub.1) (br.sub.2) (br.sub.3) (h.sub.13 + h.sub.14 + h.sub.15) (BR.sub.4) {(BRSS) + (ACS)}(32)

f(n.sub.5) = g.sub.1 g.sub.2 g.sub.3 g.sub.4 (g.sub.5 + g.sub.6) {(brss) + (acs)}= (br.sub.1) (br.sub.2) (br.sub.3) (br.sub.4) (g.sub.5 + g.sub.6) {(brss) + (acs)} (33)

f(n.sub.6) = g.sub.1 g.sub.2 g.sub.3 g.sub.4 (g.sub.7 + g.sub.8 + g.sub.9) {(brss) + (acs)} (34)

f(n.sub.7) = g.sub.9 = (acs) (lbf) (lbs) (35)

the output holding circuits 33A through 33G of the address output circuit 33I are, for instance, flip-flop circuits to the set terminals of which the outputs F(N.sub.1) through F(N.sub.7) of the priority order setting circuit 312 are applied. The set terminals of these output holding circuits 33G are connected to the output lines N.sub.1 through N.sub.7, respectively. The circuits 33A through 33F are provided with reset condition circuits 385 through 390, respectively, each of which is a logical circuit with two inputs, that is, the set output of the respective output holding circuit and the address routine completion signal ACS. The reset output of the reset condition circuits 385 through 390 are applied to the output holding circuits 33A through 33F to reset the latter, respectively, and are further applied to the priority order setting circuit 312 thereby to reset the input gate control circuits 359 through 362, respectively.

The main operation branch selection address register 33 shown in FIGS. 22 through 27 operates to sequentially select the output lines N.sub.1 through N.sub.7 with the aid of the condition outputs of the decision processing circuit 32.

Upon application of the receipt total main operation instruction IAF or V receipt total main operation instruction IVF, the priority order setting circuit 312 produces outputs based on the above-described logical expressions through the specified condition circuits and/or input gate circuits as is indicated in Table 1 below, thereby to select an output line which is necessary for the main operation.

                  Table 1
    ______________________________________
    Output        Logical
    line  Circuit expression
                             Output
    ______________________________________
    N.sub.1
          323      (3)      h.sub.3  =  (IAF) + (IVF)
                            (jg.sub.2) (CHA)
    N.sub.2
          327      (7)      h.sub.7   =  (IAF) + (IVF)
                            (jg.sub.3) (CHA)
    N.sub.3
          331     (11)      h.sub.11 =  (IAF) + (IVF (jg.sub.4)
    N.sub.4
          334     (14)      h.sub.14 =  (IAF) + (IVF)  (jg.sub.5)
    N.sub.5
          378     (25)      G.sub.6   = (BR.sub.5) (jg.sub.1)
                             (IAF) + (IVF)
    N.sub.6
          380     (27)      G.sub.7   = (BR.sub.5)(jg.sub.12) (IAF)+(IVF)
    ______________________________________

Similarly as in the case described above, upon arrival of the payment total main operation instruction OAF or V payment total main operation instruction OVF, the circuit 312 operates to select the output lines necessary for the operation as is indicated in Table 2 below.

                  Table 2
    ______________________________________
    Output           Logical
    line   Circuit   expression  Output
    ______________________________________
    N.sub.1
           324        (4)       h.sub.4 = (OAF) + (OVF)
    N.sub.5
           378       (25)       G.sub.6 = (BR.sub.5) (jg.sub.1)
                                 (OAF) + (OVF)
    N.sub.6
           380       (27)       G.sub.8 = (BR.sub.5) (jg.sub.12)
                                 (OAF) + (OVF)
    ______________________________________

Furthermore, upon arrival of the payment main operation instruction (without LCVF) and the exchange dispensation main operation instruction DIP (without CHA), the circuit 312 operates to select the output lines necessary for the operation as is indicated in Table 3 below.

                  Table 3
    ______________________________________
    Output         Logical
    line  Circuit  expression
                              Output
    ______________________________________
    N.sub.1
          322       (2)      h.sub.2   = (DIP) (LCVF) (S.sub.14)
                             (CHA) (jg.sub.2)
    N.sub.2
          326       (6)      h.sub.6   = (DIP) (LCVF) (S.sub.53)
                             (CHA) (jg.sub.3)
    N.sub.3
          330      (10)      h.sub.10 = (DIP) (LCVF) (S.sub.13)
                             (jg.sub.4)
    N.sub.4
          333      (13)      h.sub.13 = (DIP) (LCVF) (S.sub.52)
                             (jg.sub.5)
    ______________________________________

Moreover, upon arrival of the main operation instruction DIP (with LCVF in this case) based on the LCV dispensation, the circuit 312 selects the output line necessary for the operation as is indicated in Table 4 below.

                  Table 4
    ______________________________________
    Output         Logical
    line  Circuit  Expression
                              Output
    ______________________________________
    N.sub.1
          321      (1)       h.sub.1 = (LCVF) (DIP) (CHA)
                             (jg.sub.2)
    ______________________________________

Similarly, upon arrival of the change main operation instruction CHA, the circuit 312 selects the output line which is necessary for the operation, as is indicated in Table 5 below.

                  Table 5
    ______________________________________
    Output         Logical
    line  Circuit  expression
                              Output
    ______________________________________
    N.sub.1
          323      (3)       h.sub.3 = (IAF) + (IVF) (CHA)
                             (DIP) (jg.sub.2)
    ______________________________________

However, when the main operation instruction DIP is introduced in the change dispensation mode, the circuit 312 selects an output line which is necessary for the operation, as is indicated in Table 6 below.

                  Table 6
    ______________________________________
    Output         Logical
    line  Circuit  expression
                              Output
    ______________________________________
    N.sub.2
          328      (8)       h.sub.8 = (CHA) (jg.sub.3) (DIP)
                             (LCVF)
    ______________________________________

Similarly as in the case described above, upon arrival of the total main operation instruction TMF, the circuit 312 selects the output lines which are necessary for the operation, as is indicated in Table 7 below.

                  Table 7
    ______________________________________
    Output         Logical
    line  Circuit  expression
                              Output
    ______________________________________
    N.sub.1
          325       (5)      h.sub.5   = (TMF) (jg.sub.6)
    N.sub.2
          329       (9)      h.sub.9   = (TMF) (jg.sub.7)
    N.sub.3
          332      (12)      H.sub.12 = (TMF) (jg.sub.8)
    N.sub.4
          335      (15)      h.sub.15 = (TMF) (jg.sub.9)
    N.sub.5
          377      (24)      G.sub.5   = (TMF) (BR.sub.5 (jg.sub.10)
    N.sub.6
          379      26        G.sub.7   = (TMF) (BR.sub.5) (jg.sub.11)
    ______________________________________

In the same way, upon arrival of the LB main operation LBF, the priority order setting circuit 312 selects the output lines which are necessary for the operation, as is indicated in Table 8 below.

                  Table 8
    ______________________________________
    Output         Logical
    line  Circuit  expression
                              Output
    ______________________________________
    N.sub.1
          325       (5)      h.sub.5   = (LBF) (jg.sub.6)
    N.sub.2
          329       (9)      h.sub.9   = (LBF) (jg.sub.7)
    N.sub.3
          332      (12)      h.sub.12 = (LBF) (jg.sub.8)
    N.sub.4
          335      (15)      h.sub.15 = (LBF) (jg.sub.9)
    N.sub.5
          377      (24)      G.sub.5   = (LBF) (BR.sub.5) (jg.sub.10)
    N.sub.6
          379      (26)      G.sub.7   = (LBF) (BR.sub.5) (jg.sub.11)
    N.sub.7
          381      (28)      G.sub.9   = (ACS) (LBF) (LBS)
    ______________________________________

The selection outputs N.sub.1 through N.sub.7 thus obtained are sequentially transmitted in the priority order stated.

One example of this sequential transmission will be described with reference to the case where the receipt total main operation instruction is applied under the condition that data has been applied to the buffer memories B.sub.2 through B.sub.5.

Since the application of the condition outputs jg.sub.2 through jg.sub.5 have been effected in this case, the outputs h.sub.3 through h.sub.14 indicated in Table 1 are produced from the input gate circuits 351 through 354, and the output G.sub.6 is produced from the input gate circuit 378, as a result of which the output lines N.sub.1 through N.sub.4 are selected. Furthermore, all of the input gate control circuits 359 - 375 have been set upon completion of the previous transaction. However the N.sub.2, N.sub.3, N.sub.4, N.sub.5 and N.sub.6 output gate circuits 356 - 371 are in the open state with the aid of the respective gate control circuits 363, 364, 365 and 372.

Under these conditions, upon arrival of the branch start instruction BRSS from the instruction branch start circuit 21Y, the N.sub.1 output gate circuit 355 is opened, whereby the output holding circuit 355 is set. As a result, an address output is transmitted to the output line N.sub.1, while no address output is transmitted to the other output lines N.sub.2 through N.sub.7.

The address output thus transmitted to the output line N.sub.1 is applied to an ROM counter 34B of an operation instruction circuit 34 which will be described later, whereby the main program for "cash receipt" is addressed.

Upon execution of this main operation program, the address routine completion signal ACS based on the paper feeding signal PF arrives, as a result of which the output holding circuit 355 is reset through the reset circuit 385, and this reset signal operates to reset the N.sub.1 input gate control circuit. Accordingly, the N.sub.1 input gate circuit 351 is closed, that is the production of the output G.sub.1 is suspended, whereby the N.sub.2 output gate circuit 356 is opened by the gate control circuit 363.

When the N.sub.2 output gate circuit 356 has been opened, an address output is transmitted to the output line N.sub.2 similarly as in the case described above, the main operation program for "receipt of a check on our bank" is addressed with respect to the operation instruction circuit 34.

Thus, whenever the address routine completion signal ACS is obtained, the output holding circuits of the output circuit 33I are reset while the input gate control circuits of the priority order setting circuit 312 are sequentially reset. The address outputs are sequentially delivered to the output lines N.sub.3, N.sub.4 and N.sub.5 by sequentially setting the output holding circuit. As a result, the main operation programs of the receipt of a check on another bank 1, receipt of a check on another bank 2, and the subtotal of receipt in one transaction are sequentially addressed with respect to the operation instruction circuit 34.

When the address routine completion circuit signal ACS is applied to the N.sub.5 output gate circuit 370 in order to set the N.sub.5 output holding circuit 33E in the output circuit 33I, this signal ACS is simultaneously applied also to the N.sub.6 output gate circuit 371. At this time instant, however, since the input gate control circuit 375 has not been reset, the output G.sub.8 indicated in TAble 1 cannot be obtained because the condition BR.sub.5 is not satisfied. Accordingly, the N.sub.6 output holding circuit 33F is not set.

On the other hand, when the N.sub.5 output holding circuit 33E and the gate control circuit 375 are both reset, the condition BR.sub.5 for the output G.sub.8 is satisfied, and therefore the output G.sub.8 is produced. As a result, the N.sub.6 output holding circuit 33F is set so that an address output is transmitted to the output line N.sub.6. This address output operates to address the main operation program of the date/serial number with respect to the operation instruction circuit 34.

The operation of the address register 33 in the case when the receipt total main operation instruction IAF is obtained has been described. In the cases also when the other main operation instructions are obtained, the address register 33 operates to sequentially transmit address outputs to the output lines under the output conditions indicated in Tables 2 through 8, similarly as in the operation described above. However, when the LB main operation instruction LBF is obtained, the address register operates to transmit address outputs to the output lines N.sub.6 and N.sub.7 in the order stated, as is indicated in Table 8.

As is indicated in Tables 3, 4 and 6, when the payment main operation instruction is obtained, a predetermined-position detection signal Ftcs from the money dispensing machine 4 is employed as the address routine completion signal ACS, whereby as the dispensations of 10,000-yen, 5,000-yen, 1,000-yen and 500-yen notes have been successively completed, a step-by-step operation with respect to the N.sub.2, N.sub.3, N.sub.4 and N.sub.5 output holding circuits 33B, 33C, 33D and 33E is carried out.

3-4. Operation instruction circuit 34

An operation instruction circuit 34 operates to subdivide an operation branch (that is, a main branch) which has been specified by the address register 33 in the main operation mode, thereby to produce an execution step control signal and an operation execution instruction which specifies a program (that is, a sub-branch) for the execution of a numerical operation.

In this specification, the term main branch is intended to designate an operation program which should be specified for the operation instruction circuit 34 in a period during which the apparatus is in the main operation mode or the buffer operation mode, and the term sub-branch is intended to designate a program for executing a numerical operation specified in the main branch.

The operation instruction circuit 34, as is shown in FIG. 4, comprises a branch controller 34A, an ROM counter 34B, and ROM 34C, a micro-operation decoder 34D, a branch and step control circuit 34E, an instruction selection decoder 34F, and a buffer operation start circuit 34G.

The branch controller 34A operates to set a main branch in the ROM counter 34B selectively on the basis of program addressing signals which are obtained by the group of memories H.sub.1, H.sub.2, H.sub.3 and H.sub.4 described before (FIGS. 2 and 3). This set operation is achieved by the buffer operation start circuit 34G. More specifically, upon receipt of an addition or subtraction start instruction from the buffer operation instruction control circuit 13 (FIG. 3), the start circuit 34G operates to cause the addressing operation of a main branch with respect to the receipt classification instruction, manual payment classification instruction or payment money classification, which addressing operation is effected from the branch controller 34A to the ROM counter 34B, on the basis of the outputs from the group of memories H.sub.1, H.sub.2 or H.sub.3.

The detailed constructions of the branch controller 34A and the buffer operation start circuit 34G are shown in FIGS. 29 through 32.

The buffer operation start circuit 34G (FIG. 31) comprises a receipt item specification signal forming circuit 111 and a payment item specification signal forming circuit 112. The start circuit 34G further comprises operation start signal forming circuits 113, 114 and 115 which are AND circuits to obtain operation start signals in the receipt item operation mode, payment item operation mode and LCV payment operation mode, respectively.

The signal forming circuits 111 and 112 are set by input signals g.sub.2 and g.sub.3 indicated by the following logical expressions (36) and (37), respectively.

g.sub.2 = {(CAF) + (OBF) + (AB.sub.1 F) + (AB.sub.2 F)} (ODF) (BRS) (36)

g.sub.3 = {(14F) + (53F) + (13F) + (52F) + (LCVF)} (T.sub.1 + EXC) (ICF) (37)

in the above Eqs. (36) and (37), CAF, OBF, AB.sub.1 F, and AB.sub.2 F are the set outputs of the cash receipt, our bank, another bank 1 and another bank 2 memories 21B, 21C, 21D and 21E, respectively; 14F, 53F, 13F and 52F are the set outputs of the 10,000-yen note, 5,000-yen note, 1,000-yen note and 500-yen note memories 21I, 21J, 21K and 21L, respectively; and LCVF is the output of an LCV flag circuit 37D which will be described later. Furthermore, ICF and ODF are the set outputs of the signal forming circuits 111 and 112, respectively; BRS is the operation start signal of the instruction branch start circuit 21Y (FIG. 23); T.sub.1 is the control signal which is delivered from the T control circuit 21P (FIG. 3) when the T key 11J is operated; and EXC is the control signal which is produced by the T control circuit 21P in the exchange business.

When the apparatus is not in the main operation mode (or when BRS is obtained), the signal forming circuit 111 produces a receipt item output ICF under the condition that one of the receipt classification items is specified (that is, CAF, OBF, AB.sub.1 F or AB F is obtained).

On the other hand, when the T key 11J has not been operated or the exchange mode has been specified, the signal forming circuit 112 produces a payment item output ODF under the condition that one of the payment items and LCV mode is specified (that is, 14F, 53F, 13F, 52F or LCVF is obtained).

These outputs ICF and ODF are applied to the branch controller 34A, and are applied to a 1/15 address signal forming circuit 116 through an OR circuit 117. The signal forming circuit 116 is a two-input AND circuit which receives the signal BRS as its one input.

Thus, in the case when the apparatus is not in the main operation mode, the branch controller 34A produces an X.sub.5 address signal BRS (ICF + ODF) when the receipt item output ICF and payment item output ODF are applied thereto.

On the other hand, the operation start signal forming circuit 113 for the receipt item operation mode produces, as a buffer start signal, an output signal f.sub.1 indicated by the following logical expression (38).

f.sub.1 = (ADD) { (ICF) + (ODF)} (WE) (ICF) (38)

the operation start signal forming circuit 114 for the payment item operation mode produces, as a buffer start signal, an output signal f.sub.2 indicated by the following logical expression (39).

f.sub.2 =[(ADD) {(ICF) + (ODF)} (ODF) (LCV) (39)

furthermore, the operation start signal forming circuit 115 for the LCV payment operation mode produces, as a buffer start signal, an output signal f.sub.3 indicated by the following logical expression (40).

f.sub.3 = (WE) (LCVF) (40)

in the logical expressions (38), (39) and (40), ADD is the output which is produced by the key input circuit 13C (FIG. 3) when the + key 13A is operated, and WE is the input inhibit signal which when a numerical data has been applied, is produced so that data is no longer applied.

When the output signals, or buffer start signals, f.sub.1, f.sub.2 and f.sub.3 are produced by the operation start signal forming circuits 113, 114 and 115, respectively, these signals are applied to the branch controller 34A.

The branch controller 34A is provided with a Yo address signal forming circuit 120 which is a flip-flop circuit. This circuit 120 is set by the buffer start signal, thereby to produce its set output ROMF as a Y.sub.o address signal. The circuit 120 is reset by a branch completion signal ACS produced by the branch and step control circuit 34E which will be described later.

The branch controller 34A further comprises a Y.sub.2 address signal forming circuit 121 which is a two-input NAND circuit for instance. To one of the inputs of this circuit 121, the output CAF of the "cash receipt" memory 21B in the group of receipt classification item memories H.sub.1 and the output 14F of the 10,000-yen note memory 21 in the group of payment money classification item memories H.sub.3 are applied through an OR circuit 121A.

The branch controller 34A further comprises Y.sub.3, Y.sub.4 and Y.sub.5 address signal forming circuits 122, 123, and 124 which are similar to the Y.sub.2 address signal forming circuit 121. These circuits 122, 123 and 124 receive through OR circuits 122A, 123A and 124A the output OBF of the our bank memory 21C and the output 53F of the 5,000-yen note memory 21J, the output AB.sub.1 F of the another bank 1 memory 21D and the output 13F of the 1,000-yen note memory 21K, and the output AB.sub.2 F of the another bank 2 memory 21E and the output 52F of the 500-yen note memory 21L, respectively.

OR circuits 125 and 126 are provided in the input paths of the Y.sub.2 and Y.sub.3 address signal forming circuits 121 and 122, respectively. Through these OR circuits 125 and 126, the LCV signal LCVF (indicating that the LCV payment operation mode has been specified) and the monetary change signal CHA (indicating that the change operation mode has been specified) are applied, respectively.

On the other hand, a condition signal T.sub.3.BRS (indicating that neither of the main operation mode and zero proof operation mode has been specified, that is, the buffer operation mode has been specified) which is obtained on the basis of both the "T" control signal T.sub.3 (indicating that the zero proof operation mode has been specified) from the "T" control circuit 21P and the main operation branch start signal BRS (indicating that the main operation mode has been specified) from the instruction branch start circuit 21Y, is applied, as a zero condition input, to the Y.sub.2, Y.sub.3, Y.sub.4 and Y.sub.5 address signal forming circuits 121 through 124.

Thus, when the receipt classification item memories 21B - 21E or the payment classification item memories 21I - 21L are set in the buffer operation mode, or when the LCV payment operation mode is specified, the branch controller 34A operates to produce the Y.sub.2, Y.sub.3, Y.sub.4 and Y.sub.5 address signals from the respective circuits 121 through 124.

The above-described condition signal T.sub.3 . BRS is directly produced as a Y.sub.1 address signal.

The Y.sub.o through Y.sub.5 address signals thus produced are applied to Y.sub.o, Y.sub.1, Y.sub.2, Y.sub.3, Y.sub.4 and Y.sub.5 address input circuits 140 through 145 of the ROM counter 34B, respectively.

The ROM counter 34B operates to read out of a Read-only memory (ROM) 34C an operation program (that is, a main branch) which is addressed by an address operation which is carried out by the branch controller 34A in the buffer operation mode or by an address operation which is carried out by the address register 33 in the main operation mode.

The ROM counter 34B selects a main branch for execution of the main operation mode or buffer operation mode specified, on the basis of the address conditions indicated in FIG. 13. More specifically, the ROM counter 34B is provided with Y address input lines Y.sub.o through Y.sub.5 and X address input lines X.sub.o through X.sub.5. The Y address input lines are addressed from the address register 33 in the main operation mode (the Y address input lines being selected by the input circuits 140 through 150 described above), while the X address input lines are addressed, in the same way as in the case of the Y address input line, according to the operation mode specified.

The main branches stored in the ROM 34C are assigned to the addresses which are provided at the intersection points of the X and Y address input lines. Accordingly, in the case when the addresses are successively selected, the main branches fixedly stored in the ROM 34C are also successively read out in the order of the address selection, that is, a main branch corresponding to an address selected is read out of the main branches stored in the ROM 34C.

In FIG. 13, the X address input lines X.sub.1 through X.sub.4 are addressed when the apparatus is in the main operation mode, while the X address input line X.sub.5 is addressed when the apparatus is in the buffer operation mode.

That is, the input line X.sub.1 is addressed by both the address signal IAF (which is the output of the receipt total memory 21R) which is applied in the case of the receipt total mode and the address signal IVF (which is the output of the V receipt total memory 21W) which is applied in the case of the V receipt total mode, while the input lines Y.sub.o, Y.sub.1, Y.sub.2, Y.sub.3, Y.sub.4 and Y.sub.5 are successively addressed. Therefore, the main branches corresponding to the addresses at the intersection points of the input lines Y.sub.o through Y.sub.5 and the input line X.sub.1, that is, the cash, our bank, another bank 1, another bank 2, collation (read-out) and date operation programs are successively read out of the ROM 34C.

The input line X.sub.2 is addressed by the address signal OAF (which is the output of the payment total memory 215) and the address signal OVF (which is the output of the V payment total memory 21X) which are applied in the cases of the payment total and V payment total modes, respectively, while the input lines Y.sub.o, Y.sub.4 and Y.sub.5 are successively addressed. Therefore, the main branches corresponding to the addresses at the intersection points of these input lines Y.sub.o, Y.sub.4, Y.sub.5 and X.sub.2, that is, the cash payment (payment total), collation (read-out) and date operation programs are successively read out of the ROM 34C.

The input line X.sub.3 is addressed by the address signal TMF (which is the output of the memory 21U) and the address signal LBF (which is the output of the memory 21V) which are applied in the total and LB modes, respectively, while the input lines Y.sub.o, Y.sub.1, Y.sub.2, Y.sub.3, Y.sub.4 and Y.sub.5 are successively addressed. Therefore, the main branches corresponding to the addresses at the intersection points of these input lines X.sub.3 and Y.sub.o through Y.sub.5, that is, the cash, our bank, another bank 1, another bank 2, automatic dispensation and cash payment (date) operation programs are successively read out of the ROM 34C. In the case where the address (X.sub.3, Y.sub.5) is addressed, if the operation mode is the total operation mode, only the cash payment operation program will be read out, and if it is the LB operation mode, the cash payment and date operation programs will be successively read out.

The input line X.sub.4 is addressed by the address signal DIP (which is the output of the memory 21T) which is applied in the payment mode, while the input lines Y.sub.o, Y.sub.1, Y.sub.2 and Y.sub.3 are successively addressed. As a result, the main branches corresponding to the addresses at the intersection points of these input lines X.sub.4, and Y.sub.o through Y.sub.3, that is, the 10,000, 5,000, 1,000 and 500 operation programs are successively read out of the ROM 34C.

In the buffer operation mode, the input line X.sub.5 is addressed by the address signal (ICF + ODF) BRS (which is the output of the branch controller 34A in FIG. 31) which is applied upon receipt of the receipt item data and payment item data (including the data of the LCV mode), while the input lines Y.sub.o, Y.sub.1, Y.sub.2, Y.sub.3, Y.sub.4 and Y.sub.5 are successively addressed. As a result, the main branches that are the buffer operation start, numerical data write-in, cash, our bank, another bank 1 and another bank 2 operation programs are read out of the ROM 34C in a first case when the receipt item data is applied, while the main branches which are the buffer operation start, numerical data write-in 10,000, 5,000, 1,000 and 500 operation programs are read out of the ROM 34C in a second case when the payment item data is applied.

Especially in the LCV mode in the buffer operation, the input lines Y.sub.o , Y.sub.1 and Y.sub.2 are addressed, as a result of which the buffer operation start, numerical data write-in and LCV operation programs are read, as main branches, out of the ROM 34C.

The operation programs corresponding to the addresses are fixedly stored, as main branches, in the ROM 34C, as was described above. Each of the operation programs includes a step signal which is adapted to control peripheral equipment which is driven for the execution of the operation program, and a sub-branch selection instruction adapted to selectively specify an operation program (that is, a sub-branch) provided for the numerical operation of data which is stored in the main memory section MM or the buffer memory section BM according to the operation mode specified. These execution signals and instructions are transmitted out of the ROM 34C in a predetermined order when the main branches are addressed by the address register 33 as was described above.

The execution signal of the main branch read out of the ROM 34C is decoded by the micro-operation decoder 34D and is applied to the branch and step control circuit 34E. This circuit 34E operates to distribute the step signal to the periphery equipment which is provided for the execution of an operation program of a main branch, and to apply a sub-branch selection instruction to the instruction selection decoder 34E.

This instruction selection decoder 34F operates to convert a start condition as to a numerical operation which is to be executed according to a given sub-branch selection instruction, into a predetermined format which is set in an address register 36A which will be described later.

The collation and date/serial number instruction signals are applied, as an operation execution instruction, from a management instruction control circuit 14 to the instruction selection decoder 34F. When the instruction set in the ROM counter 34B is especially the buffer operation instruction, a branch completion signal is applied from the control circuit 34E to the branch controller 34A whenever a buffer operation for each of the classification items is completed, as a result of which the branch selection operation of the circuit 34A is carried out step by step.

(3-5) Main operation branch execution completion decision circuit 35

This decision circuit 35, especially in the case where the instruction set in the ROM counter 34B is the buffer operation instruction as was described above, operates to cause the step-by-step selection operation of the address register 33 and the reset operations of the main operation instruction memory groups H.sub.5 and H.sub.6 described before.

The decision circuit 35 comprises an address routine completion decision circuit 35A and a branch completion decision circuit 35B.

The circuit 35A operates to apply to the output holding circuits 33A through 33G (FIG. 9) a logical sum signal ACS (= PF + Ftcs) of the paper feeding signal PF produced by the printer 52 and a predetermined-position detection signal Ftcs transmitted by the money dispensing machine 4. The paper feeding signal PF is produced by the printer 52 when a step signal to the periphery equipment is produced by the branch and step control circuit 34E in the operation instruction circuit 34 so that the printer 52 completes its printing operation of, for instance, one line. The predetermined-position detection signal Ftcs is sent from the money dispensing machine 4 when the money dispensation mechanism reaches the money dispensation position, or predetermined-position, of each of the money containers provided separately according to the monetary denominations. The logical sum signal ACS (= PF + Ftcs) is employed as an address routine completion signal indicating the completion of an address operation with respect to one main branch specified.

Thus, the output holding circuit of one output line which has been in a set state is reset, and the main branch relating to the next output line is addressed. In the end, the address routine completion decision circuit 35 thus forms an instruction selection cycle of a key operation with the address register 34A, ROM counter 34B, ROM 34C, micro-operation 34D and branch and step control circuit 34E. Through the instruction selection cycle thus formed, the address operations of the output lines N.sub.1 through N.sub.6 of the address register 33 are carried out step-by-step.

The branch completion decision circuit 35B, upon completion of all of the operations of a main operation, operates to reset the main operation instruction memory groups H.sub.5 and H.sub.6 with the aid of the branch completion signal transmitted from the branch and step control circuit 34E in the operation instruction circuit 34, so that the memory groups H.sub.5 and H.sub.6 will be ready for receiving the succeeding instruction input.

(3-6) Operation processing control circuit 36

This circuit 36 operates the write registration data applied in one transaction into the buffer memory section BU. Furthermore, according to the classification data and operation instructions, the circuit 36 operates to read out the numerical data stored in the buffer memory section BU and the main memory section MM, to subject the data thus read out to addition or subtraction, and to write the resultant data of the addition or subtraction into the memory sections BU and MM. In addition, the circuit 36 operates to transmit the data stored in the buffer memory section BU and the main memory section MM to the data output system 5 and/or the money dispensing machine 4.

The operation processing control circuit 36, as is shown in FIG. 4, comprises an address register 36A for operation execution, a ROM 36B, a micro-operation decoder 36C and an operation and decision circuit 36D.

The address register 36A is set by receiving registration data and a decimal point signal from the data read-in decoder 22 of the program addressing system 2 and also an operation start condition signal from the instruction selection decoder 34F of the operation instruction circuit 34 and simultaneously reads a corresponding sub-branch out of the ROM 36B which is employed as an instruction word described before. This instruction word, the registration data, and a decimal point sign are combined into one data signal which is applied to the micro-operation decoder 36C.

The combined data signal is decoded by the decoder 36C and is transmitted to the operation and decision circuit 36D.

The operation and decision circuit 36D, as is shown in FIG. 9, is provided with an operation circuit which comprises a register NKR which receives a data signal from the micro-operation decoder 36A and dynamically stores data signal through a full adder FA, and a register ACR which reads out of the memory device 31 and dynamically stores the data. The registration data of the register ACR is added to that of the register NKR by the full adder FA, and the resultant data is stored in the register ACR and thereafter written in the memory device 31.

The data stored in the buffer memories B.sub.2 through B.sub.5 provided separately according to the classification items in the memory device 31 are read out to be added to the registration data by the operation circuit 36D, the resultant data being written in the collation buffer memory B.sub.1, or the data stored in the collation buffer memory B.sub.1 and also in the main memories M.sub.1 through M.sub.6 are read out to be added to one another, the resultant data being written into the memories M.sub.1 through M.sub.6, or the data stored in the buffer memory B.sub.1 or the main memories M.sub.1 through M.sub.6 are introduced into the operation circuit 36D, the data thus introduced being applied to the data output system 5.

In the case when the data are read out of or written into the memory device 31, the transmission of the data is carried out by a memory field specifying circuit 36E on the basis of an operation start condition output of the instruction selection decoder 34F.

In addition to the operation function described above, the operation decision circuit 36D has a function described below. That is, if after the completion of an operation of one step, the execution of the next operation is necessary, the set condition of the address register 36A is advanced by one state (or the state of the address register 36A is set to be another state) by the output condition of a decision circuit incorporated in the operation decision circuit 36D, whereby the operation of the succeeding step is executed.

The step-by-step function described above is effected in the execution of the date/serial number branch (when a date set instruction signal is applied by the date switch 14C). In this operation, first an operation for adding 1 to the least significant digit of a registration data in the data/serial number main memory M.sub.7 is carried out, and upon completion of this operation the next operation step is set in the address register 36A by the output signal of the decision circuit.

An operation processing cycle for the operations between the buffer memories or between the buffer memories and the main memories, and also for the read-out and write-in of the buffer memories and the main memories is formed by a loop circuit made up of the address register 36A, ROM 36B, micro-operation decoder 36C, and operation decision circuit 36D.

3-7. transfer output circuit 37

This transfer output circuit 37 operates to transfer registration money amount data and a dispensation mode signal to the money dispensing machine 4 when money is paid by the automatic money dispensation, and comprises a transfer status control circuit 37A.

This circuit 37A operates to apply a transfer control signal of one word time (hereinafter referred to as a transfer flag signal or a TRF signal when applicable) to a transfer control circuit 37B so that when data introduced into the operation circuit of the operation decision circuit 36D is transferred through the transfer control circuit 37B to the money dispensing machine 4, the data is statically stored, as a money amount represented by a binary coded decimal number, in a memory distributor 37C. After the data has been transferred to the memory distributor 37C, the transfer status control circuit 37A produces a load signal load for transferring the contents of the memory distributor 37, as a parallel data, to the money dispensing machine 4.

Furthermore, the transfer status control circuit 37A operates to produce transfer clock pulses within a time period for transferring one word so that when the circuit 37A transfers registration data to the money dispensing machine 4 through the transfer control circuit 37B, an error check and a memory check are carried out in the money dispensing machine 4.

Thus, the transfer output circuit 37 operates to transfer a static parallel money amount data of a binary coded decimal number through the memory distributor 37C from the operation decision circuit 36D and also a dynamic series money amount data directly from the transfer control circuit 37B to the money dispensing machine 4.

The transfer output circuit 37 further comprises an LCV flag forming circuit 37D which, when the application of registration data is effected by the ten-key device before the application of classification item data is carried out by the classification item switch other than the switches of the ten-key device, produces an LCV signal LCVF as a second automatic money dispensation mode signal on the basis of the registration data which is applied from the ROM 36B to the operation and decision circuit 36D.

The LCV flag forming circuit 37D, as is shown in FIG. 30, comprises a flip-flop circuit 130 and its input condition circuit 131, which is an AND circuit. The input condition circuit 131 operates to set the flip-flop circuit 130 with the timing of a predetermined timing signal DTO when data DATA from the ROM 36B is applied to the input condition circuit 131, under the condition that a condition signal AL is available which is introduced to the same circuit 131 only when data is registered by the ten-key device 12A with the group of payment money classifying key-switches G.sub.3 being not operated.

Thus, the LCV flag forming circuit 37D produces the LCV signal LCVF when the keys of the ten-key device 12A are operated before the operation of the other keys.

Depending on the program address signal and the registered data from the data input system 8, which comprises the instruction input system 1 and the program addressing system 2, the memory operational processing system 3 of the above-mentioned composition first carries out buffer operation programs as defined hereinbefore for classifying and memorizing the same, and then carries out main operation programs.

1. In the case of receiving:

The buffer operation programs are carried out as follows.

a. Either one of the switches 21B through 21E (for cash through other bank 2) of the deposition classification switch group G.sub.1 is depressed.

i. A main branch for the buffer operation corresponding to the depressed key switch is selected by the operation instruction circuit 34, and a sub-branch corresponding to the main branch is set in the instruction selecting decoder 34F.

b. The amount of money to be deposited is registered by means of ten-key device 12A.

i. The data thus registered are combined in the operation processing control circuit 36 with the instruction words, and the data thus combined are read into the register NKR (FIG. 9) in the operation discriminating circuit 36D.

c. The + key switch 13A is depressed.

i. The buffer operation is started by the buffer operation starting circuit 34G, and the registered data are added into the buffer memories B.sub.2 through B.sub.5 in the memory device 31.

ii. The registered data are also read into the collation buffer memory B.sub.1.

iii. The registered data printed out of the operation discrimination circuit 36D are sent to the data output device 5.

d. The collation key switch 14A is depressed.

i. All the registered data in the "collation" buffer memory B.sub.1 are added together, and the added result is sent to the data output device 5 as an output to be displayed.

Then, for carrying out the main operational programs.

e. A certification printing slip is inserted in the certification-printing chute, and the deposit total key switch 11M is depressed.

i. The main operation is thereby started without delay, and the data in the buffer memories B.sub.2 through B.sub.5 for 10,000-yen note through 500-yen note are added to the cash payment main memory M.sub.6, thereby to rewrite the added result in the main memory M.sub.6.

ii. All the data in the collation buffer memory B.sub.1 are added together, and the added result is transferred to the data output device 5 as an output to be printed.

iii. 1 is added to the lowest position of the content stored in the date, serial number main memory M.sub.7, and the thus added result, which is printed out, is also applied to the data output device 5.

f. The certification printing slip is pulled out.

i. The data in the collation buffer memory B.sub.1 are sequentially printed out and sent to the data output device 5.

ii. All the data in the "collation" buffer memory B.sub.1 are added together, and the added result read out of the buffer memory B.sub.1 is sent to the data output device 5 to be displayed thereafter.

iii. Data from the "date, serial number" main memory M.sub.7 are printed out to be delivered toward the data output device 5.

2. In the case of payment with the monetary denominations designated (payment through the first automatic money dispensation):

Buffer operational programs are carried out as follows.

a. Desired key switches among the switches 21I through 21L in the money denomination designating switch group G.sub.3 are depressed.

i. The buffer operation programs corresponding to the depressed key switches are selected in the operation instruction circuit 34, and set in the instruction selecting decoder 34F.

b. The amount of the money to be paid is registered by depressing ten-key device 12A.

i. The data thus registered is combined in the operation processing control circuit 36 with the instruction words, and the thus combined data are read into the register NKR.

c. The + key switch 13A is depressed.

i. The buffer operation is started by means of the buffer operation starting circuit 34G, and the resulting data are added to the data in the buffer memories B.sub.2 through B.sub.5.

ii. The data are read into the collation buffer memory B.sub.1.

iii. The output data printed out of the operation discriminating circuit 36D are registered into the data output device 5.

d. The collation key switch 14A is depressed.

i. All of the registered data in the collation buffer memory B.sub.1 are added together, and the result is sent to the data output device 5 as an output to be displayed.

Then for carrying out the main operational programs in the main memory,

e. A certification printing slip is inserted in the certification printing chute, and the deposit total key switch 11M is depressed.

i. The main operation is at once started thereby adding the data in the buffer memories B.sub.2 through B.sub.5 (for 1,000-yen note through 500-yen note) to the data in the cash payment main memory M.sub.6, and rewriting the added result into the main memory M.sub.6.

ii. All of the data in the collation buffer memory B.sub.1 are added together, and the added result is sent to the data output device 5 as an output to be printed out.

iii. 1 is added to the lowest position of the content in the date, serial number main memory M.sub.7, and the thus added result is sent to the data output device 5.

f. The payment key switch 110 is depressed.

i. A start-payment signal ST is delivered from the branch-and-step control circuit 34E of the operation instruction circuit 34 to the money dispensing machine 4.

ii. A data transferring signal TRF is delivered from the transfer-status control circuit 37A to the transfer control circuit 37B.

iii. The data concerning the highest note stored in the collation buffer memory B.sub.1 are transferred through the transfer control circuit 37.sub.B to the money dispensing machine 4.

iv. Upon transfer of the data concerning the highest denomination, data concerning lower denominations, if any, are transferred successively to the money dispensing machine 4 by repeating the above described steps (ii) and (iii).

v. When the money dispensing machine has paid all of the cash as designated by the data thus transferred, the payment completion signal EOC is delivered from the machine. The signal EOC resets the payment instruction memory 21T, and all the data concerning the monetary denomination stored in the collation buffer memory B.sub.1 are added together, with the results being further added to the data in the automatic dispensing main memory M.sub.5 to be rewritten in the same memory M.sub.5.

3. in the case of payment at a minimum sheet number (LCV or second automatic money dispensation):

a. Required data are registered by the ten-key device 12A.

i. Under the conditions of neither of the paid money designating switch group G.sub.3 being depressed, and only the data through the ten-key device 12A being registered, a signal LCVF forming an LCV flag is generated in the LCV flag forming circuit 37D.

ii. The data thus registered are read into the register NKR of the operation discriminating circuit 36D.

b. The + key switch 13A is depressed.

i. The data thus registered are read into the collation buffer memory B.sub.1.

ii. The registered data printed out from the operation discriminating circuit 36D are sent to the data output device 5.

c. The collation key switch 14A is depressed.

i. All of the data registered in the collation buffer memory B.sub.1 are added together, and the added result is sent into the data output device 5 as a displaying output. Next, for executing the main operation,

d. The certification printing slip is inserted into the certification printing chute, and the payment total key switch 11M is depressed.

i. the data in the collation buffer memory B.sub.1 are added to the data in the cash payment main memory M.sub.6, and the thus added result is rewritten in the main memory M.sub.6,

ii. All of the data in the collation buffer memory B.sub.1 are added together, and the result is sent to the data output device 5 as an output to be printed out.

iii. 1 is added to the lowest position in the date, serial number main memory M.sub.7, and the added result is sent to the data output device 5 as an output to be printed out.

e. The certification printing slip is pulled out.

i. All of the data in the collation buffer memory B.sub.1 are added together, and the result is sent to the data output device 5 as an output to be printed out.

ii. The data in the date, serial number main memory M.sub.7 are delivered as an output to be printed out to the data output device 5.

f. The withdrawal key switch 110 is depressed.

i. A dispensation start signal ST is delivered from the branchand-step control circuit 34E in the operation instruction circuit 34 to the money dispensing machine 4.

ii. A data transfer signal TRF is delivered from the transfer status control circuit 37A to the transfer control circuit 37B.

iii. The data in the collation buffer memory B.sub.1 are transferred through the transfer control circuit 37B to the money dispensing machine 4.

iv. Upon completion of the money dispensation from the money dispensing machine 4 in accordance with the transferred data, the payment instruction memory 21T is reset by the dispensation completion signal EOC, and the data in the collation buffer memory B.sub.1 are added together so that the added result is in turn written into the automatic dispensation main memory M.sub.5.

4. in the case of exchanging money:

The buffer operations are first carried out as follows.

a. The non-addition mode selecting key switch, that is, the T key switch 11J is depressed.

i. The zero-proof program is selected in the operation instruction circuit 34, and the program is set in the instruction selecting decoder 34F.

b. Money classification key switches corresponding to the kinds of money to be exchanged (switches 11F through 11I for 10000 yen note through 500 yen note) are depressed, and then the amount thereof is registered by means of the ten-key device 12A.

i. The data thus registered are combined with the instruction words in the operation process control circuit 36, and read into the register NKR in the operation discriminating circuit 36D.

c. The - key switch 13B is depressed.

i. The buffer operation is started by the buffer operation starting circuit 34G, and the data to be registered are read into the collation buffer memory B.sub.1 with the sign inverted to negative.

ii. The data printed out of the operation discriminating circuit 36D are sent to the data output device 5.

d. After depression of the money exchange key switch 11K, the money classification key switches 11G through 11I (corresponding to 500 yen note) are depressed.

i. The programs corresponding to the depressed key switches are selected in the operation instruction circuit 34.

e. The amounts in all of the kinds of money to be exchanged are registered by means of the ten-key device 12A.

i. The registered data are combined with the instruction words in the operation processing control circuit 36, and read into the register KKR.

f. The + key switch BA is depressed.

i. The registered data concerning the amounts for every denominations of money to be exchanged are added to the corresponding ones in the buffer memories B.sub.1 through B.sub.5 (for 10,000-yen note through 500-yen note).

ii. All of the data are read into the collation buffer memory B.sub.1.

iii. The output printed out of the operation discriminating circuit 36D is sent into the data output circuit 5.

g. The T key switch 11J is depressed.

i. All of the data in the collation buffer memory B.sub.1 are added together, and the thus added result is delivered from the operation discriminating circuit 36D as a displaying output to be sent to the output device. When the displaying output is 0, this means that the money exchange has been executed without error.

ii. All the data in the collation buffer memory B.sub.1 are added together, and the added result is printed out of the operation discrimination circuit 36D to be applied thereafter to the data output device 5. Then the main operation programs are executed as follows.

h. The payment key switch 110 is depressed.

i. A dispensation start signal ST is sent from the branch and step control circuit 34E of the operation instruction circuit 34, to the money dispensing machine 4.

ii. A data transfer signal TRE is delivered from the transfer status control circuit 37A, and sent to the transfer control circuit 37B.

iii. A part of the data corresponding to the highest monetary denomination is transferred from the collation buffer memory B.sub.1 to the money dispensing machine through the transfer control circuit 37B.

iv. After completion of the transfer of the data concerning the highest denomination, the data concerning lower denominations, which might exist in the collation buffer memory B.sub.1, are transferred to the money dispensing machine by repeating the above described steps (ii) and (iii).

v. When the money dispensing machine 4 has dispensed the money corresponding to the data thus transferred, entirely, the dispensation completion signal EOC issues thereupon causing the dispensation instruction memory 21T to be reset. All of the data concerning the monetary denominations contained in the collation buffer memory B.sub.1 are added together, and the result is further added to the data in the automatic dispensing main memory M.sub.5. The ultimate result is then rewritten into the same memory M.sub.5.

5. in the case of change transactions:

The buffer operational programs are executed as follows:

a. The non-additional mode selecting key switch, that is, T key switch 11J is depressed.

i. The zero proof program is selected in the operation instruction circuit 34, and the program is set in the instruction selecting decoder 34F.

b. The key switches corresponding to the money brought by a customer, which are selected from the group of the money classification key switches 11F through 11I for 10,000-yen note through 500-yen note, are first depressed, and the amount of the money is thereafter registered by means of the ten-key device 12A.

i. The data thus registered are combined in the operation processing control circuit 36 with the instruction words, and the thus combined data are read into the register NKR.

c. The - key switch 13B is depressed.

i. The buffer operations are started by means of the buffer operation start circuit 34G, and the registered data are read into the collation buffer memory B.sub.1 with the sign thereof being inverted to negative.

ii. The registered data thus read into the collation buffer memory B.sub.1 are passed through the operation discriminating circuit 36D, and the output thereof is printed out and delivered to the data output device 5.

d. The cash switch 11A in the key switch group G.sub.1 is depressed.

i. A buffer operation program corrsponding to the cash deposit is selected in the operation instruction circuit 34, and the thus selected result is set in the instruction selecting decoder 34F.

e. The received amount of money is registered by the ten-key device 12A.

i. The registered data are combined in the operation processing control circuit 36 with the instruction words, and the result is read into the register NKR.

f. The + key switch 13A is depressed.

i. The buffer operation is started by means of the buffer operation start circuit 34G, and the registered data are added to the contents of the cash payment buffer memory M.sub.6.

ii. The registered data are read into the collation buffer memory B.sub.1.

iii. The registered data are passed through the operation discriminating circuit 36D, and the output thereof out is sent to the data output device 5.

g. The change key switch 11L is depressed, and then the amount of the change is registered by the ten-key device 12A.

i. The registered data concerning change are combined in the operation processing control circuit 34 with the instruction words, and the result is read into the register NKR.

h. The + key switch 13A is depressed.

i. The registered data are read into the collation buffer memory B.sub.1.

ii. The registered data are then passed into the operation discriminating circuit 36D, and the printed-output thereof is delivered to the data output device 5.

i. The T key switch 11J is depressed.

i. All of the data in the collation buffer memory B.sub.1 are added together, and the added result is delivered as a displaying output to the data output device 5 by way of the operation discriminating circuit 36D. Herein, it is judged that the change payment was correct when the displayed output from the data output device is zero.

ii. All of the data in the collation buffer memory B.sub.1 are added together, and the result is delivered as its output to be printed to the data output device 5 by way of the operation discriminating circuit 36D.

The main operational programs are executed as follows.

j. The certification printing slip is inserted into the certification printing chute, and the deposit total key switch 11M is depressed.

i. The main operations are at once started, with the data in the cash deposit buffer memory B.sub.2 being added to the data in the cash deposit main memory M.sub.1, and the added result is rewritten in the main memory.

ii. All of the data in the collation buffer memory B.sub.1 are sequentially sent to the data output device to be printed out therefrom.

iii. 1 is added to the lowest position in the content of the date, serial number main memory M.sub.7, and the result is sent to the data output device 5 as an output to be printed out.

k. The certification printing slip is pulled out.

i. The data concerning cash deposit contained in the collation buffer memory B.sub.1 are sent to the data output device 5 to be printed out therein.

ii. The data in the date, serial number main memory M.sub.7 are sent to the data output device to be printed out therein.

1. The payment key switch 110 is depressed.

i. A dispensation start signal ST is delivered from the branch and step control circuit 34E of the operation instruction circuit 34 to the money dispensing machine 4.

ii. A data transfer signal TRF is delivered from the Transfer status control circuit 37A to the transfer control circuit 37B.

iii. The registered change data in the collation buffer memory B.sub.1 are transferred via the transfer control circuit 37B to the money dispensing machine 4.

iv. When the money dispensing machine completes the money dispensation in accordance with the data thus transferred, a money dispensation completion signal EOC is issued thereby resetting the payment instruction memory 21T, and the registered change data in the collation buffer memory B.sub.1 are then added and rewritten in the automatic dispensation main memory M.sub.5.

4. money dispensing machine

The money dispensing machine 4 is designed to dispense notes and coins in the hereinbefore mentioned first money dispensation mode or in the second money dispensation mode automatically, in accordance with the data and control signals transferred from the memory operation processing system 3. The money dispensing machine comprises the following sections (refer to FIGS. 6 and 7).

4-1. Dispensed money amount collation section:

The dispensed money amount collation section 41 receives the monetary data and the LCV signal concerning the dispensing mode, both delivered from the transfer output circuit 37 in the memory operation processing system 3, and collates the amount and denomination of the money automatically dispensed as described above against the transferred data. The section 41 comprises following elements:

A dispensation counter 41A of, for instance, six digit decimal composition, and including, for instance, six reversible counters, for receiving data about the amount of money to be dispensed, through a load control circuit 41B;

A note passage detector 41C and a coin passage detector 41D, each of which generates a detecting pulse whenever a piece of note or coin is dispensed through each passage leading to a dispensing outlet;

A counter-input selection circuit 41E which distributes the series of pulses generated in a count pulse generating circuit 41F to a counter for a corresponding digit upon reception of the detecting pulses from the detectors 41C and 41D, each series being weighted by a condition signal delivered from a hereinlater described money dispensation control section 43 and representing the denominations of the money now dispensed. To be more specific, when a 500 yen note is dispensed, five pulses are introduced through a counting input terminal of the dispensation counter 41A into the 100 position counter; and

A zero coincidence detecting circuit 41G which receives a borrowing output from each digit counter in the dispensation counter 41A, and, according to the condition of whether the content of each counter is zero or not, detects in each monetary denomination the coincidence between the sum of money thus dispensed and the sum designated by the data.

However, it should be noted that a borrowing gate circuit is provided between each of the digit counters in the dispensation counter 41A. The gate circuit is closed upon reception of the LCV signal from the transfer status control circuit 37A. Thus, when the hereinbefore described first automatic money dispensation mode is designated, the borrowing gate circuits for the digit counters corresponding to the designated denominations and therefore for the counters of higher positions than said positional counters are kept open, and since the zero-coincidence circuit 41G does not issue any detecting output as long as the contents of the positional counters corresponding to the designated denominations and of the counters of higher positions are not zero, the money dispensing operations for the designated denominations are continued until a detecting signal is issued from the zero-coincidence detecting circuit 41G.

When the second automatic money dispensing mode is instructed by the arrival of the LCV signal, the zero coincidence detecting circuit 41G issues a detecting signal each time the content of the positional counter corresponding to 10,000-yen note in this example becomes zero, whereby denominations of money corresponding to the lower positional counters are successively dispensed until the contents of the lower positional counters become zero.

An example of the counter circuit 41A of the money dispensing machine will now be described with reference to FIGS. 38 through 41.

The money dispensing machine 4 comprises six positional counters DC.sub.1 through DC.sub.6 which correspond to 1 position through 100000 position respectively of the decimal notation of the money to be dispensed. The positional counters DC.sub.1 through DC.sub.6 may be reversible counters. A memory distributor MD composed of shift registers SR.sub.1 through SR.sub.6 corresponding to the six digits respectively, of the decimal notation of the money is also provided for receiving the money dispensing data transferred from the command input system 1. When a load signal generating means (not shown) detects the completion of the data transfer and generates a load signal, the signal is applied to the preset terminals L of the positional counters DC.sub.1 through DC.sub.6, and the contents in the shift registers SR.sub.1 through SR.sub.6 are thereupon transferred to the corresponding positional counters DC.sub.1 through DC.sub.6. In the drawing, TCP designates a clock pulse supply line.

Output terminals BR of the positional counters DC.sub.1 through DC.sub.4 are connected with borrowing signal gate circuits A.sub.11 through A.sub.41, respectively, each of the gate circuits comprising a two-inputs logical product gate circuit (AND gate in the illustrated example). When the content in any of the positional counters becomes 0, the level at the borrowing output terminal BR of a positional counter corresponding thereto becomes L. Thus, when the content of the counter is further subtracted by 1 and thereby changed to 9, the level of the output terminal BR is changed to H, and the content of the next counter corrsponding to the next higher position is subtracted by 1 through the gate circuit at the instant of the rise of the output level.

To the borrowing gate circuits A.sub.11 through A.sub.41, a dispensing mode designating signal LCV, which is H in the case of the first money dispensing mode and L in the case of the second money dispensing mode, is applied as a gate control signal, thereby to execute a borrowing opera