Electronic control for totaling denominations of several countries4682288Abstract An electronic totalizer countrol for a coin sorter allows the user to assign and change fractional and whole-number coin values for denominations sorted at ten coin sorting stations in the sorter. The totalizer has a liquid crystal display (LCD) that integrates several cursors with the usual digits for displaying totals. A keyboard includes a BAG COUNT key operable to select a particular coin sorting station as indicated by one of the cursors. The keyboard also has DISPLAY keys operable to display monetary totals that has been accumulated by counting signals generated at the coin stations and adding a user-entered coin value for each signal to the total for the respective denomination. Coin data is stored in display data structures in a coin station data table for advantageous operation of the LCD. Claims We claim: Description BACKGROUND OF THE INVENTION
TABLE 1
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Key Sequence for Entering Coin Value
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(a) push BAG COUNT to illuminate cursor
element under appropriate coin
processing station;
(b) push PROGRAM key
(c) push VALUE key
(d) push numeric keys 0-9 and decimal
point key as needed, up to eight
digits,
(e) push "=" key
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When the PROGRAM key is operated, the cursor element 28 along the lower edge of the display 27, and above the legend "PROGRAM" is illuminated. When the keys in the five-by-four key matrix 25 are operated, the cursor element 28 towards the lower left corner of the display 27 is actuated. Using the key sequence in TABLE 1, the coin values shown in the legend 30 in FIG. 4 can be assigned to coin stations "2"-"8". The coin denominations in the West German monetary system include the 1-, 2-, 5-, 10- and 50-pfennig denominations, as well as the 1-, 2- and 5-deutsche mark (DM) denominations. The coin values entered are fractional values relative to the DM, and are as follows: 0,01; 0,05; 0,02; 0,50; 0,10; 1,00; 2,00 and 5,00. The West German monetary system also includes a 10-DM coin. (The comma is used to represent a decimal point as is the custom in West Germany.) In France, the coin denominations available for processing are 1-, 2-, 5-, 10- and 20- and 50-centime denominations and the 1-, 2- and 10-franc denominations where one franc=100 centimes. In Great Britain, the coin denominations available for processing are the 1/2- 1-, 2-, 5-, 10- and 50-pence denominations, where one pound Sterling=100 pence. In Mexico, the coin denominations available for processing are the 1-, 5-, 10-, 20-, 25- and 50-centavo denominations, and the 1-, 5- and 10-peso denominations, where one peso=100 centavos. These examples are given to show the advantage of the invention in permitting fractional coin values to be assigned and changed. The 0.055, 0.02 and 0.20 fractional values in these other countries do not find counterparts in the U.S. monetary system, nor are 5.00 and 10.00 values in circulation in the United States. When it is desired to display a previously entered coin value for a particular station, the key sequence in the following TABLE 2 is executed. Once the coin value is displayed, a new value can be assigned by executing the sequence in TABLE 1 above.
TABLE 2
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Key Sequence for Displaying Coin Value
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(a) push BAG COUNT to select appropriate
coin processing station
(b) push PROGRAM key
(c) push VALUE key
(d) push "=" key
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In similar fashion by substituting operation of the STOPS key for the VALUE key in Tables 1 and 2, BAG STOPS can be entered and displayed. By substituting operation of the COUNTS key for the VALUE key in Table 1 a BAG COUNT can be entered. Inside the controller housing seen in FIG. 1 are the electronics for counting coins, performing calculations and interfacing the diplay 27 and the keyboard 24. As seen in FIG. 5 this hardware includes a main processor module 35 which interfaces the display 27 and the keyboard 24. The main processor 36 and its associated memory 37 provide data to a set of display drivers 38 for operating the individual digits, symbols and cursor elements of the display 27. The main processor 36 also scans the keyboard 24 by enabling columns in the key matrix through a keyboard output port 39 and by reading in key data from the rows of the key matrix through a keyboard input port 40. Over to the far right of FIG. 5 are the coin sensors 21 for COIN STATIONS 1-10. These are interfaced to the main processor module 35 by a peripheral processor module 41. This module 41 includes its own processor 42 and associated memory 43 for reading the coin counting signals through a group of debounce circuits 44 and a pair of coin I/O ports 45,46. The main processor 36 communicates with the peripheral processor 42 through a two-way communication port 47 on the main processor module 35 and communication input and output ports 48,49 on the peripheral processor module 41. The peripheral processor 42 accumulates coin count signals received from the coin sensors 21 and it also accumulates monetary values for the denominations associated with the respective coin stations based on coin values which it receives from the main processor module 35. The main processor and memory 36,37 receive COIN VALUE entries through the keyboard input port 39 and later download them to the peripheral processor and memory 42,43 where they are used in accumulating BATCH VALUES for the respective coin stations. These BATCH VALUES are then communicated from the peripheral processor and its memory 42,43 to the main processor and its memory 36,37 where they are available for display upon the entry of BATCH DISPLAY commands through the keyboard 24. The details of the hardware on the main processor module 35 are seen in FIG. 6. The main processor 36 is a CDP1802 microprocessor manufactured by RCA. The integrated circuits on the main processor module 35, including this microprocessor 36, CMOS-technology circuits. Complete information on this microprocessor is available in literature from RCA, and of particular assistance is an RCA publication entitled "User Manual for the CDP1802 COSMAC Microprocessor." In the present embodiment four system timing signals, TPA, TPB, MWR(L) and MRD(L) are coupled to other parts of the module through a control bus 34 seen in FIG. 6. Where no symbol is used in relation to a hardware signal it is a high-true signal. The symbol "(L)" is used to signify low-true signal. This microprocessor uses separate memory and I/O address buses 50,51, the memory address bus 50 including lines MA0-MA7 and the I/O address bus 51 including lines N0-N2. In this embodiment the microprocessor also uses separate memory and I/O data buses 52,53 which are coupled through bus separators 54,55 an a processor data bus 56 to the processor 36. The main processor 36 in FIG. 6 is driven by a conventional clock circuit 57 that includes a 2-MHz crystal oscillator. A display oscillator circuit 58, provided by a free-running astable multivibrator, is connected to one of the external flag inputs (INT) available on the microprocessor 36. This oscillator circuit 58 generates a signal every eighteen milliseconds. The main processor 36 responds to this maskable interrupt signal with certain instruction sequences to debounce keyboard inputs and time other events. The display oscillator 58 also generates timing signals needed for operation of the liquid crystal display (LCD) 27. Memory on the main processor module 35 includes a main program memory 59 of programmable read-only (PROM) chips for storing 8k bytes of program information. This memory is addressable in an address range from 0000(hexadecimal) to 1FFF (hexadecimal). A main read/write memory 60, formed by two random access memory (RAM) circuits, stores up to 2k bytes of data and is addressable at addresses from 2000 (hexadecimal) to 27FF (hexadecimal). When the main processor 36 couples an address to either of the memories, 56,60 it first generates a high byte of address, and then generates a low byte of address, so that a sixteen-bit address can be transmitted through the 8-bit memory address bus 50. The memory address bus is coupled to the memories 59,60 through buffers 61 and a memory address decoding circuit 62. When the high byte of address is generated, the microprocessor 36 generates the TPA control signal to latch the high address byte in the memory address decoding circuit 62. This byte is decoded to generate certain high address signals A8, A9, A10 and certain chip enable (EN) signals to the respective portions of the two memories 59,60. The main processor 36 then transmits the low byte of address through the buffers 61 to the address inputs of the respective memories 59,60. When the high address byte is transmitted it generates a signal on a MEMORY BUS ENABLE line to the bus separator 54 which couples the memory data bus 52 to the processor data bus 56 for purposes of reading and writing information between the processor 36 and the memories 59,60. The memory address decoding circuit 62 is seen in more detail in FIG. 7. There it can be seen when the high byte of address is generated on the memory address bus 50, signals on lines MA4-MA7 are transmitted to the address inputs MA0-MA3 on an "1858" memory interface circuit 63. This circuit 63 is a four-bit latch/decoder which has been developed along with many of the other CMOS-technology chips seen on the main processor module 35 for use with the CDP1802 microprocessor. These and the other ICs on both the main processor module 35 and the peripheral processor 41 module are identified in Appendix A. For complete descriptions, diagrams and specifications for the various circuits to be described on the main processor module 35 and the microprocessor module 41, reference is made to RCA catalogs and data books for RCA CMOS products and RCA 1800-series products. It should be noted regarding FIG. 7 that the address lines MA4-MA7 have not been connected in ascending order to inputs MA0-MA3, and that the "1858" receives the TPA timing signal from the main processor 36. A signal from the chip select output (CS0) on the "1858" enables four NAND gates 65 each of which enables a respective portion of the main program memory 59. Two of these four-input NAND gates 65 are enabled through one of a pair of NOR gates 66 and two other of these NAND gates are enabled through the other of the NOR gates 66. Each pair of NAND gates 65 is further distinguished by signals from the All output on an "1866" memory interface circuit 64, which is coupled through an inverter 67 to one of each pair of NAND gates 65 and is coupled directly to the other. For convenience of the illustration, the connections of the inverted and noninverted All signals have only been shown for one pair of the NAND gates 65. A fourth input on each NAND gate 65 is pulled high to the DC supply voltage (+V). Besides enabling the four portions of the program memory 59, the memory chip select signals from the NAND gates 65 are fed back to inputs on an "1866" memory interface circuit 64, the lines to the CE3 and CE2(L) inputs being connected through inverters 69. Lines MA0-MA3 of the memory address bus 50 are coupled to the "1866" circuit, which is also a specialized four-bit latch/decoder available from RCA. The "1866" provides address signals on lines A8-A10 to all portions of the main program memory 59 and it also generates a signal from its CS output to the memory data bus separator 54 in FIG. 6. The lower three bits of the high byte of address and the TPA signal are also coupled to an "1867" memory interface circuit 68 in FIG. 7, which depending upon signals received from the "1858" and the address will enable half-portions of the main read/write memory 60 through lines connecting to CS inputs on these respective portions. The main processor 36 controls the reading of data from the main program memory 59 through the MRD(L) control line and the NOR gates 66 and it controls the reading and writing of data to and from the main read/write memory 60 through the MWR(L) line connected to inputs on the RAM memory circuits. Referring back to FIG. 6, the handling of I/O addresses and data will now be described. When the main processor 36 executes instructions to enable an I/O port, signals are coupled on lines N0-N2 of the I/O address bus 51 to a first level decoder 70. Using a three line-to-eight line decoder 70 a number of I/O ports can be controlled in a single level I/O system. The modules 35,41 here use a two-level I/O system in which the I/O address signals are decoded by a first such decoder 70 to enable a general I/O port 71. A word of data is then transmitted to this general I/O port 71 and four of its bits are coupled to a second level decoder select circuit 72 to select one of a series of second level decoders 73. The second level I/O ports include the display drivers 74, the keyboard input and output ports 40,39 and the two-way communication port 47. The details of I/O decoding are seen in FIG. 8, where the I/O address bus 51 is coupled to the first level decoder 70. The TPA and TPB control signals are coupled to clock inputs "A" and "B" to mark a time when the outputs are enabled. The chip enable (CE) input is pulled high so that the circuit 70 is always enabled for receiving the clock signals. When an I/O address is generated to enable "output port 1", an enable signal is coupled from the "1" output on the first level decoder 70 to the general I/O port 71. I/O addresses also generate signals from the "2", "4", and "6" outputs of the first level decoder 70 to a group of OR gates 75 to enable the I/O data bus separator 55 seen in FIG. 5. When using a two-level I/O system, two output instructions are executed by the processor 36 to move data to a final destination such as the display drivers 74 in FIG. 6, which are also output ports for data. The output instructions may be in a sequence like the following, which is taken from the Display Routine in the 10th Section of Appendix K.
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OUT 1
OUT 4
OUT 1
OUT 6
OUT 1
OUT 5
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A pointer register in the processor 36 is initialized so that the instruction OUT 1 will output a word of data from the read/write memory 60 to "output port 1" in the first level of I/O ports. "Output port 1" corresponds to the port enabled fom the "1" output of the 1st level decoder 70 in FIG. 8. This port is the general I/O port 71. The word of data that is sent to the general I/O port 71 determines which of its outputs D3-D7 will transmit active signals. Output D3 is active in response to a word "08" (hexadecimal) to enable the two-way communication port 47 in FIG. 5 through the ENA PIO line. Output D4 is active in response to a word "10" (hexadecimal) to generate an active signal at the "1" output of the second level decoder select circuit 72 to select the first one of the second level decoders 73. Thus, if the first OUT 1 instruction listed above is executed to move the word "10" (hex) to the general I/O port 71, the next OUT 4 instruction will generate signals to the first of the decoders 73 to activate its "4" output. This will enable the display drivers 74 for driving "DIGITS 3 & 4" of the display 27. By transmitting different enable words with the various OUT 1 instructions, the second level decoders 73 can be selected, so that when the "OUT 4", "OUT 5" and "OUT 6" instructions are executed, they will select port 4, 5, or 6 controlled by a selected second level decoder 73. It can be seen in FIG. 8 that these "4", "5" and "6" ports at the second level include nine ports for driving the digits, the symbols, the decimal points and the cursor elements 28 of the display 27 and a port for enabling the keyboard ports 39 and 40. Besides enabling the display drivers 74, the enable signals from the second level decoders 73 are also coupled back through the OR gates 75 to enable the I/O data bus separator 55 in FIG. 5 so that data can be coupled to the selected I/O port at the second level. Referring next to FIG. 9, the peripheral processor module 41 includes the peripheral processor 42, which is a second CDP1802 microprocessor. This microprocessor is also driven by a clock circuit 76 including a crystal oscillator for generating clock pulses at a 2-MHz frequency. Control lines 77 for the TPA, TPB, MRD(L) and MWR(L) signals and a memory address bus with lines A0-A7 couple the processor 42 to memory through buffers 79. The memory address bus 78 couples a high byte of address to the memory address decoding circuit 80 and a low byte of address to memory with the memory data bus separator 89 being enabled from the decoding circuit 80 on the MDB ENABLE line. The peripheral read/write memory 43 is comprised of random-access memory (RAM) circuits that are addressed in a range from 1000 (hexadecimal) to 13FF (hexadecimal). In decimal terms this range of addresses is from 4k to 5k and provides 1k bytes of data storage. The peripheral program memory 81 is addressed in a range from 0000 (hexadecimal) to 07FF (hexadecimal), which can also be expressed as an address range from 0-2k. The program memory 81 stores 2k bytes of program information used by the peripheral processor 42. The memory address decoding circuit 80 is seen in detail in FIG. 10 and includes an "1858" memory interface circuit 86, and "1866" memory interface circuit 87 and an "1867" memory interface circuit 88 similar to the memory address decoding circuit 62 for the main processor module 35 that as seen in FIG. 7. The "1858" receives the high four bits A4-A7 of the high byte of address and enables either the "1866" or the NOR gate 83, from its CE0(L) and CE1(L) outputs. The "1866" generates a signal from its CS(L) output to enable the memory data bus separator 89. The "1867" enables the read/write memory 43 with a signal from its CS0(L) output to chip select (CS) inputs on the RAM circuits. Because only one PROM circuit is enabled, only two NAND gates 82 and one NOR gate 83 are necessary for coupling the chip select (CS0) line from the "1858" , the MRD(L) line from the peripheral processor 42 and the All output from the "1866". Similar to the decoding circuit described earlier, the four-input NAND gates 82 both receive the chip select output (CS0) signal from the "1858", a logic high signal from the DC supply (+V) and an output signal from the NOR gate 83. The NAND gates 82 are selected by a signal from the All output on the 1866 circuit that is coupled to one of the gates 82 through an inverter 84 and directly to the other of the gates 82. The outputs of the NAND gates 82 are connected to the CE4 and CE2 inputs on the "1866", one of the NAND gates 82 being connected to the CE2 input through an inverter 85. Referring again to FIG. 9, the peripheral processor 42 is also connected through an I/O address bus 90 with lines N0-N2 to an I/O port decoding circuit 91. This circuit enables the communication input port 48 and the communication output port 49 through an enable I/O communication (ENA I/O COMM.) line. It also enables the coin I/O ports 45,46 through the ENABLE "A" and ENABLE "B" lines seen in FIG. 9. It also enables the I/O data bus separator 94 through a DB ENABLE line so that output data can be coupled from the peripheral processor 42 and the processor data bus 95 to the I/O data bus 96 and so that coin sensing data can be read from the coin I/O ports 45,46. Coin sensing signals are coupled through coin debounce circuits 44 for COIN STATIONS 1-10 as seen in FIG. 9. The coin debounce circuits 44 for COIN STATIONS 1-8 are connected to coin I/O port "A" while the coin debounce circuits 44 for COIN STATIONS 9 and 10 are connected to coin I/O port "B". The I/O port decoding circuit 91 is seen in more detail in FIG. 11 where the I/O address bus 90 is coupled to a first level decoder 100 and a second level decoder 101 along with the TPA and TPB control lines. When a first output instruction (OUT 1) is generated by the processor 42 the N-line signals are received by the first level decoder 100 because the second level decoder 101 has not yet been enabled. The "OUT 1" instruction generates a signal at the "1" output to enable the general I/O port 102 at its CS2 input and to enable the I/O data bus separator 94 in FIG. 9 through the four-input OR gate 103 seen in FIG. 10. Data is received on the I/O data bus 96 and latched when the TPB signal is received by the general I/O port 102. The data transmitted by the "OUT 1" instruction generates signals from outputs D3 and D4 of the I/O port 102 to a second OR gate 104 to enable the second level decoder 101. A second I/O instruction can then be executed so that signals on lines N0-N2 will be decoded by the second level decoder 101 to enable I/O communication through the second level "port 2" or to enable the coin I/O ports, which are second level ports "4" and "5". When any of these is enabled, a signal is also coupled through the OR gate 103 to enable the I/O data bus separator 94 so that data can be coupled to or from the I/O communication ports 48,49 or so that coin sensing data can be read from the coin I/O ports 45,46. Referring next to FIG. 12, the main processor module 35 and the peripheral processor module 41 communicate with each other through their respective communication ports 47-49. The two-way communication port 47 on the main processor module 35 is programmable for operation in various modes. The port 47 is a CDP1851 I/O port manufactured by RCA and a specification for its operation is provided in literature available from RCA and its distributors. The port 47 is enabled in this embodiment through the first level decoder 70, the general I/O port 71 and the ENA PIO line. The ENA PIO line is also connected to enable two NAND gates 105 coupling signals to interrupt inputs I3 and I4 on the main processor 36. The N1 and N2 lines in the I/O address bus 51 are coupled to two register address inputs on the two-way communication port 47 to select either port "A" or port "B" or one of the control/status registers in in the circuit 47. Both data words and words of control information are coupled from the main processor 36 to the two-way communication port 47. The port 47 uses handshaking signals ARDY, ASTB, BRDY and BSTB to transfer data between the two modules 35,41. When data is loaded into port "A" for transfer to the communication input port 48 on the other module, an ARDY signal is generated to a clock input on the input port 48 and through an inverter 100 to an interrupt input I3 on the peripheral processor 42. This informs the peripheral processor 42 that data in the "A" port is ready for transfer. The ARDY signal is also coupled through one of the NAND gates 105 to the interrupt input I3 on the main processor 36. When the peripheral processor 42 executes a data communication routine, it will execute an instruction to enable the communication ports 48,49 through its I/O decoding circuit 91 and the ENA I/O COMM. line. This will cause data to be transferred to the communication input port 48 and a signal that the data has been taken will be generated to the ASTB input on the two-way port 47. The peripheral processor 52 clocks data on its I/O data bus 96 into the output port 49 using the TPB timing signal. When data is transferred from the communication output port 49, a BSTB signal is coupled to port "B" on the two-way communication port 47 to indicate that data has been transferred. When the main processor 36 reads the data, it will generate a signal on the BRDY line from the two-way communication port 47. The BRDY signal will be transmitted through an inverter 107 to the I4 interrupt input on the peripheral processor 42 to signal that Port "B" is empty. The BRDY line will also generate an interrupt through one of the NAND gates 105 to the I4 interrupt input on the main processor 36. Now that the hardware on the respective modules 35,41 has been described, a further understanding of the operation of the totalizer 11 can be otained from a consideration of the program instructions for directing operation of the respective processors 36,42. These instructions are relatively fixed in the PROM program memories 59,81 and are thus referred to as firmware. Appendix B contains a map of the firmware routines such as "TIMER" and "KEYBOARD MONITOR" which are executed by the main processor 36 and stored in the main program memory 59 seen in FIG. 6. Individual instructions for each routine are listed in Appendix K. Similarly, the firmware routines stored in the program memory 81 in FIG. 9 direct operation of the peripheral processor 42. These routines are identified generally in Appendix C, and specific instructions for each routine are contained in Appendix L. The addresses shown in Appendix B and C are starting addresses in hexadecimal (hex) notation. The routines may or may not fill the entire area up to the starting address of the next routine as long as the processors 36,42 continue incrementing their program counter to reach the instructions in the next routine, as for example, by executing "no operation" (NOP) instructions. Referring next to Appendix D, the most significant data in memory is stored in the COIN STATION DATA TABLE from addresses 2000 (hex) to 21CF (hex). A duplicate of this data table is stored from address 21D0 (hex) to 239F (hex) for access by a supervisory computer or for operating a printer. Referring next to Appendix E, the COIN STATION DATA TABLE stores parameter data for COIN STATIONS 1-10 in blocks of eight bytes or eight words each. The terms "words" and "bytes" both mean an eight-bit group of data in this instance, however, in other applications the term "word" is used for groups of data with different numbers of bits. Here, for example, the COIN VALUE data for STATION 1 occupies eight bytes of memory with addresses from 2000 (hex) to 2007 (hex). This pattern for COIN VALUE data is repeated for STATIONS 2-9 and down to STATION 10 where an eight-byte block of data for the coin value of STATION 10 is stored at addresses 2048-204F (hex). Next, a group of ten eight-byte blocks of data are used to store BAG STOP data for the COIN STATIONS 1-10. The BAG STOP data for STATION 1 is located at addresses 20A0-20A7 (hex) and BAG STOP data for STATIONS 2-10 continues down to the block for STATION 10 at addresses 2098-209F (hex). A "bag stop" is a count or limit which defines the number of coins in one bag. Following the BAG STOP data are ten eight-byte blocks of data for BATCH VALUE, again corresponding to COIN STATIONS 1-10. There are also ten eight-word blocks of data for the GRAND VALUES accumulated for COIN STATIONS 1-10 and there are ten eight-word blocks of data for "BAG COUNTS" for COIN STATIONS 1-10. A "bag count" is the number of coins counted, but is not to exceed the bag stop limit. For each COIN STATION there is a block of COIN VALUE data, a block of BAG STOP data, a block of BATCH VALUE data, a block of GRAND VALUE data and a block of BAG COUNT data. Each of the eight-byte blocks of data is stored in a standardized data structure which has been mapped in Appendix F. As seen there, the block of data is arranged to hold eight nibbles (four bits each) of binary-coded data (BCD) in "Words 4-7". Each nibble provides the data for one of the eight digits of the liquid crystal display 27. In "Words 0-3" are individual bits of data corresponding to the various other elements that can be illuminated in the integrated display 27. There are bits for each of the cursor elements 28 as well as for the decimal points and commas associated with the last five digits. When data in the COIN STATION DATA TABLE such as BATCH VALUE data is displayed, the main processor 36 executes the DATA TRANSFER routine starting at 13D0 (hex) in Appendix B to transfer a block of data from the COIN STATION DATA TABLE in Appendix D to an area for DISPLAY DATA at addresses 27F0-27FF. When the data is transferred to the DISPLAY DATA area it is arranged as seen in Appendix H. "Word O" data in Appendix F is moved to address 27F1 (hex) seen in Appendix H. "Word 1" data in Appendix F is moved to address 27F3 (hex) seen in Appendix H. Similarly all eight words in a block of data as shown in Appendix F are moved to the odd-numbered lines in the sixteen-byte area for DISPLAY DATA seen in Appendix H. When the main processor 36 executes the DISPLAY ROUTINE starting at address 1540 (hex) in Appendix B, it will load the enable words seen in the even-numbered lines from 27F0-27FE (hex) in Appendix H. These are words that will be transmitted to the general I/P port 71 in FIG. 8 to select one of the second level decoders 73. The word "30 (hex)", for example, will enable the third decoder 73 in FIG. 8 so that data can be sent to the drivers for displaying the SYMBOLS, the CURSORS FOR COIN STATIONS 1-8 and the COMMA/DECIMAL POINT elements. In this way the main processor 36 uses the data stored in the data structures in the COIN STATION DATA TABLE to drive the display 27. Referring again to Appendix E it will be seen that besides the BATCH VALUE data for the COIN STATIONS 1-10 the main memory also stores a BATCH TOTAL VALUE at address 20F8-20FF (hex), a SUBTOTAL VALUE at addresses 2100-2107 (hex) and a GRAND TOTAL VALUE at addresses 2160-2167 (hex) as well as MEMORY VALUES and I.D. data. All of this data is stored in data structures as shown in Appendix F. Referring next to Appendix I, the read/write memory 43 associated with the peripheral processor 42 also stores a COIN STATION DATA TABLE as well as providing a scratchpad area at addresses 1350-13FF (hex). This COIN STATION DATA TABLE is somewhat more limited as seen in Appendix J. It does include eight-word blocks of data for BATCH VALUES, COIN VALUES. BAG STOPS and BAG COUNTS at each COIN STATION. It does not, however, provide an area for storing GRAND VALUES as the peripheral processor module 41 is "batch-oriented". Each of the eight-byte blocks in Appendix J conforms to the data structure of Appendix F and corresponds to a counterpart in the main read/write memory 37. Referring again to Appendix B, when power is supplied to the main processor 36 in FIG. 5, it executes the INITIALIZATION routine starting at 0000 (hex) to clear the COIN STATION DATA TABLE in the main read/write memory 37. When there is a "0" in the COIN VALUE data block for a particular COIN STATION, the station is seen as "off" by the totalizer 11. When a coin value for a denomination is entered by executing the key sequence in Table 1 discussed earlier, it will result in data being entered in the appropriate COIN VALUE block in the data table. When this block of data is transferred to the COIN STATION DATA TABLE in the peripheral read/write memory 43 and detected by the peripheral processor 42, the coin station is activated from the viewpoint of the totalizer 11. Referring again to Appendix B the TIMER routine starting at 0300 (hex) is executed when the processor 36 responds to the maskable interrupt signal it receives every eighteen milliseconds. This routine interfaces the hardware signal to other firmware routines to debounce keyboard inputs and to assure a periodic exchange of data between the COIN STATION DATA TABLE on the main processor module 35 and the COIN STATION DATA TABLE on the peripheral processor module 41. Following the TIMER routine in Appendix B is the KEYBOARD MONITOR routine beginning at address 0340 (hex). The KEYBOARD MONITOR routine utilizes a block of KEYBOARD INPUT DATA stored at addresses 2710-271F (hex) as seen in Appendix D. The organization of this data is seen in more detail in Appendix G, and is similar to the DISPLAY DATA in alternating data received from the keyboard with enable words used to activate the keyboard input and output ports 39, 40. In executing the KEYBOARD MONITOR routine, the main processor 36 transmits enable words stored at addresses 2711 and 2712 (hex). The first enable word (40hex) selects the keyboard output port 39 through output 4 on the fourth decoder 73 in FIG. 8. The second enable word (80 hex) at address 2712 (hex) in Appendix G is a data word that, when loaded into the keyboard output port 39, enables the five columns in the key matrix 24. Next, an input instruction is executed. This instruction uses the word at address 2713 (hex) in Appendix G to enable the input port to read six bits of data from six rows that intersect the columns in the key matrix 24. This "column 1" data is then stored at address 2714 (hex) in Appendix G. The column enable word is changed to enable the other columns through the output port 39, and the next enable word (40 hex) is transmitted to the input port 40, where row data is then read for column 2. By repeating this sequence, keyboard data for the five columns is read into memory at address 2714, 2716, 2718, 271A and 271C (hex) as seen in Appendix G. The STATUS routine is a key sorting routine in which keyboard input data is analyzed to determine which keys have been operated and in what sequence. When a key sequence corresponding to a user command is entered, the main processor 36, operating under the control of the STATUS routine, will set individual bits in a CONTROL WORD stored at 2708 (hex) in the main read/write memory 37 as represented in Appendix D. The CONTROL WORD contains flag bits that call for execution of KEYBOARD MONITOR routine the DATA COMMUNICATION routine, the ERROR routine, DATA TRANSFER routine, and the DISPLAY routine seen in Appendix B. Depending upon the command that is detected, one or more of these bits is set. As the main processor 36 proceeds through these routines in the order seen in Appendix B, it will either execute or skip the above five routines according to which bits of the control word are set. For example, when COIN VALUES are entered by pushing the "=" key, the STATUS routine sets the control bit for execution of the DATA COMMUNICATION routine. When this routine is reached and executed, the main processor 36 downloads the new COIN VALUE to the peripheral processor module 41. If the COIN VALUE at a particular coin station is changed from "0" to some fractional denomination such as "0.10", this will be seen by the processor modules 35,41 as activating the coin station. Referring to FIGS. 5, 6 and 9 the main processor 36 responds to the various commands entered through the keyboard 24 to send single blocks of COIN VALUE data, single blocks of BAG STOP data, ten-word blocks of COIN VALUE data or ten-word blocks of BAG STOP data to the COIN STATION DATA TABLE in the peripheral read/write memory 43. The main processor 36 can also signal the peripheral processor 42 through the programmable two-way communication port 47 to send BAG COUNT data and BATCH VALUE data for updating the COIN STATION DATA TABLE in the main read/write memory 37. From there, the data can be used to drive the liquid crystal display 27 in response to display commands entered through the keyboard 24. When new COIN VALUES and BAG STOPS are entered through the keyboard, they are moved from the KEYBOARD & STATUS AREA at addresses 2720-274F (hex) in Appendix B to an 8-WORD TEMPORARY STORAGE area at addresses 2700-2707 (hex) through execution of the STATUS routine. New COIN VALUE data is stored in this area until a command is completed, so that data in the COIN STATION DATA TABLE will not be erased prematurely. The DISPLAY routine is executed as the keys are examined to move new COIN VALUE data to the DISPLAY DATA area so that new COIN VALUE data can be displayed as it is being entered. When the data is entered, which occurs when an "=" key is operated, the STATUS routine sets a bit in the CONTROL WORD to execute the DATA TRANSFER routine seen in Appendix B. The DATA TRANSFER routine is then executed to move the data from the TEMPORARY STORAGE AREA to the COIN STATION DATA TABLE. The STATUS routine monitors the operation of the BAG COUNT key to maintain a pointer to the appropriate block of data in the COIN STATION DATA TABLE. The DATA TRANSFER routine is a general purpose routine for moving an eight-word block of data from one area of read/write memory to another. The DATA TRANSFER routine is also used to move data such as BATCH VALUES, GRAND VALUES, and BAG COUNTS from the COIN STATION DATA TABLE to the DISPLAY AREA. Since this data is not entered through the keyboard 24, it can be moved directly to the DISPLAY DATA area, rather than through the TEMPORARY STORAGE area. When power is supplied to the peripheral processor 42 in FIG. 9, it begins executing the instructions in the INITIALIZATION & COIN POLL portion of its firmware. This portion is represented generally in Appendix C and the individual instructions are listed in appendix L. During initialization the processor 42 executes instructions to check for hardware faults in the memories 43,81 and in the coin I/O ports 45,46. It also initilizes its own registers and certain words in the scratchpad area of its associated read/write memory 43. If no hardware faults are detected, the processor enters the COIN POLL portion of its firmware in which data is read from the coin I/O ports 45,46. This is binary-coded data, which must be checked for "debounce" of the coin sensors 21 and then converted to the BCD data used by the data structures of the COIN STATION DATA TABLES. The processor "debounces" the coin data by reading the coin I/O ports 45,46 at least twice to detect a high/low transition, before accepting the coin data for further processing. If a coin is detected at one instant, its movement beyond the sensor must also be detected before the coin sensing data is processed further. Otherwise, a coin could linger at a sensor 21 and cause it to be counted twice. The coin station debounce circuits 44 are multivibrator circuits operated in a retriggerable 1-shot mode. When a coin sensing signals is detected at the input of a coin debounce circuit 44, its output will change state for three milliseconds. At the end of this time, the multivibrator "times out" and its output returns to its original state. If a coin lingers at a sensor 21 it will retrigger the debounce circuit for an additional three-millisecond intervals until its departure. During the COIN POLL sequence, the peripheral processor checks its interrupt inputs I3 and I4 to see if the main processor 36 is signalling for communication. When that occurs, the peripheral processor will jump to a DATA COMMUNICATION routine represented in Appendix C. The individual instructions for this routine are listed in Appendix L. Assuming that an interrupt signal has not been received by the peripheral processor 42, it will then update the BAG COUNT and the BATCH VALUE data in its COIN STATION DATA TABLE. It also checks the BAG COUNTS against the BAG STOPS, and if a BAG STOP is reached, a bit will be set to cause the main processor 36 to stop the motor that drives the coin sorter 10. The BAG COUNTS for the respective coin stations are updated by adding the number of coin count signals for each station to the respective data blocks in the COIN STATION DATA TABLE. This requires conversion of the BCD data to binary data for the addition, and the conversion of the sum back to BCD data. These operations are performed through execution of an ADD routine represented in Appendix C and listed in Appendix L. BATCH VALUES are also updated using the ADD routine. For each coin, such as a dime, a COIN VALUE of 0.10 which has been stored in the DATA TABLE is added to the BATCH VALUE for each new coin count that has been added to the BAG COUNT total. There are eight types of information communicated between the main processor 36 and the peripheral processor 42. Two of these are the start motor and stop motor commands. The main processor 36 can also signal the peripheral processor 42 to send BAG COUNTS and BATCH VALUES. The main processor can also signal the peripheral processor that the batch is complete, in which case the peripheral processor 42 will clear the BATCH VALUES and BAG COUNTS from its coin station data table. The main processor 36 can also signal the peripheral processor 42 that it is sending COIN VALUES and BAG STOPS for individual stations, or for all ten stations. When executing its DATA COMMUNICATION routine the main processor 36 can enter a block transfer mode where eight words of data will be sequentially transmitted or received from the peripheral processor 42. The peripheral processor 42, on the other hand, transfers but a single word each cycle of its DATA COMMUNICATION routine due to the rapid scan rate of the I/O ports 45,46 that is needed to count coins. Those skilled in the art will appreciate that this is but one example of an embodiment for carrying out the essentials of the invention, and that certain details could be varied without departing from the teaching herein. Therefore, to apprise the public of that which is essential to the invention, the following claims are made.
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Appendix A
IC COMPONENTS
Ref.
Circuit No. Description
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Main Processor Module
Main Processor
36 CDP1802 microprocessor*
Display Oscillator
58 CD4047B multivibrator
circuit
Address and 61 Two CD4050B hex
Control Buffers noninverting buffers
Main Program 59 Four 2716 2k x 8-bit
Memory programmable read-only
memories manufactured
by Intel Corp.
Main Read/Write
60 Four MWS5114 1k x 4-bit
Memory static random access
memories
Bus Separators
54,55 Two CDP1856 and two CDP1857
4-bit buffers/bus separators
1st Level Decoder
70 CDP1853 3 line-to-8 line
decoder
General I/O Port
71 One CDP1852 8-bit
input/output port
2nd Level Decoder
72 One CD4028B BCD-to-decimal
Select Circuit (4 line-to-10 line)
decoder
2nd Level Decoders
73 Four CDP1853 3 line-to-
8 line decoders
Display Drivers
74 Eight CD4054B latch/
4-segment display drivers
and eight CD4056B 4-bit
latch/7-segment display
drivers
Keyboard Input Port
39,40 Two CDP1852 8-bit I/O
and Keyboard ports
Output Port
Two-Way Commu-
47 CDP1851 Programmable
nication Port I/O port
" 1858" 63 CDP1858 4-bit latch/decoder
"1866" 64 CDP1866 4-bit latch/decoder
"1867" 68 CDP1867 4-bit latch/decoder
Inverters 67,69 CD4069B hex inverters
NOR gates 66 CD4001B quad 2-input
NOR gates
NAND gates 65 Two CD4012B dual
4-input NAND gates
OR gates 75 Two CD4078B 8-input OR
gates and one CD4071B quad
2-input OR gates
NAND gates 105 CD4011B 2-input NAND gates
Peripheral Processor Module
Periph. Processor
42 CDP1802 microprocessor
Address and 79 Two CD4050B hex non-
Control Buffers inverting buffers
Periph. Program
81 One 2716 2k x 8-bit
Memory programmable read-only
memory manufactured
by Intel Corp.
Peripheral Read/
43 Two MWS 5114 1k x 4-bit
Write Memory static random access
memories
Bus Separators
89,94 Two CDP1856 and two
CDP1857 4-bit buffer/bus
separators
Comm. Input Port
48,49 Two CDP1852 8-bit I/O
and Comm. Output ports
Coin I/O Ports
45,46 Two CDP1852 8-bit I/O
ports
Coin Debounce
44 Ten CD4047B multivibrator
Circuits circuits
"1858" 86 CDP1858 4-bit
latch/decoder
"1866" 87 CDP1866 4-bit
latch/decode
"1867" 88 CDP1867 4-bit
latch/decoder
Inverters 84, CD4069B hex inverters
85,
106,
107
NAND gates 82 CD4012B dual 4-input
NAND gates
NOR gate 83 CD4001B quad 2-input
NOR gate
1st Level Decoder
100, Two CDP1853 3 line-to-8
& 2nd Level Decoder
101 line decoders
General I/O Port
102 CDP1852 8-bit I/O port
OR gates 103, CD4072B dual 4-input
104 OR gates
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*All circuits available from RCA unless a different manufacturer is
specified
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