Data processor for FM multiplex broadcast6128390Abstract A second random number generator (102) sets a scramble key data included in a transmitted/received data to an initial value, and it generates predetermined second random numbers. A first random number generator (101) generates first random numbers from the second random numbers supplied by the second random number generator (102). The generation of the first random numbers by the first random number generator (101) is controlled by an output from a first control circuit (103). Since the output from the first control circuit (103) is changed in accordance with a service identification code SI, the first random numbers generated from the first random number generator (101) are changed. The first random numbers are input to a gate circuit (105) via a second control circuit (104). The second control circuit (104) inhibits the output of the first random numbers in accordance with the SI value. In such a manner, scrambling or descrambling is controlled in the gate circuit (105). Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 1
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Service Identification Code (SI)
Contents
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0 Not defined
1 General information
(sequential reception)
2 General information level 1
(recording reception)
3 General information level 2
(recording reception)
4 Traffic information level 1
5 Traffic information level 2
6 Traffic information level 3
. Not defined
.
D Additional information
E Optional information
F Application signal
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For example, SI=1, 2, 3 is general information. The information from "watch radio" currently being broadcasted by JFN network belongs to the general information. SI=4, 5, 6 is road traffic information. SI=D is additional information such as a broadcasting station name and time. SI=E is optional information such as a program index data. SI=F is the data to be transmitted in the case that the broadcasting station needs it in the application. Furthermore, the corresponding SI is provided for services such as a pager and DGPS. Accordingly, the service identification code (SI) indicates the service contents of the FM multiplex broadcast. The scramble control is carried out in accordance with the SI value, whereby the scramble can be controlled in accordance with the service contents. Accordingly, it is not necessary to introduce another new identification code, and the scramble control which reduces the load of the broadcasting station and the receiver can be carried out. For example, when the general information level 1 identified by SI=2 which is not scrambled and the scrambled traffic information level 2 identified by SI=5 are mixed and transmitted from the same broadcasting station, the transmitter can determine whether or not the information is scrambled in accordance with the content of SI. The receiver can also judge whether or not the information is scrambled in accordance with SI. Furthermore, when the traffic information level 3 identified SI=6 is also scrambled, even if the same scramble key data or the like as SI=5 is used, since the processing in the nonlinear logic circuit is carried out in accordance with the SI, the different scrambling random numbers can be generated. As described above, according to the present invention, a random number signal for scrambling can be controlled by the service identification code included in the FM multiplex broadcast data. Thus, scrambling which reduces the load of the transmitter and receiver and has such a high security that it is difficult to decode can be carried out. More specifically, a basic format of the FM multiplex broadcast is effectively used, whereby effective scramble control can be carried out. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the overall constitution of a data processor 100 in an embodiment of the present invention. FIG. 2 shows a concrete circuit example of a first control circuit 103 and a nonlinear logic circuit 109 in the embodiment. FIG. 3 shows a constitutional example of a data packet. FIGS. 4(A) and 4(B) show truth tables for describing an operation of the first control circuit 103 in the embodiment. FIG. 5 shows a concrete constitutional example of a second control circuit 104 in the embodiment. FIG. 6 shows a truth table for describing the operation of the second control circuit 104 in the embodiment. FIG. 7 is a block diagram of an FM multiplex broadcasting receiver using the data processor in the embodiment. FIG. 8 shows another constitutional example of the first control circuit in the embodiment. FIG. 9 shows a state transition of the first control circuit shown in FIG. 8. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a suitable embodiment of the present invention will be described below with reference to the accompanying drawings. "Overall Constitution" FIG. 1 is a block diagram showing a schematic constitution of a data processor 100 in the embodiment. A first random number generator 101 outputs random numbers for scrambling or descrambling under the control of a first control circuit 103. A second random number generator 102 determines an initial value in accordance with scramble key data included in an FM multiplex broadcasting data, and it generates the random number, that is, a data to be input to the first random number generator 101, in accordance with a data group number and a data packet number included in a prefix. The first control circuit 103 executes an exclusive OR operation of a service identification code (SI) and low-order 4 bits of the data packet number, and supplies its output to nonlinear logic circuits (109 to 111). A second control circuit 104 controls whether the output from the first random number generator 101 is valid or invalid (zero output) in accordance with the service identification code (SI). A gate circuit 105 executes the exclusive OR operation of the FM multiplex broadcasting data and the output from the second control circuit 104. PN generators 106, 107, 108 generate an L-bit PN signal, an M-bit PN signal and an N-bit PN signal in accordance with the output from the second control circuit 104, respectively. The nonlinear logic circuits 109, 110, 111 receive the outputs from the PN generators 106, 107, 108 and the output from the first control circuit 103 as input signals, and they output a logic operation as a result of the input signals. A switch circuit 112 is controlled by the nonlinear logic circuit 110, and it outputs the PN signal corrected and controlled by the nonlinear logic circuit 109 or 111. In such circuits, the SI, the data packet number, the data group number and the scramble key data are determined in accordance with the data to be transmitted or the received data, and they are input to the data processor. The second random number generator 102 generates predetermined random numbers in accordance with the scramble key data, the data group number and the data packet number. In this example, the random numbers generated by the second random number generator 102 are divided into three, and the divided random numbers are supplied to the PN generators 106, 107, 108. The PN generators 106, 107, 108 use one part of the supplied random numbers, and they generate the corresponding PN signal independently. The outputs from the PN generators 106, 107, 108 are input to the nonlinear logic circuits 109, 110, 111, respectively. The signal from the first control circuit 103 is input to the respective nonlinear logic circuits 109, 110, 111. Each of the nonlinear logic circuits 109, 110, 111 executes a predetermined logical sum of the two signals to be input, and each nonlinear logic circuit outputs a 1-bit signal. The first control circuit 103 generates the signal from (the low-order 4 bits of) the data packet number. The outputs from the nonlinear logic circuits 109, 110, 111 are different from one another in accordance with the generated signal. More specifically, if the SI value is different, the output from the first control circuit 103 is different. Accordingly, the outputs from the nonlinear logic circuits 109, 110, 111 are different from one another. Next, the outputs from the nonlinear logic circuits 109, 110, 111 are input to the switch circuit 112. The switch circuit 112 selects the output from either nonlinear logic circuit 109 or 111 in accordance with the value from the nonlinear logic circuit 110. Accordingly, the 1-bit width random numbers are sequentially output as the output from the first random numbers generator 101 from the switch circuit 112. The random numbers are changed in accordance with the SI value. Furthermore, the output from the first random number generator 101 is input to the second control circuit 104. The SI is provided for the second control circuit 104. The second control circuit 104 controls whether or not the random numbers from the first random number generator 101 are output in accordance with the SI value. The output from the second control circuit 104 is provided for the gate circuit 105, and it is processed together with the input data. That is to say, at a transmitter side, the input data is the transmitted data to be scrambled. At a receiver side, the input data is the received data to be descrambled. The random numbers from the second control circuit 104 are processed together with the input data, whereby scrambling or descrambling processing is carried out. As described above, the second control circuit 104 controls whether or not the random numbers from the first random number generator 101 are output in accordance with the SI value. In the case where the service is not to be scrambled, the second control circuit 104 inhibits the output of the random numbers in accordance with the SI value. Accordingly, the scrambling or descrambling processing is not carried out in the gate circuit 105, and the input data is an output as it is. On the other hand, according to the SI value, in the case where the service is to be scrambled, the second control circuit 104 provides the random number from the first random number generator 101 for the gate circuit 105. Accordingly, the scrambling or descrambling processing is carried out in the gate circuit 105. Furthermore, the first control circuit 103 changes the output signal in accordance with the SI value. Accordingly, the random numbers output from the first random number generator 101 are changed in accordance with the SI value. Thus, the random numbers to be used for the scrambling processing can be easily changed in accordance with the contents of the service. "First Control Circuit and Nonlinear Logic Circuit" FIG. 2 shows a concrete circuit example of the first control circuit 103 and the nonlinear logic circuit 109. Note that the nonlinear logic circuits 110 and 111 may also be the same as the nonlinear logic circuit 109. The first control circuit 103 comprises four exclusive OR circuits 201, 202, 203, 204. The 4-bit service identification codes (b1, b2, b3, b4) and the low-order four bits (b23, b24, b25, b26) of the data packet number are input to each of the exclusive OR circuits 201, 202, 203, 204, respectively. Each of the exclusive OR circuits executes the exclusive OR, and it outputs C1, C2, C3, C4. Accordingly, the outputs C1, C2, C3, C4 are determined in accordance with the SI value and (the low-order four bits of) the data packet number value, respectively. Four AND gates 205, 206, 207, 208 are disposed in the nonlinear logic circuit 109, and they execute a logical product of the signal in the nonlinear logic circuit 109 and the outputs C1, C2, C3, C4. The AND gate 205 executes an AND of the output C1 and the inverted signal, that is, the second-bit signal from the PN generator 106 inverted by an inverter 211. The AND gate 206 executes the AND of the output C2 and the f-bit and g-bit signals from the PN generator 106. The AND gate 207 executes the AND of the output C3 and the inverted signal, that is, the i-bit signal from the PN generator 106 inverted by an inverter 212. The AND gate 208 executes the AND of the output C4 and the j-bit and k-bit signals from the PN generator 106. Furthermore, the outputs from the AND gates 206, 207 are input to an OR gate 209. The output from the AND gate 208 and the first-bit signal from the PN generator 106 are input to an OR gate 210. The first-bit signal from the PN generator 106, the outputs from the AND gates 205, 206 and the outputs from the OR gates 209, 210 are input to an exclusive OR circuit 213. The exclusive OR of the five signals is executed in the exclusive OR circuit 213, and it is output from the nonlinear logic circuit 109. In such a logic operation, the output from the PN generator 106 is modified in accordance with the SI value. "Data Packet" FIG. 3 shows a constitutional example of the data packet. As shown in FIG. 3, a 176-bit data packet comprises a prefix portion having a head of 32 bits (b1 to b32) and a data block portion having a tail of 144 bits. B1 to b4 in the prefix portion indicate the service identification number (SI), b9 to b22 indicate the data group number, and b23 to b32 indicate the data packet number. At the transmitter side, the SI, the data group number and the data packet number are determined in accordance with the data to be transmitted, and they are used so that the scrambling random numbers corresponding to the data packet are generated. On the other hand, at the receiver side, the SI, the data group number and the data packet number are extracted from the prefix of the received data, and they are used so that the scrambling random numbers corresponding to the data packet are generated. Note that the scramble key data is also described at such a portion as to not be scrambled. "Operation of the First Control Circuit" FIGS. 4(A) and 4(B) are truth tables for describing the operation of the first control circuit 103 shown in FIG. 2. In this example, since the different scramble processing is carried out in the case of SI=5 and SI=6, the outputs (C1, C2, C3, C4) from the first control circuit in the case of SI=5 and SI=6 are shown in FIGS. 4(A) and 4(B). Note that FIGS. 4(A) and 4(B) show such a case where there are only four kinds of the low-order four bits of the data packet number. Thus, in the case of SI=5, four other kinds of outputs (C1, C2, C3, C4) are obtained. In the case of SI=6, another further four kinds of outputs (C1, C2, C3, C4) are obtained. It can seen that all the outputs are different from one another. Accordingly, if the SI values 5 and 6 are input to the nonlinear logic circuits 109, 110, 111, the different outputs can be naturally obtained from the nonlinear logic circuits. "Second Control Circuit" FIG. 5 shows a concrete circuit example of the second control circuit 104. The second control circuit 104 comprises an inverter 501, an exclusive OR circuit 502 and AND gates 503, 504. B1 and b2 in SI are input to the exclusive OR circuit 502, and the output is input to the AND gate 503. Furthermore, b3 is input to the AND gate 503 as it is. B4 is inverted by the inverter 501, and it is input to the AND gate 503. Moreover, the AND gate 503 executes the AND of the input three signals, and it outputs an output signal SC 2. The output SC 2 from the AND gate 503 and the output from the first random number generator 101 are input to the AND gate 504, and the AND gate 504 executes the AND of both these outputs. FIG. 6 is a truth table for describing the operation of the second control circuit. In this example, since SC 2=0 is obtained except for the case of SI=5 and SI=6, the output SC 1=0 is naturally obtained. Furthermore, in the case of SI=5 and SI=6, SC 2=1 is obtained, so that SC 1=(the output from the first random number generator) is obtained. Accordingly, in the exclusive OR circuit 105, in the case of SI=5, 6, the scrambling or descrambling processing is carried out. "Overall Constitution of the System" FIG. 7 is a block diagram of an FM multiplex broadcast receiver using the data processor in the embodiment. FIG. 7. shows an application example of the descrambling processing at the receiver side. It should be noted that the scrambling processing at the transmitter side of a broadcasting station is also substantially the same as the above method. That is, in the case of transmission, the output from the data processor is modulated and transmitted. In the case of reception, the received data is processed together with the random numbers so as to be descrambled. In the first place, the signal which is transmitted from a desired station and received by an antenna 701 is extracted as an intermediate frequency (IF) signal at a front end 702. The signal is amplified in an IF amplifier 703, and it is detected in an FM detector 704. A usual FM broadcasting signal is output from the FM detector 704. On the other hand, the detected signal is also supplied to a 76-kHz band pass filter (BPF) 705, and an FM multiplex data signal is extracted. The signal output from the band pass filter 705 is demodulated in an L-MSK demodulating portion 706. The demodulated signal is regenerated in a synchronous reproducing circuit 707, and an error of the generated signal is corrected in an error correcting circuit 708. The corrected signal is supplied to the data processor 100 as the packet data. As described above, the descrambling processing is carried out. The output from the data processor 100 is supplied to an application microcomputer 709, where a necessary processing is carried out. The received FM multiplex data is displayed in a display 710. "Another Constitutional Example of the First Control Circuit" Furthermore, in the above example, the first control circuit 103 is constituted of the four exclusive OR circuits, but this constitution is not restrictive. The first control circuit 103 may be constituted of a combination of the AND gate, the OR gate and the like, or a combination of a flip-flop circuit and the OR gate. FIG. 8 shows another constitutional example (example 2) of the first control circuit 103. In this example, the signals C1, C2, C3, C4 controlled by the SI alone are output. That is to say, this circuit is a PN generating circuit (x4+x+1) in which the SI value is defined as the initial value. The first control circuit 103 comprises a timing generating circuit 801, flip-flop circuits 802, 803, 804, 805 and an exclusive OR circuit 806. The timing generating circuit 801 supplies a preset clock P which sets an initial timing (a timing in synchronization with the first random number generator 101) for generating the data and a clock CK in synchronization with a data clock to each preset terminal and clock input terminal of each flip-flop circuit 802 to 805. Furthermore, b1 to b4 in the SI is supplied to each initial value input terminal of each flip-flop circuit 802 to 805. Moreover, C1 to C4 are output from the flip-flop circuits 802 to 805, respectively. The output from the flip-flop circuit 805 is input to a data input terminal of the flip-flop circuit 802. The output from the flip-flop circuit 802 is input to the exclusive OR circuit 806. The output from the flip-flop circuit 805 is also input to the exclusive OR circuit 806. The exclusive OR of both the signals is executed in the exclusive OR circuit 806, and the output from the exclusive OR circuit 806 is input to the flip-flop circuit 803. The output from the flip-flop circuit 803 is input to the flip-flop circuit 804. The output from the flip-flop circuit 804 is input to the flip-flop circuit 805. In such a constitution, for example, if SI=5 (b1=1, b2=0, b3=1, b4=0) is preset to the initial value, the output states (C1, C2, C3, C4) are changed whenever the clock CK is input. At a first clock, the outputs (C1, C2, C3, C4) are (0, 1, 0, 1). At a second clock, the outputs (C1, C2, C3, C4) are (1, 1, 1, 0). At a sixteenth clock, the output states return to those of the first clock. FIG. 9 shows a state transition table of the first control circuit 103 in such a constitution. "Other Constitutions" Furthermore, in an embodiment of FIG. 1, the nonlinear logic circuits 109, 110, 111 are controlled by the same first control circuit 103, but these nonlinear logic circuits 109, 110, 111 may also be controlled without any problem by a different first control circuit 103.
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