Mode 4 reply decoder5001751Abstract A reply decoder (30) for declaring mode 4 replies when used with a KIR cryptograph computer (25) is described including timing logic (114), memory (112) for storing mode 4 replies and logic circuitry for analyzing replies stored in the memory (112). The invention further provides logic circuitry for detecting railing (117) i.e., successive replies, for detecting garbled or overlapping replies (123), for providing a floating density value window (114, 120) for summing the replies in nonselected reply positions and for target start/stop determination (215) based on selected criteria. The invention overcomes the problem of declaring excessive mode 4 replies which over burden the subsequent reply processing in a reply processor (50). Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE I
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RAILING WINDOW WIDTH TABLE
Railing
Window RDS RWW n lines
Width 2 1 0 (435)
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4 0 0 0 4 no gates enabled
5 0 0 1 5
6 0 1 0 5, 6
7 0 1 1 5, 6, 7
8 1 0 0 5, 6, 7, 8
9 1 0 1 5, 6, 7, 8, 9
10 1 1 0 5, 6, 7, 8, 9, 10
(not used)
1 1 1 (not used)
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When signal RDS3 equals logic zero, railing adder tree 451 and comparator 456 look for consecutive railed replies equal to RWW from railing detector register 449 shown in FIG. 4B. When RDS3 equals logic 1, railing adder tree 451 and comparator 456 look for consecutive railed replies equal to RWW minus two since when signal RDS3 equals a logic one, AND gate 439 adds two (2) to the railing adder tree. The output of railing adder tree 451 is coupled by way of four leads 452 through latch 453 over four leads 454 to inputs A1-A4 of magnitude comparator 456 which has an output over lead 457 at such times as the magnitude of the signals attached to inputs A1-A4 equal or exceed the magnitude of the signals coupled to inputs B1-B4. The signal on leads 454 represent the number of railed replies summed in railing adder tree 451. In operation of FIG. 4B, rail pulses 322 which have passed through the blurring gates of FIG. 4A are shifted into railing detector register 449 which may consist of 113-stages, which has a multiplicity of taps 450 which are arranged at 14 clock (1.75 microseconds) intervals. The 1.75 microsecond interval corresponds to the same pulse spacing as mode 4 reply pulses on lead 110 shown in FIG. 1. The 18.5 microsecond advance look of the railing input register 412 allows time to check up to 10 pulse interval positions for reply pulses received on lead 110. Referring to FIG. 4A, the nominal position centertap 427 of the three always enabled input shift register taps of register 412 is delayed an additional 0.75 microseconds to provide a total 19.25 microsecond delay. The 19.25 microsecond delay is equal to 11 intervals at 1.75 microseconds. Therefore, any railing pulses present at or near correct time alignment with the correct reply position will be stored in the railing detector register 449 shown in FIG. 4B. Referring to FIG. 4B, railing threshold i.e, number of railing pulses present at these look positions which contribute to the railing decision, is controlled by 4 setup lines RDS0 on lead 430 through RDS3 on lead 433. Signals RDS0 through RDS3 control the following actions: (1) 3:8 line decoder 434 sets railing window width from 4 to 10 pulse interval positions to enable AND gates 440 through 445. Railing window width deriviation is shown in Table I. (2) The setup MSB, RDS3 on lead 433 determines whether railing threshold is (n) or (n-2). When n-2 railing is selected, RDS3 on lead 433 enables AND gate 439, which adds the value 2 to the existing railing detection count when railing is present at the CAR14 position on lead 124 originating from shift register 512 shown in FIG. 5. (3) Inverter 437 adds the value 4 to the octal value of the three LSBs, because 4 is a minimum window width, to form 4-bit threshold values from 4 through 10 for octal setup values of 0 through 6. Threshold value 455 is applied to magnitude comparator 456 and, if railing adder tree 451 latched output value 454 equals or exceeds this threshold, A equal or greater than B than output 457 will go high. (4) Referring to FIG. 4C, the 4-bit threshold 455 is also applied to 2:1 multiplexer 463 as the initial number or replies (n-1) to be inhibited ("railed") following the initial reply which always will be declared using the present circuitry. Referring to FIG. 4C the outputs 472 of decoder 471 are coupled to inputs A-D of 4-bit counter 473 the output of decoder 471 represents the 1's complement plus 1 of rail gate width. Input of A of counter 473 is always high. At such times as the signal on lead 457 is high counter 473 loads the outputs 472 into counter 473. An 8 MHz clock is coupled to a clock input of counter 473. The output of counter 473 leads 474 are coupled to logic 475 which decodes count 0. The output of logic 475 is coupled to the enable input of counter 473 and to a select input of multiplexer 463. At such times as logic 475 decodes count 0 of counter 473, multiplexer 463 selects A inputs. The output of multiplexer 463 is coupled via leads 464 through delay 465 which has a delay of 1 clock time having an output on leads 466 which are coupled to respective inputs of 4-bit adder 467 and gate 468 to provide in effect a subtractor of the value 1 from the value on the leads 466 when ever that value is other than zero. The output of adder 467 is coupled over leads 469 through delay 470 which may for example 2 clock times having an output over leads to an input of delay 461 which may have a delay of 11 clock times. The output of delay 461 is coupled over leads 462 to the A inputs of multiplexer 463. Leads 460 carrying signals RD1-RD4 are coupled to respective inputs of OR gate 477 having an output coupled to the data input of register 478. Register 478 may have for example 10 stages. An 8 MHz clock is coupled to register 478. Output stages 10-7 are coupled over leads 487 to respective inputs of AND gates 479-482 each having outputs coupled to respective inputs of OR gate 483 having an output over lead 122, signal RAIL-12. A second input of AND gates 479-482 is coupled to respective signals RGW3, RGW5, RGW7 and RGW9. Delay 461, multiplexer 463, delay 465, adder 467 and delay 470 are coupled in series and form a recirculating rail flag shift register 484 for shifting 4-bits of data through 14 clock intervals. Referring further to FIG. 4C, at times when A is equal to or greater than B, 4-bit counter 473 is loaded with the 1s complement of the 2-bit value of railing gate width (blurring), plus 1, (15+1-RGW n), where (RGW n) is a value from 0 to 4 provided by setup inputs LRGW0 485 and LRGWl 486. These input enable blurring gates 419 through 424, FIG. 4A, and they also provide compensating delay equal to 1/2 of the position blurring window width so that the 4-bit data circulating in railing flag register 484 shown in FIG. 4C is synchronized with the centertap of railing input register 412, shown in FIG. 4A. Referring to FIG. 4C, once counter 473 is loaded, it will increment on each system clock at 8 MHz until the necessary delay has expired. Then, at count 0, decoder 475 will output a low which switches 2:1 multiplexer 463 to the "A" inputs. These inputs complete a circulating loop of shift registers which is 4-bits wide and 14 clocks long. Thus, the B inputs to the multiplexer provided an initial value of (n-1), which is decremented every 14 clocks to keep the reply output inhibited for (n-1) replies following the railed reply. The railing flag is developed by picking off the 4-bit value of replies remaining to be railed, and ORing them in gate 477 so that only a value of 0 will produce a low. The pick-off point is 3 clocks into the recirculating loop of shift registers 484. The final four stages of 10-bit shift register 478 are applied to AND gates 479 through 482, one of which will be enabled by Railing Gate Width signal RGW3, 5, 7, or 9) to shift the railing gate center as a function of selected gate width. These four AND gates are ORed by gate 483 to form a high-active Railing Flag (RAIL-12) for quality evaluation logic 123, shown in more detail in FIG. 5. Quality evaluation logic 123 provides delay 550 for delaying signal RAIL-12 an additional 12 clocks to coincide with the current reply declaration on lead 128. Referring to FIG. 5, leads 321 containing signals QB1-QB16 (Quality Bit 1-16) shown in FIG. 3 is coupled to OR gate 510 over line 511 to the data input of shift register 512 which may consist of, for example, 33 stages. Shift register 512 is clocked at 8 MHz. Stage 1 is coupled to an input of AND gate 522. Stages 2-4 are coupled over leads 513-515 respectively to inputs of AND gate 530. Stage 5 is coupled to an input of AND gate 522. Stage 15 is coupled to lead 124 and carries signal CAR14. Stage 17 is coupled over lead 516 to an input of AND gate 546. Stage 29 is coupled to an input of AND gate 523 and over lead 517 to an input of AND gate 127. Stage 30-31 is coupled over leads 518-520 to respective inputs of AND gate 532. Stage 33 is coupled over lead 521 to an input of AND gate 523 having an output coupled over lead 525 to an input of OR gate 527 having an output coupled over lead 529 to an input of AND gate 532. Control signal 5WIDE from setup latch 145 is coupled over lead 536 to an input of OR gate 526 and 527. The output of AND gate 522 is coupled to a second input of OR gate 526 having an output coupled over lead 528 to an input of AND gate 530. The output of AND gate 530 is coupled over lead 531 to an input of AND gate 534 having an output CLN (CLEAN) coupled over lead 535 to an input of 12-stage delay 537 and an input of OR gate 544. Signal NO QUALITY REQUIRED from setup latch 145 is coupled over lead 143 to an input of OR gate 539 and an input of OR gate 544. The output of delay 537 is coupled over lead 125 to an input of OR gate 539 and to target status word section 138 with signal CLEAN. The output of OR gate 539 is coupled over lead 540 to an input of AND gate 127. Signal ENRAIL (Enable Rail) from set up latch 145 is coupled over lead 144 to an input of NAND gate 547 and NAND gate 549. The output of NAND gate 547 is coupled over lead 548 to an input of AND gate 546. The output of AND gate 546 is coupled over lead 142 to target start/stop logic 215 with signal M4RD-12. Signal RAIL-12 from railing detector and adder 117 is coupled over lead 122 to an input of NAND gate 547 and 12-stage delay 550. The output of delay 550 is coupled to an input of NAND gate 549 having an output coupled over lead 551 to an input of AND gate 127. The output of AND gate 127 is coupled over lead 128 to an input of target status word section 138 with signal M4RD (Mode 4 Reply Decoded). The output of delay 550 is coupled over lead 130 to target status word section 138 with signal RAIL FLAG. As shown in FIG. 3, 17 taps (2.125 microseconds) in advance of each density value tap 119 of the shift register 112, a tap 118 is provided for input to the quality evaluation logic 123. This advance look allows time for the quality evaluation process to be completed concurrently with the density value computation. Quality evaluation logic 123 functions to examine signal M4DR on lead 110 as it leaves shift register 112 on lead 118 to see if there are adjacent overlapping replies. Density value adder 120 functions to sum the replies on signal M4DR on lead 110 in shift register 112 in 15 of the non selected reply positions and specifically excluding the valid reply position to provide an indication of the number of replies in shift register 112 in the nonselected reply positions extending over 56 microseconds while the reply position extends over 4 microseconds. Referring to FIG. 5, quality evaluation logic 123 is shown. 16 quality bit input lines on leads 321 pass through OR gate 510 and form a common quality bit data stream 511 with data from the selected reply position only. The signals on lead 511 are shifted into 33-stage quality evaluation shift register 512. AND gates 530 and 532 form two windows where the center taps are separated by twice the 1.75 microsecond spacing of the 3-pulse reply transmitted by a transponder. AND gate 532 looks for the absence (i.e., lows) of leading (earlier) reply decodes while AND gate 530 looks for trailing (later) reply decodes. The first three stages of the quality evaluation shift register 512 provide 0.375 microsecond delay to the center of the trailing reply window. The stage 15 of shift register 512 is also forwarded to the railing adder as a carry-in which is 14 clocks (1.75 microseconds) in advance of the analysis reply output tap. As shown in FIG. 5 stage 15 is coupled over lead 124 with signal CAR14. If a reply appears in either of these two windows AND gate 534 output will be a logic low. When there are no replies in either the leading or the trailing windows, the outputs of both 530 and 532 will be HIGH, causing the CLEAN output of 534 to be HIGH. AND gate 534 will enter this high into a 12-stage digital delay 537 to delay the CLEAN bit until the reply under analysis has propagated 12 clocks to the reply tap 517. Then, the reply under analysis from tap 517, and the delayed CLEAN bit on lead 538 ORed in gate 539 with the NO QUALITY REQUIRED on lead 143, are ANDed together in gate 127 with the enabled Rail Flag 551 to generate M4RD (Mode 4 Reply Decoded) on lead 128. The enabled Railing Flag input on lead 551 to AND gate 127 will be high except when railing has been enabled (line 144) and detected (line 122). M4RD on lead 128 is one bit of the target status word coupled over bus 139 to be unloaded into reply FIFO memory 40. Referring to FIG. 5, when 5WIDE input signal on lead 536 is active, it enables two additional shift register taps of shift register 112 for each of the two reply pulse windows, so that they are opened to a 5-clock width. Wider windows are used with the alternate embodiment in direct connection of KIR cryptograph computer 25 (as shown in FIG. 11) because of the highly time jitter implicit in the alternate mode 4 decoding scheme. Whenever railing detection is enabled and railing has been detected and a reply is also present, AND gate 127 will be disabled. Rail-12 on lead 543 is delayed in 12-stage- digital delay 550 to disable AND gate 127 when the analysis reply is also present. Rail flag on lead 130 is included in the target status word 138 for the declared replies so that reply processor 50 is aware that additional railed replies are present in the vicinity of the current declared reply. Quality evaluation logic 123 also generates signal M4RD-12 (mode 4 New Hit) on lead 142 when a replied decode is present at the current analysis position stage 17 of register 512, and either the CLEAN bit is present or the no quality required signal on lead 143 is active, and railing is either not present or not enabled. Referring to FIG. 5, the logic elements involved in this function are OR gate 544, NAND gate 547, and AND gate 546. Digital delays 537 and 550 work together with OR gate 539, NAND gate 549 and AND gate 127 to provide signal M4RD output in time coincidence with the declared reply. The first reply in a series of railed replies will be passed to reply FIFO memory 40, but signal M4RD-12 on lead 142 will be inhibited for subsequent replies in the series of the replies. Signal M4RD-12 on lead 142 is stored as a miss in the new hit register of target start/stop logic 215. Then, subsequent railed replies will not be passed to target start/stop logic as signal M4RD-12 on lead 142. Therefore, there can be no new hit registered and no new target start; rather, a started target count will be decremented. Also, the signal NHONLY (New Hit Only Bit) 132, which is returned to Reply FIFO memory 40 as part of the status word, will be inhibited. Quality evaluation logic 123 checks whether the current analysis reply is clean (i.e., no closely spaced or overlapping replies). Since the 3-pulse decoded reply input on lead 110 shown in FIG. 1, is a single, narrow pulse which represents the 3-pulse decoded reply with pulse spacing of 1.75 microseconds, an overlapping condition is inferred by looking for 3-pulse decodes in register 512 that lead or trail the analysis position by 1.75 microseconds. Referring to FIG. 6, waveform 800 having pulses 801 through 804 is shown representative of pulses entering shift register 512 and propagating from left to right. In FIG. 6, the abscissa represents time and the ordinate represents a voltage. Pulse 801 represents the input to stage one of shift register 512. Pulse 802 represents the F2 position of an overlapping trailing reply at stage 31 of shift register 512. Pulse 803 represents the current analysis reply at stage 17 of shift register 512. Pulse 804 represents the F2 position of an overlapping leading reply at stage 31 of shift register 512. The leading edge of pulse occurring 802 is positioned 1.75 microseconds behind the leading edge of pulse 803. The leading edge of pulse 803 is positioned 1.75 microseconds behind the leading edge of pulse 804. Therefore pulse 802 is positioned 14 stages in shift register 512 behind pulse 803 which in turn is positioned 14 positions of shift register 512 behind pulse 804. Waveform 810 in FIG. 6 shows leading window 811 and trailing window 812 with reference line 814 showing the center of the leading window and reference line 816 showing the center of the trailing window. Windows 811 and 812 each have the width of three shift register stages. At times when signal 5 WIDE is present additional logic gates are enabled to provide windows 821 and 822 corresponding to the leading and trailing window wherein each window is five stages wide of shift register 512. Windows 811, 812, 821 and 822 show where a pulse occurring within the window will be detected to cause signal CLN on lead 535 to be low. To accommodate time jitter and pulse-spacing tolerance of the particular Reply Decoder 30 application, the leading and trailing reply look positions are blurred or ORed either by 3 or 5 adjacent taps of the shift register, as setup by the user to suit his application. Also, when No Quality Required signal is low on lead 143, only those replies which are clean (i.e., no reply present in either garble window) can be loaded into target status word section 138. Referring to FIG. 7, target status word section 138 is shown in more detail. Signal NO QUALITY REQUIRED is coupled over lead 143 from setup latch 145 to an input of OR gate 539 having an output coupled over lead 540 to an input of AND gate 127. Quality evaluation logic 123 provides signal CLEAN over lead 125, 538 to an input of OR gate 539 and to an input of status latches 568. Quality evaluation logic 123 provides signal reply position over lead 517 to an input of AND gate 127. Quality evaluation logic 123 provides an output signal Rail Flag over lead 130 to an input of NAND gate 549 and an input of status latches 568. Signal ENRAIL is coupled over lead 144 to an input of NAND gate 549 having an output coupled over lead 551 to an input of AND gate 127 having an output, signal M4RD coupled over lead 128 to an input of status latches 568. Signal ENM4AR (Enable Mode 4 Actual Range) is coupled from setup latch 145 over lead 560 to an input of OR gate 561. Signal NHONLY (New Hit Only) is coupled over lead 132 to an input of status latches 568. Signal AZ OFFSET/0-3 is coupled over lead 137 to an input of AZ offset register 135 having an output coupled over lead 136 to an input of status latches 568. Signal target start is coupled over lead 133 to an input of OR gate 561 and to an input of status latches 568. Status latches 568 has respective outputs 569-573 coupled to respective output buffers 574, 576, 578, 580, 589, and 582 having respective outputs 575, 577, 579, 581, 590, and 583. Signal range gate is coupled over lead 563 to an input of NAND gate 564 having an output coupled over lead 565 to an input of latch 566. The output of OR gate 561 is coupled over lead 562 to an input of NAND gate 564. The output of status latch 566 is coupled over lead 567 to the load input of output buffers 574, 576, 587, 580, 589, 582, 584, 586, and 592. Signal rollover fault is coupled over lead 134 to an input of status latch 590 having an output over lead 591 to an input of output buffer 592. Output buffer 592 has an inverted output on lead 593 with signal rollover fault which is coupled to reply FIFO memory 40 via data bus 139. Output buffer 586 provides signal UNLOADB which is coupled over lead 587 to FIFO memories 40, 42, and 44. Output buffer 584 has an inverting output on lead 585 which is coupled to reply FIFO memory 40 which may be duplicated to provide additional bits of signals having a plurality of bits to reply FIFO memory 40. Signal CLRB from interface board 33, shown in FIG. 1, is coupled over lead 37 to the CLEAR input of status latches 568 and to the PR input of status latch 566. In operation of status word section 138 shown in FIG. 7, status word section 138 provides at its output a 16-bit status word to reply FIFO memory 40 when output buffers 574, 576, 578, 580, 582, 584, and 586 are gated on by signal UNLOAD on lead 567. Signal UNLOAD on lead 567 will be generated for any target within the range gate indicated by signal range gate on lead 563, provided that target start flag 133 is set to a logic "1". These two conditions are prerequisite to declaring any reply by reply decoder 30 and unloading it to FIFO memory 40. Three types of replies can be declared by reply decoder 30 and passed to reply FIFO memory 40, as determined from inputs or replies to reply decoder 30 and by setup inputs of reinforced replies, strobed replies, and actual-range target replies. Reinforced replies occur whenever a new hit is present within target start gate width (window). Strobed replies are at the range of the target start flag, and occur when no new hit is present for a previously started target within the target start flag gate width (i.e., target start flag 133 set). Strobed replies are identified by M4RD 579 and HNONLY 581 bits being false. Actual range target replies are enabled by ENM4AR 560 and occur when there is a new hit within the target start flag gate width, but they occur at the actual range of the new hit. If the new hit is in the same range cell as the target start flag, only one reply will be output; but if the new hit is within the target start window but not in the same range cell as target start flag, replies will be output both at the target start flag range cell and at target actual range. Reply status word output format and content is shown in Table 2.
TABLE 2
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Mnemonic Status
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DV0-DV3 Density Value computation for the
current Target Start; a 4-bit number
from 0 to 15 which indicates the number
of replies received at the 15 incorrect
positions for a given target range.
RO Rollover Fault (of range counger 633)
will be true if the range counter has
reached terminal count and is then
inhibited at approximately 640 nautical
miles.
Rail Flag Rail Flag is true where railing has been
detected which trails the current reply.
Clean Clean quality bit for Mode 4 decoded
replies.
NHONLY Indicates a reply within the range gate
window width (which is centered about
the range of the Target Start flag).
(Will always be true when M4RD is true,
because M4RD requires the current reply
to be within the same range cell as
Target Start Flag.)
Start Flag Target Start Flag in current range cell.
M4RD Actual-target/strobe flag. (Refer to
Table 8-1 for logic of this status bit.)
AZ0F0-3 Azimuth Offset. This value is the
in stored n/CM-1 value between first hit
and Target Start.
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FIG. 8 shows the logic circuitry for range counter and reply totalizer 212. Signal M4ZR is coupled over lead 146 to an input of AND gate 610 having an output coupled over lead 611 to an input of OR gate 614. Signal CKSW is coupled over lead 29 to an input of AND gate 610 and to the inverted input of AND gate 612. Signal SIFZR is coupled over lead 36 to an input of AND gate 612. The output of AND gate 612 is coupled over lead 613 to an input of OR gate 614 having an output coupled to the input of AND gates 616 and 624 and to the data input of latch 645. Signal POPEN is coupled over lead 224 to the inverted input of AND gate 616 and to AND gate 618. The output of AND gate 616 is coupled over lead 617 with signal range normal start to an input of OR gate 620 having an output over lead 225 with signal RAM START. Signal target range start on lead 642 is coupled to an input of AND gate 618 having an output coupled over lead 619 to an input of OR gate 620 and an input of inverter 621 having an output on lead 622 with signal R/WCLRB. Signal M4RD-12 is coupled over lead 142 to an input of AND gate 652. Signal SIF NEW HIT is coupled over lead 48 to an input of AND gate 654. Signal CKSW is coupled over lead 29 to an input of AND gate 652 and the inverted input of AND gate 654. The output of AND gate 652 is coupled to an input of OR gate 653. The output of AND gate 654 is coupled to an input of OR gate 653 having an output on lead 655 with signal NEW HIT which is coupled to an input of AND gate 625. The output of AND gate 625 is coupled over lead 628 to an input of counter 630. An 8 MHz clock is coupled over lead 35 to the clock input of counter 630. Signal NHCNTCLR from setup demux and latch 210 is coupled over lead 623 to an input of NAND gate 624. Signal CLRB is coupled over lead 37 to an input of NOR gate 627. The output of NAND gate 624 is coupled over lead 626 to the input of NOR gate 627 having an output coupled over lead 629 to an input of counter 630. Signal range gate is coupled over lead 563 to the inverter input of AND gate 625. The output of counter 630 is coupled over lead 631 to the A input of 2:1 multiplexer 635. The output of multiplexer 635 is coupled over lead 636 to an input of 16-bit latch 637 which has an output on lead 213 to range FIFO memory 42. Signal range counter preset from setup demux and latch 210 is coupled over lead 632 to the preset input of counter 633. An 8.276 MHz clock is coupled over lead 35 to an input of flip-flop 645, flip-flop 647 and counter 633. The output of flip-flop 645 is coupled over lead 646 to the J input of flip-flop 647 and to the load input of counter 633. Counter 633 has an output coupled over lead 649 to the K input of flip-flop 647. The complement output of flip-flop 647 rollover fault is provided on lead 134. The output of counter 633 is also coupled over lead 634 to the A input of start comparator 638 and the A input of stop comparator 639 as well as the B input of multiplexer 635. Signal target start setup value is coupled over lead 640 to the B input of start comparator 638. Signal target stop set up value is coupled over lead 641 to the B input of stop comparator 639. Start comparator 638 provides an output on lead 642 at times A=B with signal target range start which is coupled to the J input of flip-flop 644. Stop comparator provides signal target range stop at times A=B on lead 643 to the K input of flip-flop 644. The output of flip-flop 644 is signal range gate on lead 563 which is coupled to the control input of multiplexer 635 and the inverted input of AND gate 625. Multiplexer 635 selects A at times the signal on its control input is low and selects B at times the signal on its control input is high. Referring to FIG. 8, the range counter and reply totalizer section 212 includes a 16-bit range counter 633, magnitude comparators 638 and 639 for target start and stop, a 16-bit reply totalizer counter 630, 2:1 multiplexer 635 to select either range count or reply total for output, output latch 637, and range counter control logic. The 16-bit range counter 633 is cleared and preset at the beginning of each new interrogation sweep in response to M4ZR on lead 146 in Mode 4, or by SIFZR on lead 36 in ATCRBS/SIF modes. Selection is controlled by Clock Switch (CKSW) 29 and AND gates 610 and 612. At range zero, the next following 8/8.276 MHz clock sets flip-flop 645 so that the second clock will enter a preset value (632), equal to one-half of range cell width, into the four LSBs of range counter 633. Flip-flop 647 is clocked on at the same time, to enable range counter 633 on the third clock following range zero. The range counter 633 is clocked at 8.276 MHz for all modes and configurations so that range data input to Reply Processor 50 will be consistently scaled. Because Mode 4 reply declarations are made at the 8 MHz rate, a .+-.30 nanosecond ambiguity is unavoidably introduced, which translates to a range accuracy of .+-.0.0024 nm. Maximum range accommodated by the range counter is 640.5 nm. Maximum range resolution is, of course, the full 16 bits for a range cell width of 121 nanoseconds (where LSB is 1 clk); but only the number of bits, beginning with the MSB, required for a given application will be used. Range cell width and range counter preset 632 value are required to offset range cell center from range counter zero time. This preset value is the 4-bit range resolution value which is user programmed as bits 6 through 9 of setup demux and latch 210 with word No. 1. Range resolution values are provided in Table 3.
TABLE 3
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Range Cell Cell Range
Counter Width Width Counter Delay
Bits Used in nanosec
in nm Preset Value
in nm.
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16 (R1-R16)
121 .01 0 0
15 (R2-R16)
242 .02 1 .01
14 (R3-R16)
483 .04 2 .02
13 (R4-R16)
967 .08 4 .04
12 (R5-R16)
1933 .16 8 .08
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Referring further to FIG. 8, it will be seen that 2:1 multiplexer 635 selects range counter output when Range Gate 563 is active (high) for output to Range FIFO 42. When Range Gate 563 is low, 2:1 multiplexer 635 selects the 16-bit output of reply totalizer 630, which is enabled to increment each time a reply is decoded (either Mode 4 or ATCRBS/SIF). Cumulative reply count can be kept on an interrogation sweep basis, in which case NHCNTCLR setup bit 623 will be high. Then, each RANGE0 will clear the counter; but if NHCNTCLR is held low, count will accumulate until the next RANGE0 after NHCNTCLR is allowed to return high. TRRG (data word No. 2, bit 15) when set, selects counting of only those targets which are in the range gate; when TRRG is clear, all targets are counted. The target start comparator 638 and target stop comparator 639 are identical 16-bit circuits which compare user-selected range gate data against the running range count to generate Target Range Start 642 and Target Range Stop 643 signals, respectively. These outputs of the range counter section are applied to clocked latch 644 which generates Range Gate 563. When range count becomes equal to the stop value, Range Gate 563 returns low. Range counter 633 is adequate for 640 nautical miles of range, so that rollover should never occur; but if rollover does occur, JK flip-flop 647 will be clocked off to inhibit range counter 633 and to output Roll over Fault (ROFLT) signal 134 to target status word section 138. Referring to FIG. 9, the logic circuitry of RAM address section 217 is shown in more detail. Signal RAM start is coupled over lead 225 to an input of load logic 664 having a first output coupled over lead 665 to the load input of read address counter 661 and a second output coupled over lead 666 to the enable input of read address counter 661 and to an input of AND gate 668 and to an input NOR gate 677. An 8 MHz clock is coupled over lead 35 to the clock input of load logic 664. Setup data on lead 45 which may be, for example, 8 bits, is received from setup FIFO memory 444 and coupled to the data input of read address counter 661. Read address counter 661 has an output to provide the read address which is coupled over lead 662 to the A input of 2:1 multiplexer 810, to the A input of adder 670 and to the R/W logic 676. Signal LSB from read address counter 661 is coupled over lead 663 to an input of AND gate 668 and to an input of R/W logic 676. Signal R/W offset which contains four least significant bits, is coupled over lead 667 to the 4LSB inputs of input B of adder 670. If B input is able to accommodate 16 bits then the 12 higher bits are tied high by way of lead 669. Referring to FIG. 9, the sum output of adder 670 is coupled over right address bus 671 to the B input of multiplexer 810. The output of multiplexer 810 is coupled over lead 688 to an input of 16 bit latch 689 having an output over lead 218 with signal address to random access memory 34 which may be for example 128 words by 12 bits. The output of AND gate 668 is coupled over leads 672 through delay 673 which may for example 60 nanoseconds to lead 216 with signal data latch. Signal M4ZR is coupled over lead 146 to an input of NOR gate 674. Signal SIFZR is coupled over lead 36 to an input of NOR gate 674 having an output coupled over lead 675 to an input of NOR gate 677. Signal CLRB is coupled over lead 37 to an input of NOR gate 677 having an output coupled over lead 678 to the input of AND gate 681 and an input of delay 673 and 679. Delay 679 may be for example a 31 nanosecond delay. The output of delay 679 is coupled over lead 680 to a second input of AND gate 681 having an output on lead 682 with signal GATE coupled to the control input of bidirectional bus driver 686. Signal R/W CLRB is coupled over lead 622 to an input of R/W logic 676. An output of R/W logic 676 is coupled over lead 684 with signal R/WB to a control input of RAM 34. A second output of R/W logic 676 is coupled over lead 690 with signal CS to an input of RAM 34. A third output of R/W logic 676 is coupled over lead 683 with signal SELE which is a logic 1 for writing is coupled to bidirectional bus drivers 686. Data from RAM 34 is coupled over bidirectional bus 219 through bus drivers 686 to bidirectional data bus 687. Referring now to FIG. 9, RAM address section 217 generates read and write addresses for target RAM 34, and control signals for RAM and internal operation. Read address counter 661 functions independently of, but in parallel with, range counter 633 and is clocked at 8 MHz in Mode 4 and 8.276 MHz in ATCRBS/SIF. Actually, counter 661 is a 17-bit counter; the LSB is used only to generate the Data Latch (DL) 216 which latches data read from RAM 34 into target start/stop logic 215. The NLSB toggles at a 2/2.069 MHz rate, allowing sufficient time for read and write operations for each read address count. The counter is loaded with all zeros (except during test) by RAM start 225. In popup mode, RAM start will go high with Range Gate 563, so that a smaller RAM can be used for popup. If the popup RAM were the same size as recommended for normal operation however, (32k range cells for 640 nm application), then SIF 2-of-n and Mode-4 2-of-n data can be stored without interaction by using the popup bit to select Mode 4 or ATCRBS/SIF. In popup mode, the range GATE is started at a range determined by setup data input, and this range must be consistent for each subsequent interrogation to enable consistent access to stored data. Referring further to FIG. 9, 16-bit full adder 670 adds the 2's complement value (669) of a programmed setup read/write differential to the read count, so that write address on bus 671 tracks read address on lead 662 but lags by the programmed amount to allow processing time for hit correlation. Writing is inhibited by R/W logic 676 until the read address count increments to 2. R/W logic 676 also generates R/WB on lead 684 to read RAM data when high, and to write into RAM when low. Similarly, SELE signal 683 controls direction of the bidirectional bus drivers 686. These drivers are inhibited by Gate 682 for 31 nanoseconds each time direction is changed. Another 60 nanosecond delay is provided by digital delay 673 before generating Data latch on lead 216 which latches RAM readout data into the target start/stop logic 215. SELE signal on lead 683 also operates 2:1 multiplexer 672 to select read address on lead 662 or write address on lead 671. Referring further to FIG. 9, read address counter 661 is clocked by 8/8.276 MHz, but the LSB is not used, so Read and Write addresses increment at a 4/4.138 MHz rate. Read address leads the current write address by 4, so that eight 8-MHz clock periods are allowed in which data processing is performed. The 128k byte RAM 34 is organized into four sections of 32k each. One normal or one popup section can be written into while the other RAM section can be read back. Each RAM section provides 12-bit storage at each of the 32k range cells, each of which represents one count of range counter 212. When a reply is decoded, the count window that has been specified for 2-of-n start is entered into the 3 LSBs; thus, if a 2-of-8 criteria has been established for verifying a target, then a 7 will be loaded at the time of the initial hit to indicate the count remaining for the target verification window. This stored count will be decremented one count for each successive sweep. Referring now to FIG. 10A, start/stop logic section 215 is used both in Mode 4 and in ATCRBS/SIF operation. In Mode 4 operation, start/stop logic is essential; but also, in ATCRBS/SIF modes, when reply rates and FRUIT are unusually high, it is used to perform hardware defruiting in Reply Decoder 30 and thereby avoid overburdening the Reply Processor 50. Start criteria are determined by inputs to setup demultiplexer and latch 210. In 2-of-n operation, n=hexadecimal value input as bits 11 through 14 of setup word No. 2. Also selectable is 1-of-1 operation, where a single-hit will initiate a Target Start. Stop criteria also are determined by setup inputs, including six bits which preset the nonconsecutive miss (NCM) count, and four bits which preset (at target start time) the consecutive miss (CM) count. Three additional bits determine whether both counts--or which one--is required to disqualify a target and thereby force the range cell data to all zeros. Referring further to FIG. 10A, data register subsection 713, includes three shift registers 715, 720 and 726 which store target starts, CM count, and NCM count. All three registers 715, 720 and 726 are 7 clocks deep so that data propagating in the priority logic subsection 776 shown in FIG. 10A have reached the register centertaps and will output the A, B, and C control signals at the same time that the related data is exiting the data register subsection. Target start register 715 is 1-bit wide. The n/CM register 720 is 4-bits wide to accommodate the maximum CM count of 15. The NCM counter 726 is 7 bits wide to accommodate the maximum NCM count of 128. Referring again to FIG. 10A, two similar select logic subsections, identified as Select logic 738 and select 1 logic 733, are shown. These 4:1 data multiplexer sections operate under control of the priority subsection 776 shown in FIG. 10B control signals A on lead 764, B on lead 765, and C on lead 766 to perform switching and 2's complement subtractions to process n/CM and NCM counts in bit-parallel, byte-serial fashion. Output data from these two subsections is latched in 3-state latches 737 and 745, and output is enabled by SELE 683 which toggles the read and write operations. Select subsection 738 is a 7-bit wide switch which selects either: all 1s, NCM setup value, stored NCM count, stored NCM count-1, or, when Strobe 767 goes high for Target Stop, all 0s will be selected. The "select 1" subsection 733 is a 4-bit wide switch which selects either: n setup value, CM setup value, stored n/CM count-1, or, when Strobe 767 goes high for Target Stop, all zeros will be selected. Both subsections 733 and 738 are inhibited when control signal C is high, or when CM or NCM mode control signals are high. NCM count either can be decremented when a miss occurs, or rewritten into RAM without change when a hit occurs. CM count will either be decremented when a miss occurs, or reset to the programmed value when a hit occurs. When the n/CM portion of RAM is used to store n start criteria for non-started targets during 2-of-n start, select logic will either: decrement the stored value of n when a new hit is not received following a previous first hit; or, when a new hit reinforces a previous first hit, write target stop criteria into RAM 34. Referring to FIG. 10B, priority subsection 776 receives new hits and propagates them in a 13-stage, 1-bit wide shift register 777. Eleven taps on this register are monitored by window logic 779 to which gate width 760 and start mode 794 control lines are also applied. Similarly, 10-stage stored-hit register 782 has +/-3 taps about the centertap. Window and control logic subsection 779 consists entirely of decoder gates on the window taps of the new hit and stored registers 777 and 782, respectively. Together, these signals determine which logic operation will be performed during each system clock period; they appear at subsection output in time coincidence with the related target data exiting the data register subsection 713. Reply range gate width, determined by setup inputs, may be 5, 7, 9, or 11 clocks wide. Reply range gate width qualifies target start and also subsequent new hits: i.e., they must fall within the gate to be valid. Narrow range gate width is desirable for optimal range resolution in ATCRBS/SIF applications where reply time jitter is minimal; typically, a 5-clock-wide gate is used. In Mode 4 applications however, and especially where either the Interrogator Processor 25 performs the 3-pulse reply decoding, and/or the KIR cryptograph computer is not directly connected to the Reply Decoder 30, reply time jitter can be as much as .+-.0.5 microseconds. In such applications, wider range gate width is necessary to avoid exclusion of valid replies, as range gate width establishes the "look" window for subsequent replies. Referring further to FIG. 10B, the number of new hit register 777 taps 778 and stored hit register 782 taps 765 actually in use is determined by the currently established gate width, as tabulated in Table 4 for range correlation of new and stored hits table.
TABLE 4
______________________________________
Gate Width New Hit Taps Used
Stored Hit Taps Used
______________________________________
5 +/- 2 +/- 1
7 +/- 3 +/- 2
9 +/- 4 +/- 2
11 +/- 5 +/- 3
______________________________________
Referring further to FIG. 10B, priority logic 776 compares new hit and stored hit data present in these two windows to configure target start/stop logic 21 for performing the needed operation. Priority logic thus determines whether each of two stored counts will be decremented, rewritten into RAM 34, or reset to zero. Setup data to Start Mode input 794 will determine whether start criteria is 1-of-1 mode (where the target start flag will be set true with a first hit), or 2-of-n mode where the programmed n-1 value will be stored in lieu of the CM count until target start; then, on the next interrogation sweep, any new hit that passes through the window will cause a target start. Target start range will be at the mean position of the stored hit and the new hit. When 2-of-n start has been programmed, the programmed value of n-1 (4 bits) will be written into RAM 34 by the first hit to indicate the number of hits remaining within which to find a second hit. Then, each subsequent interrogation will decrement this count until at zero count, if not reinforced by another new hit, the first hit window will be discarded. Conversely, a reinforcing new hit within the first hit window will set the Target Start flag, then CM stop criteria will be loaded into these four bits of RAM. The target start then establishes a gate window which is equal in width to the reply range gate width. No other target start can begin in the established window, but each new hit that passes through the window will reinforce the existing target start flag, which is bit RD01 in RAM. Once a target start occurs, it will remain in the same range cell until stop criteria have been met. Range position in this application is not averaged between target start and each successive new hit. Although such an averaging scheme could be used to appropriately move the target's location by means of a different set of logic in the Priority Subsection 776. Referring again to FIG. 10B, priority logic subsection 776 uses signals derived by these register taps to generate logic control signals A on lead 764, B on lead 765, and C on lead 766. These control signals determine which logic operation will be performed on the stored data by the select logic subsections 733 and 738, FIG. 10A to select one of four possible operations. The C output 766 indicates that all zeros are to be stored. In order to cover all situations that require an output of all zeros, C output is logically ORed with outputs of decoders 768 and 769 to detect the all-zeros condition following some nonzero value. This operation allows zero to be a stored number before it is acted upon, so that up to 16 loops can occur for a 4-bit binary number. The tables below show logic operations performed for n hits vs consecutive miss count, nonconsecutive miss count, and target start flag. 2-of-n Start (n)/Consecutive Miss (CM) Count is shown in Table 5, and Nonconsecutive Miss (NCM) Count is shown in Table 6.
TABLE 5
______________________________________
Control signals:
C B A Logic Operation
______________________________________
0 0 0 First hit; write n start criteria.
Value = n-1.
0 0 1 New start; write CM stop criteria.
Value = CM-1.
0 1 0 Old start, new hit; write CM stop
criteria. Value = CM-1.
0 1 1 No new hit; write current stored
value -1.
1 x x Write all zeros.
______________________________________
Target Start (TS) Flag Table is shown in Table 7.
TABLE 7
______________________________________
Control Signals:
C B A Logic Operation
______________________________________
0 0 0 First hit; output TS = 0
0 0 1 New start; TS = 1.
0 1 0 Old start, new hit; TS = 1.
0 1 1 No new hit; write current value
of TS.
1 x x Write all zeros.
______________________________________
Each new bit must be compared against the reply range window established by previously stored first hits and Target Starts (TS) to determine which one of the following conditions exists: a. New hit is a first hit, which meets target start criteria in 1-of-1 mode only. b. New hit is a second or subsequent hit, which meets target start criteria in 2-of-n mode per setup value of n. c. No new hit but previous first hit: decrement n count. d. No new hit but previous target start: decrement NCM and CM. Logic implemented in the priority subsection obeys the following rules: a. In 2-of-n mode, new hits only combine with previous first hits within the specified range gate width to initiate a new target start. b. In 1-of-1 mode, a new hit will initiate a new target start if there had been no previous first hit. c. A new start will be placed at the average position of the new hit and the previous first hit--unless that placement should place it in the range gate window of another target start, in which case only a first hit flag will be set for the new hit's range cell. d. New start average positions are weighted toward the new hit if position is not an exact cell location. e. New hits also store to the present range cell location as a first hit if there is not a target start in the cell, even if the new kit has also combined with a previous first hit to generate a new target start. f. Once stored as a first hit, new hits for unstarted targets stay in the same cell. g. New hits and previous target starts associate without restriction to permit the ne hit to validate the previous target starts. h. Once started, target starts stay in the same cell. New hits do not occur in adjacent cells--due to present implementation of the present video quantizer and Leading Edge Detector 28, which does not generate leading edges with less than two-clock separation. FIG. 10B also shows azimuth offset section 220, where the difference between (n) setup value and current (n) stored value is determined by 2's complement subtraction in adder 787. This value represents the number of interrogations between first hit and target start. Actual azimuth data bytes are passed to the associated FIFO via interface circuitry 33. Azimuth offset section 220 could also be used to read out the number of interrogations between any two reinforcing hits. The 4-bit difference 788 is latched in 789 and delayed four clocks in azimuth offset register 135 (in DV chip) before being latched with the remaining bits of the target status word as shown in FIG. 7. One of the features of the present invention is that many parameters of reply decoder 30 are user-programmable. Although this user-programmable feature is not new in principle, it is described here to facilitate comprehension of Reply Decoder operation. The particular features implemented greatly expand the functionality and operation of the invention. Referring to FIG. 1, it will be seen that setup demultiplexer and latch 210 receives 16-bit data words from the Reply Processor 50, via setup FIFO memory 44, and stores the user-selectable parameters conveyed by these words. A FIFO memory is not mandatory: other means could be used to queue and input setup data. The format of presently used setup words is tabulated below. There are no setup default values: all used bits must be initialized on power-up; however, data to be changed can be written into the addressed register over existing data; so, only data requiring change need be reentered for each new setup. Data storage registers for the setup words are addressed by two select line inputs, and are written into by a data strobe from setup FIFO memory. Setup demux and latch 210 includes two sets of registers for target start and stop ranges. Other data for popup operation (i.e., n, CM, NCM, gate width, mode select, and power-up bit) use the same register which are used for normal operation. Setup Data Word No. 1 on lead 45 and Format is shown in Table 8.
TABLE 8
______________________________________
Bit Mnemonic Function
______________________________________
0-2 STOPMODE Determines whether a zero
value of NCM count, CM count,
or both will disqualify a
target and force the output to
all 0s. The octal codes are:
100 = both NCM and CM
010 = only NCM
001 - only CM
3-5 Gate Width Determines gate width in
clocks, where CW1,2,3 are:
000 = 5 clocks (center +/-2)
100 = 7 clocks (center +/-3)
110 = 9 clocks (center +/-4)
111 = 11 clocks (center +/-5)
6-9 Range Determines range counter
Resolution offset delay for range
resolution setup as follows:
0000 = 8.276 MHz, 121 nsec
0001 = 4.14 MHz, 242 nsec
0010 = 2.07 MHz, 483 nsec
0100 = 1.04 MHz, 967 nsec
1000 = 0.517 MHz, 1933 nsec
10 NHCNTCLR When set, this pin allows
range zero to clear the total
reply counter so that total
reply count is per
interrogation sweep.
Otherwise, the counter is not
cleared but continues to count
continuously with a rollover
at count 65536, so total reply
count is cumulative.
11 (Not used.)
12 MODE When clear (0), selects 2-of-n
start mode; when set (1),
selects 1-of-1 start mode.
13 SOR4 When low, forces SIFEN low to
enable software defruiting of
ATCRBS/SIF replies. When
high, enables hardware
defruiting of ATCRBS/SIF
replies.
14 POPUP When set (logic 1), next
interrogation will be a popup
15 POWERUP Used for power-up or mode
change. When clear (logic 0),
data propagated out of RAM is
discarded in first stages of
n/CM, NCM, and TS registers,
thereby effectively clearing
the previously stored register
information.
______________________________________
Setup, Data Word No. 2 Format on lead 45 is shown in Table 9.
TABLE 9
______________________________________
Bit Mnemonic Function
______________________________________
0-6 NCM Sets initial NCM count. Value
to be entered is NCM-1.
7-10 CM Sets initial CM count. Value
to be entered is CM-1.
11-14 N Sets value of n for 2-of-n
target starts. Value to be
entered in n-1.
15 TRRG When set (1), total reply
counter will count only
replies in the range gate;
when clear (0), all replies
are counted.
______________________________________
Set up, Data Word No. 3 on lead 45 and Format is shown in Table 10.
TABLE 10
______________________________________
Bit Mnemonic Function
______________________________________
0-15 Target Range value for target start
Start Range range gate, normal or popup
target. LSB = .01 nmile
______________________________________
Setup, Data Word No. 4 on lead 45 and Format is shown in Table 11.
TABLE 11
______________________________________
Bit Mnemonic Function
______________________________________
0-15 Target Range value for target stop
Stop Range range gate, normal or popup
target. LSB = .01 nmile
______________________________________
Referring again to FIG. 1, it will be seen that, in addition to the above setup inputs from setup FIFO memory 44, other setup parameters are input to setup latch 145. Presently, one 16-bit word is used as shown in the table below. This setup word is latched by the Data Load Strobe (DSTB) input. In addition to this word, there are seven "hardwired" static setup inputs, including the NDIRCT configuration control and a 6-bit Range Counter Delay Preset. Setup Word Format is shown in Table 12.
TABLE 12
______________________________________
Bit Mnemonic Function
______________________________________
0-3 RDSC0-3 Railing Decode Select
Criteria. A 4-bit code which
specifies the number of
possible reply positions which
are to be analyzed by the
railing detection logic. Two
decoding criteria are
selectable: N replies of N
possible positions (when RDSC3
= 1); or, N-2 replies out of N
possible positions (when RDSC3
= 0). Values are as follows:
______________________________________
RDSC3 RDSC2 RDSC1 RDSC0 Criteria
______________________________________
0 1 1 1 2 of 4
0 1 1 0 3 of 5
0 1 0 1 4 of 6
0 1 0 0 5 of 7
0 0 1 1 6 of 8
0 0 1 0 7 of 9
0 0 0 1 8 of 10
0 0 0 0 Not used.
1 1 1 1 4 of 4
1 1 1 0 5 of 5
1 1 0 1 6 of 6
1 1 0 0 7 of 7
1 0 1 1 8 of 8
1 0 1 0 9 of 9
1 0 0 1 10 of 10
1 0 0 0 Not used.
______________________________________
Bit Mnemonic Function
______________________________________
4-5 RGW0 & 1 Railing Gate Width. A 2-bit
code selects gate width for
railing logic to be 3, 5, 7,
or 9 clocks wide as follows.
(Railing gates are centered at
1.75 microsecond intervals.)
______________________________________
RGW1 RGW0 Gate Width (in Clocks)
______________________________________
1 1 3
1 0 5
0 1 7
0 0 9
______________________________________
Bit Mnemonic Function
______________________________________
6-8 DVGW0 - 2 Density Value Gate Width.
A 3-bit code selects gate
width for the density value
computation to be, 5, 7, 9, or
11 CLKs wide as follows:
______________________________________
DVGW2 DVGW1 DVGW0 Gate Width (CLKs)
______________________________________
1 1 1 5
1 1 0 7
1 0 0 9
0 0 0 11
______________________________________
Bit Mnemonic Function
______________________________________
9 5EN Enable 5-wide gate. When
input to DV chip is true (L),
5-wide gate is used for
3-pulse decoder logic. When
input is false (H), the
standard 3-mode gate is used.
10 RAILEN When input to DV chip is true
(H), railing detector output
is enabled to inhibit output.
______________________________________
Referring now to FIG. 11, a first alternate embodiment of the invention is shown where the KIR Cryptographic Computer 25 is connected to the Interrogator 10 and thus indirectly to the reply decoder 30 of this invention, rather than connected directly to the reply decoder 30 as shown in FIG. 1. This system configuration is the conventional one used with previous Reply Decoders. The INDRCT configuration control input 49, to which a logic high is applied, is effectively passed through retiming logic 114 as the FOUND signal 115, and also enables a stationary DV window about reply position 8. GTC and TDV inputs are not used. In the KIR indirect connection of FIG. 11 the sequence of system operation is as follows: a. The effect of having a fixed evaluation window at reply position 8 is to add 32 microseconds to the KIT+KIR delay time, plus the 18.75 microsecond delay incurred in shift register 112. This pre-enables fixed windows at the center reply position for railing and QB taps, while enabling the eighth DV tap as being the assumed correct position. b. Mode 4 Pretrigger (M4PT) 24 is output to KIR Crypto Encoder 27 by Interface Board 33 to initiate Interrogation sweep start. c. Crypto Encoder 27 sends KIRCV 23 to Interrogator Transmitter 16, and KIRGTC 22 to Interrogator Receiver 19. d. In indirect configuration, INDIRECT 49 (control input) will be logic-high to disable the 3-pulse decode circuit in LED. Three-pulse Decoded Replies M43PD on lead 199 from Interrogator Receiver 19 are applied to KIR Crytpo Delay 26, which imposes the correct delay and outputs Time Decoded Video (KIRTDV) on lead 21 to the associated Quantizer and Leading Edge Detector 28. e. Video Quantizer (part of 28, FIG. 11) passes the 3-pulse decoded reply onto the composite video input of LED 28 (part of 28, FIG. 11) which outputs a single leading-edge detected pulse on the M4DR on lead 110. Reply decoding then proceeds as previously described, but without the floating evaluation window as provided in FIGS. 1 and 3. A second alternate embodiment would differ from the preferred embodiment only in that two Synchronizer chips 32 and 32' of the same type and with the same function as 32 shown in FIG. 11 would be used. The second Synchronizer chip 32' is designed with a separate configuration input Odd-or-Even (ODE) 49 which makes this possible. The two Synchronizer chips 32 and 32' operate with the external RAM 34 in a time-sharing scheme. This permits a 2:1 improvement in Range resolution since targets can be detected and stored each 1/8 microsecond rather than each 1/4 microsecond as with a single synchronizer chip 32. Read address counter 661 is enabled on an 8 MHz clock phase determined by the State of ODE input. For 2-chip operation, the two chips are alternately enabled: SELE control lines (683, FIG. 9) for the two chips are 180 degrees out-of-phase for mutually exclusive odd/even operation. Chip No. 1 is considered to be the "even" chip (ODE=L), and starts incrementing at M4ZR 146 for Mode 4 or SIFZR 36 for ATCRBS/SIF modes. The "odd" chip (ODE=H) is enabled one clock after the even chip. In this manner, the quiescent space of one chip is interleaved with the active period of the other.
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