Cycle stealing I/O controller with programmable offline mode of operation

Abstract

A dual mode microprocessor acts either as a front-end IO controller processor relative to a primary host processor and device or as a secondary data processor having independent storage, processing and IO capabilities. Host software prepares a list of device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor so as to evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, performing this transfer in an autonomous manner, i.e., without assistance from either processor. In PO mode the microprocessor directs associated elements to perform one or more programs of operations defined by secondary commands contained in a command list which is transferred to the microprocessor's memory by special PO mode "LOAD" type DCB's, and interpreted in response to special PO mode type "START" DCB's. A list transferred by one LOAD DCB may be repeatedly accessed at various positions by several START DCB's. The architecture of the command list includes commands which permit the microprocessor to exchange data with the host and/or a device, perform arithmetic operations on data, perform bit and byte manipulative operations on data, and directly control the device interface.

Claims

It is claimed:

1. In a data processing system containing a primary processing subsystem, a peripheral device and a secondary processing subsystem interfacing between said primary subsystem and device, an improved secondary subsystem comprising:

means for storing primary commands received from said primary subsystem;

means responsive to the setting of a mode bit in each said stored primary command for conditioning said secondary subsystem to operate in either a high speed mode or a programmable offline mode;

means rendered effective when said secondary subsystem is operating in said high speed mode for transferring data at high speeds between said device and a memory in said primary subsystem;

means for storing an array of multiple secondary commands; and

means rendered effective when said secondary subsystem is operating in said programmable offline mode for causing said secondary subsystem to perform a program of secondary data processing operations defined by commands in said stored array; said secondary operations being conducted in an offline relationship to operations concurrently being conducted in said primary subsystem, and permitting said secondary subsystem to exchange data with either said device or a memory in said primary subsystem and to process said data without assistance or direction from said primary subsystem.

2. An improved secondary subsystem in accordance with claim 1 comprising:

means responsive to a concluding condition manifested while said secondary subsystem is operating in either said high speed or said programmable offline mode for examining a chaining flag bit contained in a stored primary command designating that mode; said chaining bit representing either a chaining or a non-chaining condition; and

means responsive to the condition represented by said examined chaining bit for causing said secondary subsystem to retrieve and interpret another primary command when said chaining bit represents a said chaining condition and otherwise to post a status interruption to said primary subsystem and terminate its current operation without chaining when said chaining bit represents a non-chaining condition.

3. A secondary subsystem in accordance with claim 2 wherein said means for storing said array of secondary commands comprises:

a storage medium;

means rendered effective when a said primary command received from said primary subsystem contains a mode bit specifying said programmable offline mode for directing said secondary subsystem to interpret an additional type bit in said primary command distinguishing the respective command as either a load type command or a start type command;

means rendered effective when said primary command is a load type command for causing said secondary subsystem to retrieve a said secondary command array from said memory in said primary subsystem and to store said array in said storage medium; and

means rendered effective when said primary command is a start type command for causing said secondary subsystem to perform a program of operations defined by secondary commands previously stored in said medium by said retrieving and storing means.

4. A secondary subsystem in accordance with claim 3 wherein said load type primary command contains line position information variably defining a starting line position in an array loaded in response to the respective command; and

said secondary subsystem includes means for retaining said starting line position information and responsive to said information interpretation of a start type primary command for causing said secondary subsystem to interpret commands in said stored array in a predetermined sequence beginning with a command located at a starting line position.

5. A secondary subsystem in accordance with claim 4 wherein:

each said start type primary command contains information defining a variable sized area in said memory in said primary subsystem;

any said stored secondary command list array may contain a variable number of secondary commands defining a corresponding number of data transfers relative to said variable sized area; and

said secondary subsystem contains means rendered effective when said area is either filled or emptied during execution of said secondary commands for manifesting a said concluding condition to said secondary subsystem.

6. A secondary subsystem in accordance with claim 4 wherein each said start type secondary command contains a command number indication and said secondary subsystem comprises:

means for storing said command number;

means for counting the number of secondary commands of a specific type interpreted by said secondary subsystem in response to each start type command;

means for determining when the counted number of interpreted secondary commands exceeds the value of the stored command number; and

means responsive to said equality determination for manifesting a said concluding condition.

7. In a data processing system containing a primary processing subsystem, a device and a secondary processing subsystem, interfacing between the primary subsystem and device, an improved secondary subsystem comprising:

a secondary microprocessor;

cycle steal adapter means for exchanging data with a directly accessible memory in said primary subsystem;

device adapter means for exchanging data with said device in a variable format;

means interconnecting said adapter means for passing data bidirectionally between said device and said primary subsystem memory;

means connecting said microprocessor with both said adapter means for transferring primary command information from said primary subsystem to a memory in said microprocessor, and including means for transferring data and other information between said memory in said micoprocessor and either said memory in said primary subsystem or said device;

said microprocessor containing means responsive to primary commands received one at a time from said primary subsystem for conditioning said secondary subsystem to operate in either a high speed cycle stealing mode or a programmable offline mode;

said adapter means comprising means conditioned by said microprocessor in said high speed mode for operating said adapter means autonomously relative to said microprocessor to transfer an amount of data specified in said primary subsystem and said device; and

means conditioned by said microprocessor in said programmable offline mode for operating said adapter means under direct control of said microprocessor to transfer data between said memory in said microcessor and either said device or said memory in said primary subsystem.

8. A method of operating a data processing system containing primary and secondary processing subsystems comprising:

storing a program of chainable primary commands variably defining high speed and programmable offline modes in response to a setting of a mode bit;

interpreting said commands in said secondary subsystem in a predetermined sequence and establishing operating modes defined by said commands;

performing I/O data transfers, under the direction of said secondary subsystems, between a memory in said primary subsystem and a peripheral device while said high speed mode is effective;

storing an ordered array of multiple secondary data processing commands in said secondary subsystem; and

directing said secondary subsystem to perform one or more programs of secondary data transfer and data processing operations defined by commands in said list array when said offline mode is effective; said programs being performed without assistance or interference from said primary subsystem.

Description

CROSS REFERENCE TO RELATED PATENT APPLICATIONS

The present patent application is related to the following copending patent applications:

(1) Application Ser. No. 345,177, filed Feb. 2, 1982, entitled "PERIPHERAL INTERFACE ADAPTER CIRCUIT FOR USE IN I/O CONTROLLER CARD HAVING MULTIPLE MODES OF OPERATION", the inventor being C. A. Heath; and

(2) Application Ser. No. 345,129, filed Feb. 2, 1982, entitled "PERIPHERAL ATTACHMENT INTERFACE FOR I/O CONTROLLER HAVING CYCLE STEAL AND OFF-LINE MODES", the inventors being L. P. Andrews et al.

The descriptions set forth in these copending applications are hereby incorporated in the present application by this reference thereto.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to data processing systems in which I/O operations relative to a primary processing subsystem are directed by intelligent secondary subsystems containing a programmable microprocessor or the like.

2. Prior Art

Contemporary data processing systems have made extensive use of programmable microprocessors, in their I/O channels and I/O controllers, for directing transfers of data between peripheral devices and (a memory in) a primary (host) subsystem and even for relieving the host subsystem of certain path management and path selection duties traditionally assigned to host software. In some systems these "secondary" microprocessors have even been adapted to perform traditional data processing functions as satellites of the primary subsystem (e.g. to perform matrix multiplications). However, such satellite operations are usually tightly controlled by primary system software, requiring passage of "raw" data from the primary subsystem to the secondary subsystem and return of "processed" data to the primary subsystem, as well as requiring the primary subsystem to prepare commands for directing the performance of these data processing operations in the secondary subsystem. We have realized that this type of hierarchical organization is not well suited for supporting real time process management applications or the like wherein the time from solicitation of attention by a device to transfer of a corresponding attention or control indication may be critical. In such environments, contention for primary system resources by real time processes may not only present undue interference with other important system operations but also it may prevent the primary system from giving timely attention to other time-critical processing conditions.

SUMMARY OF THE INVENTION

The present invention enables a secondary subsystem, containing processor and memory facilities separate (either physically or logically) from those of a primary subsystem, to function either as an I/O controller associated with a device and presenting a single device address to the primary subsystem, or as a fully independent processor capable of acquiring data from the device, processing such data and controlling the device without any assistance from the primary subsystem. The invention also permits the secondary subsystem to store programs of "secondary" commands for directing such independent data acquisition and processing activities with little or no assistance from the primary subsystem.

A feature of the invention is that primary command descriptors herein termed "Device Control Blocks" or DCB's--which are retrieved one at a time by the secondary subsystem (from primary subsystem storage)--contain a mode setting bit which evokes operation of the secondary subsystem in either a basic high speed data transfer mode or a programmable offline mode. In the high speed mode data is transferred between a (directly accessible) memory in the primary subsystem and a device. In the programmable offline mode the secondary subsystem is conditioned to interpret one or more programs of secondary commands contained in a "command list" prestored in the secondary subsystem. These programs permit the secondary subsystem to acquire and process data and control the device without assistance from the primary subsystem.

Another feature is that the primary commands are chainable to cause the secondary subsystem to switch dynamically back and forth between its high speed and programmable offline modes under certain predefined real time conditions. This, for instance, permits a system user to direct the secondary subsystem to acquire and process small data items in offline mode, and then switch the system to high speed mode for passing other large data sets (generally at higher than offline speed) between the primary subsystem and device. It also permits the secondary subsystem to move data between a device multiplexor and a memory area in the primary subsystem at slow speeds, with intermediate storage of block portions of the data in the secondary subsystem, whereby the secondary subsystem may selectively examine and process portions of the data in transit.

Another feature is that each primary command descriptor (DCB) for evoking the offline mode contains a type bit distinguishing the respective command as either a load type or a start type. The load type command contains a "starting line" parameter, defining a command position in an associated command list array, and a "command list length" parameter which if other than 0000 defines the number of commands in the associated array. If the list length parameter is not 0000 the load type DCB causes the secondary subsystem to store the starting line and list length parameters, locate a command list array in the (directly accessible) memory of the primary subsystem and load that array into its own memory. If the list length parameter is 0000 and the secondary subsystem's memory contains a previously loaded command list, the secondary subsystem only stores the starting line information. The start type DCB causes the secondary subsystem to interpret commands in a previously stored command list, in a predetermined sequence, beginning with a command defined by a previously stored starting line parameter.

Another feature is that the processing of secondary commands in offline mode may be interrupted at any position in the command list array, and when so interrupted is restartable at that position, without having to reload the array, by a chained or otherwise received load type command containing a list length of 0000 and a starting line parameter pointing to the interruption position.

Another feature is that processing of secondary commands in offline mode is terminatable when: (a) the number of secondary commands which have been processed exceeds an "operation length" parameter specified in the start type primary command under which the current secondary sequence was started; or (b) the number of data bytes transferred between primary system storage and the secondary subsystem exceeds the capacity of an area effectively designated by the associated start type command; or (c) a device end or exception interruption is specifically evoked by a secondary command.

For a more complete understanding of the invention, and a comprehension of other features and advantages thereof, reference should be made to the following description in connection with the accompanying drawings, and to the appended claims which indicate the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a system block diagram broadly illustrating a system environment in which the present invention is useful.

FIG. 2 provides a schematic view of various system configurations in which a secondary processing subsystem in accordance with the present invention may be used.

FIG. 3 is a functional flow diagram illustrating the operation of a system including a secondary subsystem in accordance with the present invention.

FIG. 4 illustrates a process by which primary command information is prepared by a primary subsystem and supplied to a secondary subsystem for initiating operations of the present invention.

FIG. 5 illustrates the form and logical utilization of various types of primary commands in accordance with the present invention.

FIG. 6 illustrates the form of a secondary command list array in accordance with the present invention.

FIG. 7 illustrates the logical organization of a secondary subsystem for moving data between a memory in that subsystem and either a primary subsystem or device in response to indicated secondary commands.

FIG. 8 illustrates the logical organization of a secondary subsystem for moving data internally in response to indicated secondary commands.

FIG. 9 illustrates a device interface for busing variable format data relative to a secondary subsystem adapter in accordance with the high speed mode of operation associated with the present invention.

FIG. 10 illustrates a schematic block diagram of a secondary microprocessor and its ROS and RAM.

FIGS. 11 and 12 respectivelly illustrate maps of ROS and RAM allocation; ROS for subroutine storage and RAM for storage of IDCBs, DCBs, data, command list parameters, etc.

FIGS. 13-15 illustrate various dual mode real time applications for subject SPO type DCBs.

FIGS. 16-18 respectively illustrate microprocessor interpretation sequences for IDCB handling, DCB retrieval/interpretation and secondary command (command list) retrieval/interpretation.

DETAILED DESCRIPTION

FIG. 1 schematically illustrates an environmental system incorporating an embodiment of the invention. Primary data processing subsystem 1 communicates with peripheral device or device multiplexor 2 through secondary processing subsystem 3. Primary subsystem 1 is conventionally configured and includes a central processing unit 1a, a memory 1b, and one or more I/O channels 1c. For certain presently contemplated real time process control applications an IBM Series/1 processing system with architecture modifications described herein would be entirely adequate for embodying the subsystem 1. For background descriptions of relevant aspects of Series/1 systems reference may be made to IBM Publication G 360-0061-5, File No. 51-00 "IBM Series/1 Digest", Copyright 1981 International Business Machines Corp., and U.S. Pat. Nos. 4,038,642 to Bouknecht et al (entitled "Input/Output Interface Logic") and 4,053,950 to Bourke et al (entitled "Residual Status Reporting During Chained Cycle Steal Input/Output Operations").

Subsystem 3 comprises: a host interface adapter 3a, for exchanging data with memory 1b in a cycle stealing mode (via channel 1c and a not-shown direct access coupling to the memory); peripheral interface adapter elements 3b, 3c and 3d interfacing with device or device multiplexor 2 for respectively exchanging data (in various formats), handshaking signals for timing data movements, and other control signals; a microprocessor 3e; a random access memory 3f accessible to microprocessor 3e; a bus 3g for transferring data betweem adapters 3a and 3b, a bus 3h for passing data and other information between subsystem 1 and microprocessor 3e via adapter 3a; a bus 3i connecting microprocessor 3e with storage 3f and adapters 3b, 3c and 3d; and lines 3j between adapters 3b and 3c for coordinating data transfer and handshake signalling operations therebetween. Subsystem 3 links to subsystem 1 and device 2 via external buses respectively indicated at 4 and 5.

In accordance with the present invention subsystem 3 is switched dynamically between two distinct modes of operation--high speed (HS) and programmable offline (PO) modes--in response to a dedicated mode bit in certain primary command descriptors termed "device control blocks" (hereafter DCB's). DCB's are prepared in memory 1b by primary subsystem software, are retrievable and interpretable by subsystem 3, and are linkable by chaining. Consequently, subsystem 3 may be programmed to switch dynamically back and forth between HS and PO modes under conditions described herein.

With state-of-the-art integrated circuit packaging technology, subsystem 3 is packageable on a single multi-chip card, and is referred to in FIG. 1 and variously in this text as an "attachment feature card" or "attachment". It should be understood that to subsystem 1 attachment card 3 and device 2 are "viewable" as a single device address and that channel 1c is susceptible of attachment to plural such cards and other device controllers.

Adapter 3a and its interface busing 4 are described in U.S. Pat. No. 4,246,637. Adapted 3b and bus 3g are fully described in the above cross-referenced co-pending patent application by Heath. Adapters 3c, 3d and interface buses 5 are described in the above cross-referenced co-pending patent application by Andrews et al. The disclosures of these applications are hereby incorporated in this description.

FIG. 2 illustrates various examples 10-14 of possible attachment usage configurations. Example 10 shows a single attachment card 3 linking a device such as 2 with a host subsystem such as 1 (through a not-shown host channel such as 1c, see FIG. 1). Example 11 shows two attachment cards separately attaching two devices to one host system (through separate not-shown subchannels of a not-shown host channel). Example 12 shows two attachment cards presenting an extended parallel data busing interface to a single device and linking that device to one host system. Example 13 shows two attachment cards linked to one host system for passing data between two subchannels of the system using a card-to-card tandem linkage described in the above cross-referenced co-pending patent application by Andrews et al. Example 14 shows two attachment cards linking two separate and relatively asynchronous host systems via the just-mentioned tandem linkage configuration.

As explained above subsystem 3 operates alternately in high speed (HS) and programmable offline (PO) modes in response to a mode bit parameter contained in sequentially interpreted command descriptor arrays termed DCBs (Device Control Blocks). The processes by which such DCBs are prepared, fetched and interpreted are illustrated generally in FIGS. 3 and 4.

As suggested at 20 and 21, application software, operating on the host processor, schedules operations of devices including the subject attachment card by preparing an initiating instruction OIO (Operate I/O) and an "immediate" command descriptor IDCB (Immediate Device Control Block). At a suitable time 21 the host processor interprets the OIO instruction, and using address information in the instruction, retrieves the IDCB. The IDCB specifies a device address (in this instance the address of the attachment card) and an IDCB command function. This command function specifies either a DPC (Direct Program Controlled) operation 22 or a CS (Cycle-Steal) operation mode 23.

While interpreting the IDCB the host processor instigates selection of the attachment card and branches on the command function. If DPC operation is specified the host processor and attachment card interact synchronously to conduct a data transfer 22 between microprocessor storage on the attachment card and an "immediate data field" portion of the IDCB. This transfer requires the host processor and attachment microprocessor to directly control appropriate elements in respective subsystems; for steering the immediate data to or from the channel/attachment interface on the host side and through the host interface adapter from or to microprocessor storage on the attachment side. If a CS operation is defined by the IDCB a copy of the IDCB is transferred to microprocessor storage on the attachment card, as suggested at 24, and thereafter the attachment card microprocessor uses IDCB information to condition host adapter 3a (FIG. 1) to perform a "cycle-steal write" transfer of a DCB (Device Control Block) command descriptor from host storage to attachment microprocessor storage. The DCB--consisting of eight 16-bit words described later--directs the microprocessor and attachment subsystem to perform additional operations. Retrieval and interpretation of the DCB are suggested at 25 in FIG. 3.

To this point, the operations described above are conventional "prior art" functions traditionally performed by IBM Series/1 processing systems and I/O controllers pre-dating the present invention. Such operations have been disclosed, for instance in the above-referenced U.S. Pat. No. 4,246,637 to Brown et al. However, in the present instance, the DCB contains mode setting and chaining bit parameters which invoke varied modes of attachment operation presently considered unique and novel.

Branching on the condition of the just-mentioned mode bit in the DCB (decision 26, FIG. 3) the attachment microprocessor instigates a sequence of attachment subsystem operations in either a high speed (HS) mode 27 or a programmable offline (PO) mode 28. In HS mode the microprocessor selects its attached device 2 (which, relative to the primary subsystem, has the same device address as the attachment card), and prepares host interface adapters 3a and 3b and device 2 (operation 29) to conduct a data transfer (having a byte count length specified in the DCB) between host memory and device 2 (operation 30). In such transfers the data traverses interface 5 in one of several bit-parallel formats specified by the DCB, and is appropriately converted to adapter 3b to format compatible with a fixed busing configuration at the host adaption interface. This type of operation, conducted by the adapters in asynchronous relation to contemporary operations of the host processor and attachment microprocessor, is described in the above cross-referenced application by Heath.

In PO mode the attachment microprocessor branches on a presently unique "type bit" in the DCB (decision 31, FIG. 3) to perform either a "command list" preparation operation 32 or a program of operations 33 defined by "secondary commands" contained in a previously prepared command list. When the type bit value is 0 the DCB is termed a "Load Programmable Offline" (LPO) mode type DCB, and when the type bit is 1 the DCB is termed a "Start Programmable Offline" (SPO) mode type DCB.

When interpreting an LPO type DCB the attachment microprocessor branches at 34 on the value of a 4-bit list length factor contained in that DCB. If this value is other than 0000 the microprocessor conditions adapter 3a to retrieve a "command list" array, from an area of host memory effectively defined by boundary address information contained in the DCB in combination with a list length factor contained in the DCB. The microprocessor loads this command list array into a pre-assigned area of microprocessor storage, as suggested at 35. The loaded array contains a variable number of 16-bit "secondary" command words (DCBs presently are referred to as primary commands and commands in a command list are termed secondary commands). Preserving list length and starting line factors contained in this DCB, as suggested at 36 and 37, the microprocessor now branches at 38 on the value of the chaining bit contained in the DCB. If the chaining bit is 0 (chaining not specified) the microprocessor posts a status interruption to the host system, as suggested at 39, and concludes the current sequence of attachment subsystem operations. If the chaining bit is a 1 (chaining specified) the microprocessor and adapter 3a cooperatively retrieve another DCB and sequence through another series of operations conditional on the value of the mode bit in that DCB. When an LPO type DCB contains a 0000 list length factor the microprocessor takes the "YES" branch at decision step 34. It thereby skips command list loading step 35, but preserves new DCB start line information 37, and then takes chaining branch 38.

When interpreting an SPO type DCB (sequence 33, FIG. 3) the microprocessor uses the start line information preserved at 37, as an initial "command address", for entering a command list previously stored in microprocessor storage, and performs a program of operations defined by a series of secondary commands in said list beginning at the initial address. The microprocessor repeatedly retrieves a command at the command address, performs a function defined by the command, and increments the command address until it encounters one of several "ending conditions" explained later. This sequence is shown at 40. When the ending condition is encountered the microprocessor stores status as suggested at 41, and takes chaining bit branch 38.

For the sake of clarity, FIGS. 4 and 5 indicate the logical organization of the system formed by the host and attachment subsystems in respect to performance of the foregoing operations. As shown at 51 and 52 in FIG. 4, the OIO instruction and the IDCB descriptor are double-word (32-bit) expressions. The OIO, which is handled only by the host processor, contains the effective address in host storage of the IDCB as suggested at 53. As previously explained, the IDCB evokes a coordinated information transfer between the host and attachment subsystems in either a DPC or CS mode. The IDCB contains a command defining portion 54, a device (address) identifying portion (in this instance defining the address of the attachment card), and a portion 56 having a variable context depending on the information in the command portion. Decoding logic 57 in the host subsystem examines the command portion and sets up either a DPC transfer operation through "switch path" 58 or a CS transfer operation through switch path 59.

In the present instance, the device address portion 55 is used by the host subsystem to select the attachment card. In a DPC transfer, field portion 56 of the IDCB constitutes an "immediate data field", which represents either a source or destination of immediate data to be sent to or received from attachment microprocessor storage. In a CS transfer, address information contained in a portion 56 defines the boundary address in host storage of the first word of an 8-word (128-bit) DCB descriptor. This information passes to the attachment card (suggested in dotted outline at 3), which thereafter operates on an asynchronous basis to retrieve the associated DCB.

As shown at 60 and 61 in FIG. 5, a DCB descriptor in accordance with the present invention comprises an eight-word expression having words individually designated as words 0 through 7 (abbreviated WD0, WD1, etc.). Each word contains 16 bits, designated bits 0 through 15. Word 0 contains the chaining bit (WD 0, bit 0), and othr information defined below. Word 1 bit 0 contains the mode defining bit (designating HS or PO mode). Other bits in word 1, bit 2 of word 0 and all bits of words 2, 3, 6 and 7, have varied contexts of interpretation explained below, dependent on the value of the mode bit. Word 4 contains the beginning address in host storage of an 8-word area for storage of "residual status block" (RSB) information defined below. Word 5 defines a chaining address which is used when the sequence of operations for interpreting this DCB concludes and the chaining bit of this DCB specifies chaining (word 0, bit 0=1).

FIG. 5 provides an overview of the definitions and logical effects of certain key parts of the DCB. All of the DCB elements are more completely defined below.

Referring to FIG. 5, when the mode bit specifies HS mode (word 1, bit 0=0) the second bit of word 1 (word 1 bit 1) defines a command suppress function indicated at 62 (if this bit is 0 a "device directed command" function contained in words 2 and 3, and indicated at 63 and 64, is transferred by the attachment subsystem to the device, but if this bit is 1 this command transfer is suppressed). When PO mode is specified (word 1 bit 0=1) the second bit of word 1 distinguishes command type, as suggested at 65 (type LPO if the bit is 0, type SPO if it is a 1).

If HS operation is specified bit 2 of word 0 defines a transfer of data in one of two directions, from the device to host storage (a "READ" transfer) if this bit is a 1, or from host storage to the device (a "WRITE" transfer) if this bit is a 0. This transfer is performed by adapters 3a and 3b (FIG. 1) without microprocessor interference, and without intermediate storage of data in microprocessor storage. The amount of data transferred in this mode is specified by a transfer byte count contained in DCB word 6.

If PO mode is defined, the meaning of word 0 bit 2 depends on the value of the type bit (word 1 bit 1). If LPO type is specified word 0 bit 2 must be 0 (in effect associating with a "write" transfer of a command list from host storage to microprocssor storage; refer to operation 35, FIG. 3). However, if SPO type is defined word 0 bit 2 must be 0, and may have a dual directional context explained later under "dual mode operation". In respect to this context, when SPO type is specified plural data transfer operations may be conducted intermittently between the attachment and plural areas of host storage under the direction of certain secondary (command list) commands specifying read and write transfer operations.

When PO mode and LPO type are specified word 2 is idle (by convention set to all 0's), as suggested at 66, and words 3, 6 and 7 respectively contain "start line", "list length" and "start address" parameters suggested respectively at 67, 68 and 69. If length 68, defined by word 6, has a value other than 0000 (hexadecimal), address 69 defines the beginning of an area in host storage containing a command list which is to be transferred to (loaded into) microprocessor storage. In this case, address 69 and length factor 68 are used to access the list area in host storage and carry out the transfer one command at a time (operation 35, FIG. 3). The start line factor 67 is used by the attachment microprocessor to determine a command line position, within the (loaded) command list at which processing of secondary commands is to begin when the microprocessor subsequently operates under direction of an SPO type DCB. If the list length value is 0000 (Hex), certain parts of the DCB (the start line and list length factors) are preserved in microprocessor storage, for effectively enabling the microprocessor to access a list loaded under the direction of a previously interpreted LPO type DCB, but the LPO type DCB immediately being interpreted is not used for transferring a command list to microprocessor storage.

When PO mode and SPO type are specified, word 2 of the DCB represents a "read byte count" 70, word 3 defines a "read start address" 71, word 6 defines a "write byte count" 72 and word 7 defines a "write start address" 73. The read start address and byte count effectively define an area in host storage into which data may be transferred from the attachment (by operation of certain secondary commands contained in a command list currently resident in microprocessor storage), and the write start address and write byte count functions define another area in host storage (usually, but not necessarily, separate from the read area) from which data is to be extracted for transfer to the attachment under the direction of certain write commands in the currently resident command list.

When HS mode is specified, bits 2-15 in DCB word 1 have contexts indicated at 74. Two of these bits are used to specify one of four device interface formats, for the associated data transfer (these formats being defined below and described in the above cross-referenced patent application--by Heath). Four of these bits define one of 16 timer waveforms selected from a timer source described in the above cross-referenced patent application by Andrews et al. The remaining bits define the location in host storage of an array indexing factor to be used when a certain device interface format (B16) and an associated array indexing operation are specified (these formats and array indexing are described in said Heath application (in array indexing the microprocessor and adapters 3a, 3b operate in coordination to transfer address information from the microprocessor to the device and certain "array data" between host storage and the device).

When PO mode is specified bits 2-15 in word 1 are all 0's if the DCB is LPO type, as shown at 75. However, if the DCB is SPO type, these bits are used as shown at 76 to define one of several handshaking formats (for the device interface), one of 16 timer waveforms (similar to the times defined for HS operation) and a maximum operation length parameter indicating the maximum number of secondary commands which may be executed under the direction of the respective DCB.

These DCB definitions are specified in more specific detail as follows:

HS MODE (WORD 1, BIT 0=0)

This mode permits rapid transfer of data between the attached device and host storage, without microprocessor or host processor assistance and without storage of the data intermediately in microprocessor storage. The amount of data transferred is specified in word 6. The word portions of this DCB have the following meanings (for attachment subsystem interpretation).

DCB WORD 0 (CONTROL WORD)

    ______________________________________
    Bit 0     Chaining flag. When this bit is a 1, the
              attachment performs a chaining procedure.
              The attachment completes the current
              operation, but does not send an interrupt
              request to the host processor. Instead,
              the attachment fetches the next DCB in the
              chain and performs the next operation.
              (DCB word 5 indicates the location of the
              next DCB). Chaining continues until the
              attachment fetches a DCB that has a chaining
              flag set to 0, thus indicating the last
              operation in the chain.
              If the suppress exception bit (bit 4) is a
              1, a residual status block (RSB) is stored
              for each operation in the chain, unless an
              exception interrupt is reported. An excep-
              tion interrupt also terminates a chain.
              (Refer to the explanation of bit 4.)
    Bit 1     Program-controlled interrupt. When this
              bit is a 1, a program-controlled interrupt
              is posted upon completion of the DCB
              fetch. (Each interrupt must be serviced
              before another interrupt can be posted.)
    Bit 2     Input flag. For this (HS) mode this bit
              indicates which direction data is to be
              transferred. When this bit is a 1, the
              attachment transfers data to processor
              storage; when this bit is a 0, data is
              transferred from processor storage to the
              attachment.
    Bit 3     This bit is not used in this operation;
              it must be a 0.
    Bit 4     Suppress exception. When this bit is a 1:
              Exceptions in length which would
              otherwise cause an exception interrupt
              are reported as permissive device end.
              The status of the attachment is stored
              at the address specified by the residual
              status block address (DCB word 4),
              unless an exception interrupt is
              reported.
              A residual status block (RSB) is posted at
              the end of each operation that is programmed
              for suppress exception. The format of the
              RSB is discussed below under "Residual
              Status Block".
    Bits 5-7  Address key. This is a three-bit key that
              the attachment presents during data transfer
              to verify that the program has authorization
              to access processor storage. An incorrect
              address key causes an exception interrupt.
    Bits 8-10 These three bits are not used in this
              operation; they must be 0's.
    Bits 11-13
              Program-controlled interrupt ID.
              These three bits are presented as
              bits 3, 4, and 5 of an Interrupt
              Information byte (IIB) explained later,
              during a following program-controlled
              interrupt. (All other bits in the IIB
              are 0's.)
    Bit 14    21-second time-out. When this bit is
              a 1, it activates a 21-second time-out
              on the DCB operation. The attachment
              must either chain or interrupt within
              21 seconds; otherwise, an exception
              interrupt is reported, and bit 9 of
              cycle-steal status word 3 is set to 1.
              When this bit is 0, the time-out is
              not used.
    Bit 15    Terminate chaining. When this bit is
              a 1, in conjunction with bits 0 and 4
              set to l's, the attachment suppresses
              exceptions in length. However, it
              terminates chaining operations when
              a short exception in length is en-
              countered (that is, the data that is
              transferred is less than the byte
              count specified in word 6).
              When this bit is a 1 and either bit
              0 or bit 4 is a 0, the attachment
              reports a DCB specification check.
              When this bit is a 0 and bit 4 is a 1,
              the attachment continues chaining
              despite short exceptions in length.
    ______________________________________

    ______________________________________
    Bit 0    DI/DO definition. This bit is set to 0 to
             define HS (high-speed DI/DO) mode
             operation.
    Bit 1    Command suppress. If this bit is a 0, the
             command words given in DCB words 2 and 3
             are delivered to the device. If this bit
             is a 1, delivery of the command words to
             the device is suppressed.
    Bits 2, 3
             Format. These bits define the format
             of the attachment interface:
           Bits 2, 3
                    Interface format
           00        8 bits, unidirectional (U8)
           01       16 bits, unidirectional (U16)
           10       16 bits, bidirectional (B16)
           11       32 bits, bidirectional (B32)
             (For information about these formats and the
             attachment-device interface, refer to copending
             applications by Health and Adrews et al
    Bits 4-7 Timer value. These bits designate the
             timer output period to be used (refer to
             BC9-81-013 for information timer usage).
           Bits 4-7   Timer output
           0000       No transitions
           0001        10.4 usec pulse*
           0010        10.4 usec
           0011        20.8 usec
           0100        41.6 usec
           0101        83.3 usec
           0110       166.6 usec
           0111       333.3 usec
           1000       666.6 usec
           1001       1.333 msec
           1010       2.666 msec
           1011       5.333 msec
           1100       10.66 msec
           1101       21.33 msec.
           1110       42.66 msec.
           1111       85.33 msec
    Bits 8-15
             Array index boundary (port 0 counter
             preset). When in 16-bit bidirectional
             format, this field is set into the
             high-order byte of the bus not used
             for data transfer. The low-order byte
             is set to hex 00. Together, the two
             bytes form an array index expression
             whose use is described in Heath.
             Formats other than 16-bit bidirectional
             must have bits 8-15 set to hex 00;
             otherwise the attachment posts a DCB
             specification check.
    ______________________________________
     *0001 causes a single pulse; all other options cause a continuously
     repetitive signal.

    ______________________________________
    Bit 0    Chaining flag. Same context as in HS mode
             DCB
    Bit 1    Program-controlled interrupt. Same as for
             HS mode.
    Bit 2    Input flag. This bit indicates which
             direction data is to be transferred.
             Because data (i.e. command list) transfer
             for this type of operation is always from
             host storage to the attachment, this bit
             must be a 0. Otherwise, a DCB specification
             check will result.
    Bit 3    This bit is not used in this operation;
             it must be a 0.
    Bit 4    Suppress checksum non-compare. The attach-
             ment always.transfers and checks the check-
             sum (the last word of the command list).
             When bit 4 is set to 1, checksum non-compare
             exceptions do not result in exception
             interrupts. However, the checksum error
             status is set, and the residual status
             block is stored at the address specified by
             the residual status block address (DCB word
             4), if an exception interrupt is not
             reported.
             Note: This bit does not suppress interrupts
             caused by exceptions in length. Nor does it
             cause retries to occur when checksum non-compare
             exception interrupts are suppressed.
    Bits 5-7 Address key. Same as HS mode.
    Bits 8-10
             These three bits are not used in this
             operation; they must be 0's.
    Bits 11-13
             Program-controlled interrupt ID.
             Serves as HS mode.
    Bit 14   21-second time-out. This bit must be
             a 1. It activates a 21-second time-
             out on the DCB operation. The attach-
             ment must either chain or interrupt
             within 21 seconds, or an exception
             interrupt is reported.
    Bit 15   Terminate chaining. This bit must
             be a 0.
    ______________________________________

    ______________________________________
    Bit 0       This bit is a 1 for all PO mode
                operations.
    Bit 1       This bit is a 0 for LPO type operation.
    Bits 2-15   These bits are reserved; they must
                be 0's.
    ______________________________________

    ______________________________________
    Bit 0      Chaining flag. Same as for HS.
    Bit 1      Program-controlled interrupt. Same as HS.
    Bit 2      Input flag. For this DCB, this bit must be
               a 1. This DCB is used to invoke execution
               of a series of command list commands which
               may direct data transfers both to and from
               host storage (see "Dual Mode Applications"
               below).
    Bit 3      This bit is not used and must be 0.
    Bit 4      Suppress exception. Same as HS.
    Bits 5-7   Same as HS.
    Bits 8-10  These bits are reserved and must be 0's.
               Otherwise, a DCB specification check will
               result.
    Bits 11-13 Program-controlled interrupt ID.
               Same as HS.
    Bit 14     21-second time-out. When this bit is a 1,
               it causes a programmable offline mode I/O
               operation to terminate 21 seconds after
               the operation is started, if it has not
               already terminated. Status is then
               returned to the command list program that
               a time-out has occurred.
               When this bit is a 0, the time-out is not
               used.
    Bit 15     Terminate chaining (short exceptions in
               length). When this bit is a 1, in conjunc-
               tion with bits 0 and 4 set to l's, the
               attachment suppresses exceptions in length.
               However, it terminates chaining operations-
               when a short exception in length is
               encountered (that is, the data that is
               transferred is less than the byte count
               specified in word 2 or word 6 of the start
               programmable offline mode DCB).
               When this bit is a 1 and either bit 0 or
               bit 4 is a 0, the attachment reports a DCB
               specification check.
               When this bit is a 0, the attachment
               continues chaining despite exceptions in
               length.
    ______________________________________

    ______________________________________
    Bit 0      This bit is a 1 for all PO mode operations.
    Bit 1      This bit is a 1 for SPO type operation.
    Bits 2, 3  Handshake. These bits define the hand-
               shaking of the interface. Bit 2 controls
               bus 1; bit 3 controls bus 0. Coding is as
               follows:
               1 = device request (device controls
               transfers)
               If either bit is a 1, data transfers
               on the bus controlled by that bit are
               initiated by a request from the device.
               Command processing halts pending pro-
               grammable offline mode I/O transfers.
               0 = internal request (attachment
               controls transfers)
               If either bit is a 0, no request is
               required from the device for that bus.
    Bits 4-7   Timer value. Same as for HS.
    Bits 8-11  Operation length. This field contains a
               code that designates the maximum permissible
               operation length, that is, the number of
               secondary (command list) I/O commands that
               may be performed as a result of a single
               SPO type DCB. If the designated maximum
               is exceeded, the program terminates with a
               device end interrupt, and bit 11 in cycle-
               steal status word 3 is set to 1.
    Bits         Operation length
    8-11         Hex      Decimal
    ______________________________________
    0000         1        1
    0001         2        2
    0010         4        4
    0011         8        8
    0100         10       16
    0101         20       32
    0110         40       64
    0111         80       128
    1000         100      256
    1001         200      512
    1010         400      1024
    1011         800      2048
    1100         1000     4096
    1101         2000     8192
    1110         4000     16384
    1111         8000     32768
    ______________________________________
    Note:
    While this parameter is intended as a
    terminating default condition, any length
    operation may be achieved by chaining multiple
    DCBs so that each succeeding DCB restarts the
    command code of the preceding DCB. For example: -
          First DCB operation length
                             512
    Second DCB operation length
          128
    total operation length
          640
    As many DCBs as are needed may be chained to
    achieve the desired total.
    A command list program that terminates as a result
    of the operation length being exceeded may be restarted
    by using the restart feature of LPO (DCB word 3). -
         Bits 12-15
                   This field must be all 0's, or a DCB
        specification check will result.
    ______________________________________

    ______________________________________
    Bit 0        End of chain (EOC). This bit
                 is a 1 when bit 0 of DCB word 0 is
                 a 0.
    Bit 1        Retry (RT). This bit is not used
                 and is always a 0.
    Bits 2-7     Reserved. These bits are al-
                 ways 0's.
    Bit 8        Write excess length (WEL). The
                 length of the transfer on the
                 device interface exceeds the byte
                 count specified in the DCB.
    Bit 9        Read excess length (REL). The
                 length of the transfer on the de-
                 vice interface exceeds the byte
                 count specified in the DCB.
    Bits 10-13   Reserved. These bits are al-
                 ways 0's.
    Bit 14       Incorrect-length record (ILR).
                 This bit indicates that the record
                 written to or read from the device
                 is shorter or longer than the byte
                 count specified in the DCB.
    Bit 15       No error (NE). This bit is a
                 summary of bits 8, 9 and 14. When
                 When each of those bits is a 0, bit
                 15 is a 1.
    ______________________________________

    ______________________________________
    Bit 0      Attachment parity check. Bad
               parity was received on the device
               interface (when parity operation is
               selected).
               Note: This bit is always reported
               as a 0.
    Bit 1      Cycle-steal status error. An error
               was detected during processing of
               the Start Cycle Steal Status com-
               mand operation.
               Note: This bit is always reported
               as a 0.
    Bit 2      Exceptional length transfer. The
               attachment did not transfer the
               entire length of the record(s).
               The number of transfers on the
               device interface exceeds the byte
               count.
    Bit 3      Checksum error. A checksum comparison
               error occurred during command list
               load.
    Bit 4      Programmable offline mode process
               error. The command decoder was
               unable to process a command line.
               Note: This bit is always reported
               as a 0.
    Bit 5      Excessive length command list. The
               offline code command list length
               exceeded the command list length
               specified in the DCB.
               Note: This bit is always reported
               as a 0.
    Bit 6      Device error. The last operation
               terminated due to loss of the `ready`
               line on the device interface, or
               a + transition occurred on the
               `ready` line when the attachment
               was not busy. This bit is reported
               only after a load programmable off-
               line mode DCB.
    Bit 7      Equipment check. The attachment
               detected an internal malfunction,
               or a DCB of other than 16-bit bi-
               directional mode received while
               the card-to-card option switch is
               set on.
               Note: This bit is always reported
               as a 0.
    Bit 8      Bidirectional data transfer. The
               last transfer was a bidirectional-
               DCB transfer
    Bit 9      21-second time-out. DCB word 0
               bit 14 was set to 1 and a time-out
               occurred because the attachment
               operation did not complete the data
               transfer within 21 seconds. This
               bit is reported only after a start
               programmable offline mode DCB.
    Bit 10     Command list not stored. No command
               list is stored.
    Bit 11     Operation length exceeded. The
               programmable offline mode operation
               length (designated by word 1) was
               ecxceeded.
    Bit 12     Offline debug mode. The offline
               debug mode is on.
    Bit 13     Interface overrun control sync
               loss. Interface request overrun
               caused a loss of control synchron-
               ization.
               Note: This bit is always reported
               as a 0.
    Bit 14     Device ready state. The inverse of
               the current device ready state (0 =
               ready, 1 = not ready). This bit
               is reported only after a load
               programmable offline mode DCB.
    Bit 15     Device status. The state of the de-
               vice status line on the interface.
    ______________________________________

    ______________________________________
    Transfer  Device I/O register
                               S0      S1  S2
    ______________________________________
    Word 0    Bits 0-15 (bytes 0-1)
                               0       0   0
    Word 1    Bits 16-31 (bytes 2-3)
                               0       0   1
    Word 2    Bits 32-47 (bytes 4-5)
                               0       1   0
    Word 3    Bits 48-63 (bytes 6-7)
                               0       1   1
    Word 4    Bits 64-79 (bytes 8-9)
                               1       0   0
    Word 5    Bits 80-95 (bytes 10-11)
                               1       0   1
    Word 6    Bits 96-111 (bytes 12-13)
                               1       1   0
    Word 7    Bits 112-127 (bytes 14-15)
                               1       1   1
    ______________________________________

    ______________________________________
    Transfer        Input/Output register
    ______________________________________
    Word 0          Bits 128-143 (bytes 0-1)
    Word 1          Bits 144-159 (bytes 2-3)
    Word 2          Bits 160-175 (bytes 4-5)
    Word 3          Bits 176-191 (bytes 6-7)
    Word 4          Bits 192-207 (bytes 8-9)
    Word 5          Bits 208-223 (bytes 10-11)
    Word 6          Bits 224-239 (bytes 12-13)
    Word 7          Bits 240-255 (bytes 14-15)
    ______________________________________

    ______________________________________
    Bit 8       Read/Write (Data direction is with
                reference to the attachment).
                This bit is a 0 when:
                . Data is transferred to the attach-
                ment from the device (operation
                type A)
                . Data is transferred to the attach-
                ment from host storage (operation
                type D).
    Bit 9       Device/host
                This bit is a 0 when data is transferred
                with the device.
                This bit is a 1 when data is transferred
                with the host.
    Bits 10-12  These bits determine the initial word
                to be transferred. They contain a value
                (0-7) defining word 0 through word 7.
                On device transfers, bits 10, 11, 12 are
                the initial subaddress S0, S1, and S2,
                respectively.
    Bits 13-15  These bits contain a value that is one
                less than the number of words to be
                transferred. For example:
                Bits 13, 14, 15 = 0,0,0 indicates
                only one word transfer.
                Bits 13, 14, 15 = 0,1,0 indicates
                three word transfers.
                Bits 13, 14, 15 = 1,1,1 indicates
                eight word transfers.
    ______________________________________

    ______________________________________
    Operation
    type       Data movement
    ______________________________________
    A or B     Copy an input register to an output register:
               Bit 8 is a 0 to copy a register.
               Bit 9 is a 0 for host-to-device; it is
               a 1 for device-to-host.
               Bits 10-12 are the initial word address
               in the input register.
               Bits 13-15 are a binary value that is
               one less than the number of words to
               be transferred.
    C or D     Transfer a block of data from the host to
               the device or from the device to the host:
               Bit 8 is a 1 to transfer data.
               Bit 9 is a 0 for host-to-device; it is
               a 1 for device-to-host.
               Bits 10-15 are a binary value that is
               one less than the number of words to
               be transferred.
    ______________________________________

    ______________________________________
    Command     Operation
    ______________________________________
    ADD         Adds the contents of the accumulator 0
                to the contents of the designated
                accumulator (Acc n).
    CLR         Resets the most-significant bit in the
                designated accumulator (ACC n) to 0.
    INV         Inverts the most-significant bit in the
                designated accumulator (ACC n).
    SROT(1)     Shifts or rotates the contents of the
                designated accumulator (Acc n). (Re-
                fer to the full description of this com-
                mand for coding details).
    XOR         Exclusive ORs the contents of the accu-
                mulator 0 with the contents of the
                designated accumulator (Acc n).
    ______________________________________

    ______________________________________
    ADD          110010AC  XXXXXXXX
                 or
                 110111AC  XXXXXXXX
    ______________________________________

    ______________________________________
    CLR          110100AC  XXXXXXXX
                 or
                 110101AC  XXXXXXXX
    ______________________________________

    ______________________________________
    INV          110000AC     XXXXXXXX
                 or
                 110001AC     XXXXXXXX
    ______________________________________

    ______________________________________
    Bits
    ______________________________________
    8 9       Shift/rotation
    0 0       Shift left. Set the carry/borrow/error flag
              if a 1 is shifted out at any time during the
              instruction. The flat is reset, otherwise.
    0 1       Shift right. Set the carry/borrow/error flag
              if a 1 is shifted out at any time during the
              instruction. The flag is reset, otherwise.
    1 0       Rotate left.
    1 1       Rotate Right.
    ______________________________________

    ______________________________________
    XOR          110110AC     XXXXXXXX
                 or
                 110111AC     XXXXXXXX
    ______________________________________

    ______________________________________
    RTN          111110XX     XXXXXXXX
                 or
                 111111XX     XXXXXXXX
    ______________________________________

    ______________________________________
    Hex Value
             Meaning
    ______________________________________
    0        No operation.
    1        Issue `reset` pulse on the device interface.
    2        Move the state of the `device status bit`
             line on the device interface to the most-
             significant bit position of the designated
             accumulator.
    3        Increment the special interface counter.
    4        Set the most-significant byte of the special
             interface counter from the designated accu-
             mulator.
    5        Read the least-significant byte of the special
             interface counter to the designated accumulator.
    6        Set the least-significant byte of the special
             interface counter from the designated accu-
             mulator.
    7        Reserved.
    8        Report an exception interrupt to the host.
    9        Report a device end interrupt to the host.
    A        Report an exception with attention interrupt
             to the host.
    B        Report a device end with attention inter-
             rupt to the host.
    C        Set the `last transfer` line on the device
             interface.
    D        Set the `command` line on the device inter-
             face.
    E        Set the `status` line on the device interface.
    F        Clear all device interface tags.
    ______________________________________

    ______________________________________
           Command
    Line   list code
    Number (hex)      Instruction      Purpose
    ______________________________________
    00     6900      LDIA     A1   A1 = 0  Set-up
    01     5900      PARB          A1 .fwdarw. RO
                                           table
    02     6901      LDIA          AL = 1  .dwnarw.
    03     5901      PARB          A1 .fwdarw. R1
                                           .dwnarw.
    04     6902      LDIA          A1 = 2  .dwnarw.
    05     5902      PARB          A1 .fwdarw. R2
                                           .dwnarw.
    06     6903      LDIA          A1 = 3  .dwnarw.
    07     5903      PARB          A1 .fwdarw. R3
                                           .dwnarw.
    08     6904      LDIA          A1 = 4  .dwnarw.
    09     5904      PARB          A1 .fwdarw. R4
                                           .dwnarw.
    OA     6905      LDIA          A1 = 5  .dwnarw.
    OB     5905      PARB          A1 .fwdarw. R5
                                           .dwnarw.
    OC     6906      LDIA          A1 = 6  .dwnarw.
    OD     5906      PARB          A1 .fwdarw. R6
                                           .dwnarw.
    OE     6907      LDIA          A1 = 7  .dwnarw.
    OF     5907      PARB          A1 .fwdarw. R7
                                           .dwnarw.
    10     6908      LDIA          A1 = 8  .dwnarw.
    11     5908      PARB          A1 .fwdarw. R8
                                           .dwnarw.
    12     6909      LDIA          A1 = 9  .dwnarw.
    13     5909      PARB          A1 .fwdarw. R9
                                           .dwnarw.
    14     6910      LDIA          A1 = 10 .dwnarw.
    15     590A      PARB          A1 .fwdarw. RA
                                           .dwnarw.
    16     6911      LDIA          A1 = 11 .dwnarw.
    17     590B      PARB          A1 .fwdarw. RB
                                           .dwnarw.
    18     6912      LDIA          A1 = 12 .dwnarw.
    19     590C      PARB          A1 .fwdarw. RC
                                           .dwnarw.
    1A     6913      LDIA          A1 = 13 .dwnarw.
    1B     590D      PARB          A1 .fwdarw. RD
                                           .dwnarw.
    1C     6914      LDIA          A1 = 14 .dwnarw.
    1D     590E      PARB          A1 .fwdarw. RE
                                           .dwnarw.
    1E     6915      LDIA          A1 = 15 set-up
    1F     590F      PARB          A1 .fwdarw. RF
                                           table
    20     E040      DIDO     From host; first
                                         Input from
                              word, first posi-
                                         host
                              tion       .dwnarw.
    21     6900      LDIA     A1 = 0     .dwnarw.
    22     0911      GOBB     A1 .sym. 11 (host
                                         .dwnarw.
                              input register,
                                         .dwnarw.
                              least-significant
                                         .dwnarw.
                              byte) = A  .dwnarw.
    23     5920      PARB     A1 .fwdarw. R20
                                         Convert
    24     6900      LDIA     A1 = 0     .dwnarw.
    25     2D20      GORBI    A1 .sym. with
                                         .dwnarw.
                              register pointed to
                                         .dwnarw.
                              by R20 = A1
                                         .dwnarw.
    26     4900      PABB     A1 .fwdarw. 00 (device
                                         Output to
                              output register)
                                         device
    27     E080      DIDO     To device: first
                                         .dwnarw.
                              word, first
                                         .dwnarw.
                              position Device
                                         .dwnarw.
    28     7809      STIT     end interrupt
                                         .dwnarw.
    ______________________________________