System for resisting interception of information5253296Abstract A time segment scrambling information encoding and decoding system wherein a multiplicity of scrambling algorithms are stored in a memory such as a ROM for use during transmission via a chosen medium and a multiplicity of correlated unscrambling algorithms are stored in memory for use during reception, the transmission equipment including apparatus which at different times substantially selects one of the scrambling algorithms to rely on in transmission until a different one of the scrambling algorithms is selected, the signals transmitted to receiving apparatus including finite-duration transmission of coordinating signal components by which the receiving and descrambling apparatus is caused to choose and rely on the coordinate algorithm there stored and to keep its restorative time-shifting of segments coordinated with the arrival of the time-shifted segments produced by the algorithm then being relied on at the transmitting point. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 1
______________________________________
Element
Item IC Type Source
______________________________________
21 Oscillator CD4069U RCA
43 "
27 Counter CD4040 RCA
33 Latch CD4042 RCA
42 "
47 "
31 Debounce R-C Integrator
or CMOS
buffer with
feedback
37 Dual one-of- CD4555 RCA
four decoder
23 Multitone CD22859 RCA
Generator
35 Multitone CD4098 RCA
Duration one-shot
25 Multitone SSI202 Radio Shack
Detector
41 "
______________________________________
Timing diagram (FIG. 2) shows the timing relationship between the various elements of the signalling system: The top line (A) of the timing diagram (FIG. 2) illustrates the action of push-to-talk switch 29 (FIG. 1). Until this switch is closed, the system remains in the standby mode. When push-to-talk switch 29 (FIG. 1) is closed, the system enters the transmit mode and remains in the transmit mode until push-to-talk switch 29 (FIG. 1) is released. The second line (B) of the timing diagram (FIG. 2) represents the output of multitone duration control circuit 35 (FIG. 1). It should be noted that there is no delay of concern (a few nanoseconds) in debounce circuit 31 (FIG. 1) or latch 33 (FIG. 1). The third line (C) of the timing diagram (FIG. 2) shows a signal envelope representing the transmitted multitone signal. Since there is negligible delay in the multitone generator circuits, the starting and ending of the dual tone envelope is shown coincident with the enabling pulse from multitone duration one-shot 35 (FIG. 1). The fourth line (D) of FIG. 2 represents the occurrence of the data outputs of multitone detector 25 (FIG. 1). The time of occurrence of the data-valid signal is delayed (approximately 45 milliseconds) with respect to the initiation of the received multitone signal. Also, the cessation of the data-valid signal is delayed (45 milliseconds) with respect to the end of transmission of the multitone signal. Four bits of information recovered from the received multitone signal appear at the data outputs of multitone detector 25 approximately 7 microseconds before the appearance of the data-valid signal output of multitone detector 25 (FIG. 1). The delayed timing of the data-valid signal relative to the appearance of the data outputs is shown by line (E) of timing diagram (FIG. 2). The four recovered data bits are stored in latch 42 throughout the transmission. The extension of the transmit interval after release of push-to-talk switch 29 (FIG. 1) is illustrated by waveform (G) (FIG. 2). In the receive portion of the signalling system (FIG. 1), the system is in the "standby" mode until such time as a valid multitone signal is received. Upon arrival of a valid multitone signal, (line C, FIG. 2) the receiving process is initiated. The appearance of the data-valid signal is delayed (45 milliseconds) with respect to the time of arrival of the valid multitone signal. The data-valid signal places the signal processing counters in the reset mode and disables the signal selector switches in the receiver. During the data-valid signal interval, the four bits representing the decoded multitone signal are stored in receiver latch 47 (FIG. 1) for application to the address inputs of read-only memory 49 (FIG. 4). At the end of the data-valid signal, the reset is removed from the signal processing counters and the signal selector switches are enabled. The time of the start of processing message information with respect to the trailing edge of the multitone signal is the same in the transmitter and the receiver; hence, the operation of the two units is synchronized. In the preferred system (the analog system) of privacy communication, whether between plural transceivers or between a transmitter and one or more receivers, there is preferably provided at the transmitting point a delay line consisting of a series of switched-capacitor delay elements (also known as "Charge Coupled Devices" or "Bucket Brigade Devices") to divide the incoming signal into discrete segments having durations of approximately one-eighth second. These segments are rearranged in a controlled manner to obscure the intelligence contained in the transmitted message signal. The preferred system requires minimal components for implementation. The following paragraphs provide a detailed description of the operation of the analog transmitter (FIG. 3). The analog transmitter accepts an intelligence signal from an information source [for example, speech output from a microphone (with or without amplification)], processes the signal to suit the transmission medium, rearranges the segments of information into one of numerous predetermined random patterns, and feeds the resulting signal to the transmission medium. The block diagram of the analog transmitter FIG. 3), heretofore referred to, will be further explained. Part of the analog transmitter is the signalling system discussed in a previous section of this disclosure. The information to be transmitted is fed to input signal processor 20 (FIG. 3) where the input signal level is set and is filtered to remove any out-of-band components. Also, protective devices may be incorporated to protect the transmitter from high voltage noise on the input line. From input signal processor 20 (FIG. 3), the signal is fed into a delay line comprising a series of discrete delay elements 15 collectively denoted 24 (FIG. 3). The delay system 24 (FIG. 3) propagates the input signal therethrough in a period determined by the number of delay elements in the circuit path and the delay element clock rate. The operation of a delay element 15 can be visualized as a series of sampling circuits (approximately 2000 per delay element) wherein the instantaneous voltage present at the input of a sampling circuit is sampled and transferred to the next sampling circuit of the element on the following clock cycle. This process continues until the first sample is passed to the output of the delay element. As this first sample was passed along the sampling circuits of delay element 15, the next level present at the input of delay element 15 was sampled and started on the path through a delay element 15. In this manner, a sine wave fed into the input of delay system 24 would appear at the output of delay system 24 as a series of voltage samples following the input sine waveform and delayed with respect to the input waveform. In one example, the clock rate and the number of stages in the delay element 15 were chosen to yield a delay of approximately 146 milliseconds per element; hence, the delay through such a seven element delay system would be 1.022 seconds. Oscillator 21 was discussed in detail in the section describing the operation of the signalling system. Free-running counter 27 provides several outputs essential to the operation of the transmitter as discussed in the following paragraphs: The bits present at the four least significant outputs of free-running counter 27 at the time of closure of push-to-talk switch 29 are stored in latch 33 (FIG. 1) and define the random number which determines the algorithm for rearranging the segments of the message. A divide-by-256 output of counter 27 (FIG. 3) is the clock signal for segment duration counter 22. This output is further divided to produce a 6.8 Hz segment rate. A divide-by-512 output of free-running counter 27 serves as the clock for delay system 24. The output of segment duration counter 22 serves as the clock for up/down counter 26. The up/down control of counter 26 (FIG. 3) follows an output of read-only memory 34. A data bit at every memory location in read-only memory 34 instructs up/down counter 26 to count up or to count down. If this bit is a zero, up/down counter 26 will be incremented by each clock pulse from the address pointed to by the four bits recovered from the transmitted multitone signal. If this bit is a one, up/down counter 26 will be decremented by each clock pulse from the address pointed to by the four bits recovered from the transmitted multitone signal. The data processing counters (segment duration counter 22 and up/down counter 26) are held in reset by the data-valid output of multitone detector 25. Action of the transmission gates, units 38, is inhibited until inhibit flip flop 36 is set. Since the first information to be transmitted is coincident with the trailing edge of the data-valid signal, removing the inhibit on the action of transmission gates unit 38 by setting inhibit flip flop 36 with the trailing edge of the data-valid signal establishes synchronism of the transmitted message signal with the data-valid signal. At the end of the message [signalled by the release of push-to-talk switch 29 (FIG. 3)] transmission must continue until all of the information stored in delay system 24 has been transmitted. The delay in the ending of the transmission interval is accomplished by using the positive-going trailing edge of the push-to-talk switch signal to trigger end-of-message delay 30 (FIG. 3). At the termination of the end-of-message interval (approximately 1.3 seconds), inhibit flip flop 36 (FIG. 3) is reset and the transmission is terminated. At the end of the data-valid signal interval, up/down counter 26 (FIG. 3) will start from 000 (the reset output of the counter); therefore, the starting address for read-only memory 34 will be determined by the four data bits recovered from the transmitted multitone signal. If it is desired to repeat a particular sequence of segments, the instruction to count up or count down would be repeated at each of the eight addresses (000 through 111). Read-only memory 34 (FIG. 3) is programmed so that the three binary bits appearing at its least significant data outputs (D.sub.0, D.sub.1, D.sub.2) select the input of the first delay element of delay system 24 or the output of one of the several delay elements of said delay system 24. The sequence in which the outputs of the several delay elements are selected is determined by the scrambling algorithm selected for the particular transmission. The three data outputs of read-only memory 34 are connected to the data inputs of one-of-eight decoder 18. Only one output of one-of-eight decoder 18 goes high in response to any combination of ones and zeros applied to the data inputs of one-of-eight decoder 18. The eight outputs of delay line 24 are connected to the corresponding inputs of the respective transmission gate 38 (FIG. 3). The outputs of the eight transmission gates 38 are tied together to form a common path for the scrambled output signal. The common output of the transmission gates is fed to the input of output signal processor 11 (FIG. 3). The eight outputs of one-of-eight decoder 18 are connected in order (output one of one-of-eight decoder 18 is connected to the gate element of the transmission gate 38 whose input is connected to the input of the first delay element of delay system 24, and so on). With this arrangement, the segments of the message are delivered to output signal processor 11 in the order prescribed by read-only memory 34. Output signal processor 11 incorporates a low pass filter to eliminate any clock noise present in the signal. Provision is made for setting the level of the signal fed to line driver 13. Line driver 13 conditions the signal to meet the requirement for transmission of the signal via the selected transmission medium. Table 2 identifies examples of elements such as integrated circuit units which may be used in the block diagram functions of the analog transmitter FIG. 3.
TABLE 2
______________________________________
Element Item Source
______________________________________
Type
20 Input Signal TL082 Texas Instruments
Processor
11 Output Signal "
Processor
13 Line Driver "
15 Delay Element MN3008 Panasonic
21 Oscillator CD4069U RCA
27 Free-running CD4040 RCA
Counter
22 Segment Duration
CD4040 RCA
Counter
26 Up/down Counter
CD4516 RCA
34 Read-only memory
2716 National
Semiconductor
38 Transmission CD4066 RCA
Gates
18 One-of-eight 1-CD4555 RCA
Decoder 1-CD4556 RCA
30 Delay One-shot
CD4098 RCA
36 Inhibit Flip-flop
CD4013 RCA
Additional suitable parts relative to FIG. 1
IC Type
23 Multitone CD22895 RCA
Generator
33 Quad Latch CD4508 RCA
42 "
47 "
37 Dual-binary CD4555 RCA
One-of-four
Decoder
25 Multitone CD22204 RCA
Detector
41 "
______________________________________
The analog receiver (FIG. 4) accepts the signal arriving via the transmission medium, rearranges the scrambled segments of information into the original sequence and processes the recovered intelligence signal for presentation to the user. A necessary part of the analog receiver is the previously discussed signalling system. The information received from the transmission system is fed to input signal processor 127 where the level of the signal is set and the signal is filtered to remove any out-of-band components. Also, protective devices may be incorporated in input signal processor 127 to protect the receiver from high level noise spikes induced into the transmission system. From input signal processor 127, the signal is fed into a set of transmission gates 129 which control the point along delay system 128 (a series of delay elements) at which a particular message segment enters the signal recovery system. The output of input signal processor 127 is fed to multitone detector 41 where the four bits determining the message segment sequence and the data-valid signal are recovered. The output of input signal processor 127 is also fed to signal present detector 138 which is enabled by the trailing edge of the data-valid signal. Signal-present detector 138 maintains a high level output as long as a signal is being received. At the termination of the input signal, the shift in level at the output of signal present detector 138 triggers end-of-message delay one-shot 139 which delays the reset of inhibit flip flop 140 for approximately 1.3 seconds after the last message information is received. This period is sufficiently long for the last received segment of information to be processed through the system. The outputs of one-of-eight decoder 130 are held at zero (0) as long as the inhibit is active (high level). This means that none of the transmission gates of unit 129 will pass data while the inhibit is in effect. Inhibit flip flop 140 is set by the trailing edge of the data-valid signal. In this mode, transmission gates 129 will follow the instructions of read-only memory 49. The output of oscillator 43 (3.579545 MHz) is present at all times power is on. This signal is divided-by-eight and is fed to multitone detector 41 where it is utilized in the detection and decoding of the multitone signal arriving via the transmission medium. The multitone signal must persist for a minimum of 45 milliseconds to be considered valid. The output of oscillator 43 is also fed to free-running counter 135. The divide-by-512 output of free-running counter 135 is the clock for delay elements 128. The divide-by-256 output of free-running counter 135 is the clock for segment duration counter 151. The occurrence of the data-valid signal places segment duration counter 151 and up/down counter 53 in reset. These counters remain in reset [each presenting a low logic level (0) at its output] as long as the data-valid signal persists. At the same time the reset is applied to segment duration counter 151 and up/down counter 53, the four bits representing the received multitone signal are applied to the address inputs (A.sub.6 through A.sub.9) of read-only memory 49. The three least significant bits at the output of up/down counter 53 are applied to the three least significant address inputs (A.sub.0, A.sub.1, A.sub.2) of read-only memory 49. Remembering that up/down counter 53 is held in reset by the data-valid signal, it is recognized that the information appearing at the data outputs of read-only memory 49 is determined by the four bits recovered from the received multitone signal. The three least significant data bits at the output of read-only memory 49 are applied to the data inputs of one-of-eight decoder 130 and a fourth output of read-only memory 49 is applied to the up/down control of up/down counter 53. When the reset is removed from segment duration counter 151 and up/down counter 53, inhibit flip flop 140 is set. Setting inhibit flip flop 140 removes the inhibit from transmission gates 129 so that transmission gates 129 will follow the instructions appearing at the data outputs of read-only memory 49. This instant coincides with the arrival of the first segment of information from the transmitter. While segment duration counter 151 is timing the duration of the first segment (approximately 146 milliseconds), the first segment of data is fed into delay system 128 at its left-hand end or at an intermediate point therealong as determined by the four bits recovered from decoding the multitone message preamble. Since the instruction at each particular address in read-only memory 49 is the descrambling complement of the scrambling algorithm at the same address in read-only memory 34 in the transmitter (FIG. 3), the incoming segments of information will be transposed to the order in which they arrived at input signal processor 20 of the transmitter (FIG. 3). The output of delay system 128 is fed to output signal processor 55. Output signal processor 55 sets the level of the output signal and removes any sampling noise added to the signal as it was processed through delay system 128. The speaker or display 133 transforms the electrical signal from the output of signal processor 55 to an audible or visible form as required by the application. Table 3 sets forth examples of parts useable in the construction of an analog receiver:
TABLE 3
______________________________________
Element Title IC Type Source
______________________________________
127 Input Signal TL082 Texas Instruments
Processor
55 Output Signal "
Processor
128 Delay System MN3008 Panasonic
43 Oscillator CD4069U RCA
135 Free-running CD4040 RCA
Counter
151 Segment Duration
"
Counter
53 Up/Down counter
CD4516 RCA
49 Read-only Memory
2716 National
Semiconductor
129 Transmission Gates
CD4066 RCA
130 One-of-eight 1-CD4555 RCA
Decoder 1-CD4556 RCA
41 Multitone Detector
CD22204 RCA
47 Quad Latch CD4508 RCA
______________________________________
There are many components and functions which are identical in the above described analog transmitter and analog receiver. FIG. 5 and FIG. 6 present an analog signalling system and an analog transceiver, respectively, which substantially reduces the duplication of components and functions, while retaining the full capability of the separate transmitter and receiver, to the extent that the latter may be used for communication to and from a given position or a given vehicle. The switch sections (S.sub.1 through S.sub.5) of push-to-talk switch 61 (FIGS. 5 and 6) are shown in the receive position. Each of these switch sections is moved to its alternate position when the system enters the transmit mode. Also, when power is turned on or the system leaves the transmit mode, the system automatically returns to the receive mode. Operation of the system in the transmit mode is discussed in the following paragraphs. As noted above, when system power is turned on, the system automatically enters the receive mode. In this mode (as in the transmit mode) oscillator 107 is operative and supplies the reference frequency (3.579545 MHz). The clock signals for free-running counter 108, multitone generator 100 and multitone detector 114 are derived from the output of oscillator 107. Several other control signals are derived from the outputs of these devices. When push-to-talk switch 61 (including section S.sub.1) is closed for transmitting a message, the level at the input to debounce circuit 71 changes from a high level (+5 volts) to a low level (0 volts). Any perturbation of the signal at the input to debounce circuit 71 is removed. The control level at the output of debounce circuit 71 performs several functions as follows: Transmit/receive flip flop 116 is set (that is, the Q output is at a high level and the Q output is at a low level). The four bits appearing at the least significant outputs of free-running counter 108 at the instant of closure of push-to-talk switch 61 are stored in latch 102. Multitone Duration one shot 103 is triggered by the negative-going edge at the output of debounce circuit 71. This is the opposite of the action of extension one-shot 105 which triggers on the positive-going edge at the output of debounce circuit 71. This choice of triggers configures the circuit so that multitone duration flip flop 103 (FIG. 6) triggers when push-to-talk switch 61 is closed and extension one shot 105 (FIG. 6) is triggered when push-to-talk switch 61 opens. The control T line enables transmit read-only memory 111. This very simple memory control system is possible since the read-only memory selected for this application has a tri-state output which, when read-only memory 111 is not selected, presents a high impedance to the data bus. When control T is active, the information appearing at the data outputs of transmit read-only memory 111 are present on the data lines. (Via the enable function in the receive read-only memory 112, control R line serves the same purpose in the receive mode as the control T line serves in the transmit mode). All switch sections (S.sub.1 through S.sub.5) are transferred to the transmit position. Transmit read-only memory 111 is enabled. The four bits stored in latch 102 are fed to the inputs of dual-one-of-four decoder 101. The two least-significant bits stored in latch 102 are decoded by dual-one-of-four decoder 101 and the decoded output is applied to the row inputs of multitone generator 100. In like manner, the two most-significant bits at the output of latch 102 are decoded and the decoded output is appled to the column inputs of multitone generator 100. During the active interval of multitone duration one-shot 103 (approximately 0.2 second) multitone generator 100 produces a multitone signal at its output. The frequencies of the multitone signals are determined by the four bits stored in latch 102. These tones are fed to multitone detector 114 via output signal processor 115 and section S.sub.4 of push-to-talk switch 61. After the multitone signal has been present at the input of multitone detector 114 and successfully decoded for approximately 45 milliseconds, a set of four bits identical to those stored in latch 102 will appear at the data outputs of multitone detector 114. Approximately 7 microseconds after the appearance of these four bits, a data-valid signal will appear at the data-valid output of multitone detector 114. It should be repeated that the data-valid signal and the four bits persist at the outputs of multitone detector 114 for approximately 45 milliseconds after the end of the multitone signal. The data-valid output of multitone detector 114 is used as follows: The leading edge of the data-valid signal strobes latch 113 to store the four data bits present at the output of multitone detector 114. These bits will remain stored in latch 113 until another valid multitone signal is received or system power is turned off. The data-valid signal is used as a reset for segment duration counter 109 and up/down counter 110. The inverted trailing edge of the data-valid signal sets inhibit flip flop 106 so that one-of-eight decoder 99 is enabled. The simultaneous removal of the reset on the counters and the enabling of one-of-eight decoder 99 synchronizes the start of transmission with the ending of the data-valid signal. The four bits stored in latch 113 are applied to the address inputs of both the receive and the transmit read-only memories. However, since the transceiver is in the transmit mode, only the output of transmit read-only memory 111 will appear on the data bus. During the period of the data-valid signal, segment duration counter 109 and up/down counter 110 are held in reset. Under these conditions, the outputs of both counters will be zero. Hence, the first segment to be selected for transmission will be the one pointed to by the four bits obtained by decoding the transmitted multitone signal. One output of the read-only memories is designated (D.sub.c) to control up/down counter 110 and is connected to the up/down control of counter 110. This bit is a part of the data stored at each particular address and determines whether up/down counter 110 will be incremented or decremented at the end of each segment of transmitted data. In response to the information stored in transmit read-only memory 111, each group of seven segments of a particular message will be transmitted in a predetermined sequence. If the duration of the message is greater than one second, the sequence of segments in the second and succeeding groups will be repeated. The start of the message signal enters the first section of delay system 97 via switch S.sub.2. This first segment of the message may be selected by transmission gates 98 to be the first segment transmitted or it may be propagated through delay system 97 and selected at a later time. Each of the elements of delay system 97 introduces a delay of approximately 146 milliseconds. The process continues as each segment of a one second message is selected in the sequence specified by the information stored in transmit read-only memory 111. When the end of a particular message is signalled by the release of push-to-talk switch 61, it is highly probable that some information will remain in delay system 97. The release of push-to-talk switch 61 triggers extension one-shot 105. This one-shot delays the reset of transmit/receive one-shot 116 for approximately 1.3 seconds (1.3 seconds is more than enough time to guarantee that transmission of a particular message is complete). The transceiver leaves the transmit mode and enters the receive mode when extension flip flop 105 times out and transmit/receive flip flop 116 is reset. Referring to FIG. 6, the block diagram of the analog transceiver, will be of help in understanding the following paragraphs describing the operation of the analog transceiver in the receive mode. When system power is turned on, the system automatically enters the receive mode. Under these conditions: Oscillator 107 commences generating the reference signal (3.579545 MHz) from which the clock signals for all of the circuits are derived. All of the switch sections (S.sub.1 through S.sub.5) are placed in the receive position. The system will remain in the receive mode until push-to-talk switch 61 is closed or system power is turned off. The system will remain in what is, effectively, a standby mode until a valid multitone signal is received and recognized. Nothing will pass through transmission gates 98 (One-of-eight decoder 99 being disabled) until a data-valid signal appears at the output of multitone detector 114. All incoming signals are passed through input signal processor 96. In this unit, the signals are fed through a low pass filter to remove any out-of-band components, the signal level is set, and any voltage spikes are removed. The output of input signal processor 96 feeds the input of the first selected one of the transmission gates 98 via switch section S.sub.2, and the input of multitone detector 114 via switch sections S.sub.3 and S.sub.4. When a valid multitone signal is received, multitone detector 114 measures the duration of the multitone signal and if the duration is greater than 45 milliseconds, four bits representing the particular multitone signal will appear at the output of multitone detector 114. Approximately 7 microseconds after the appearance of the four bits at the output of multitone detector 114, a data-valid signal will appear at an output of multitone detector 114. The data-valid signal is applied as a reset to segment duration counter 109 and up/down counter 110. The leading edge of the data-valid signal is applied as a trigger to latch 113 where it causes the four data bits at the output of multitone detector 114 to be stored in latch 113. These four bits will remain in latch 113 until another valid multitone signal is received or system power is turned off. The four bits recovered from the received multitone signal are fed to the address inputs of transmit read-only memory 111 and receive read-only memory 112. Only receive read-only memory 112 will recognize the presence of the four address bits. This results from the fact that in the receive mode receive/transmit flip flop 116 is reset; hence, transmit read-only memory 111 is disabled and receive read-only memory 112 is enabled. Three data bits and a control bit (D.sub.c) appear at the data outputs of receive read-only memory 112. Since segment counter 109 and up/down counter 110 are held in reset by the data-valid signal, the information specifying where the first received message segment is to be fed into the set of delay elements 97 is determined by the four bits obtained by decoding the incoming multitone signal. The three data bits appearing at the output of receive read-only memory 112 are applied to the inputs of one-of-eight decoder 99. This decoder produces a high level at one, and only one, of its eight outputs in response to the information from receive read-only memory 112. The high level at the input of the selected one of transmission gates 98 causes the incoming signal to enter the series of delay elements 97 at the point specified by read-only memory 112. When segment duration counter 109 reaches a count of 1024 (approximately 146 milliseconds after the beginning of the segment) up/down counter 110 is clocked. This counter will be incremented or decremented in response to the information present at up/down counter 110's control input. The direction of the count (increment or decrement) is determined by the control bit present at the D.sub.c output of receive read-only memory 112. Of course, the instruction will be proper to retranslate the incoming message. The retranslated message will be fed to a speaker or other transducer via output signal processor 115. This processor includes a low pass filter to eliminate sampling noise induced into the signal. Processor 115 also includes means for setting the level of the outgoing signal. Table 4 delineates examples of parts which may be used in the construction of an analog transceiver.
TABLE 4
______________________________________
Element
Title IC Type Source
______________________________________
96 Input Signal TL082 Texas Instruments
Processor
115 Output Signal "
Processor
97 Delay System MN3008 Panasonic
(Composed of 7
Delay Elements)
98 Transmission Gates
CD4066 RCA
99 One-of-eight 1-4555 RCA
Decoder 1-4556
100 Multitone Generator
CD22859 RCA
101 Dual one-of- CD4555 RCA
four Decoder
102 Dual Quad latch
CD4508 RCA
113 "
103 Duration One-shot
CD4098 RCA
105 Extension One-shot
"
71 Debounce RC
Integrator
or CMOS
buffer with
feedback
106 Signal Inhibit CD4013 RCA
Flip Flop
116 Transmit/receive
"
Flip Flop
107 Oscillator CD4069U RCA
108 Free-running CD4040 RCA
Counter
109 Segment Duration
" RCA
Counter
110 Up/down counter
CD4516 RCA
111 Read-only memory
2716 National
Semiconductor
112 "
114 Multitone SSI202 Radio Shack
Detector
______________________________________
DESCRIPTION OF AN ALTERNATE EMBODIMENT OF A PRIVACY TRANSMISSION SYSTEM A substantial difference between the preferred embodiment (analog system) and the alternate embodiment (digital system) of the present invention lies in the choice of the delay system wherein the segments of the message are held until they are selected for transmission. In the analog system, a delay line performs the storage function, and in the digital system, a solid state memory performs the storage function. In the digital system, the incoming message signal is converted to digital form and the data representing the message is stored in a solid state memory. The digital data is read out of memory in segments which have, for example, a duration of approximately one-eighth of a second. To minimize the bandwidth required to transmit the digitized message, the data read from memory is converted to analog form and is filtered to remove quantizing noise before transmission. The designation of the sequence in which the segments of information are read from memory is conveyed to the receiver by a multitone preamble to the transmitted message. A system of memory control logic for the digital transmitter, digital receiver, and digital transceiver is set forth in FIGS. 7, 7A, 7B and 7C. The active elements are designated by conventional symbology. Table No. 5, set forth below, provides an illustrative tabulation of available solid-state devices which may be used in constructing the memory control system from small scale integrated circuit devices. Certain portions of the memory control logic system will be referred to in the description of the operation of the transmitter, receiver, and transceiver of FIGS. 9, 10 and 11 respectively. These are followed by a more detailed description of the of the memory control logic system. Illustrative examples of components useable in the memory control logic are set forth below:
TABLE 5
______________________________________
Element Item IC Type
______________________________________
Source
301 D Flip Flop CD4013 RCA
308 "
314 "
326 "
335 "
355 "
358 "
359 "
371 "
389 "
392 "
317 S-R Flip Flop CD4044 RCA
324 "
340 "
342 "
345 "
374 "
376 "
382 "
302 2-input AND CD4081 RCA
316 "
320 "
323 "
334 "
351 "
352 "
353 "
356 "
364 "
365 "
377 "
384 "
387 "
390 "
394 "
396 "
398 2-input AND CD4081 RCA
303 Inverter CD4049 RCA
321 "
329 "
330 "
331 "
343 "
362 "
304 3-input AND CD4073 RCA
309 "
312 "
313 "
315 "
328 "
347 "
348 "
305 2-input OR CD4071 RCA
306 "
307 "
310 "
311 "
325 "
327 "
332 "
333 "
336 "
339 "
341 "
344 "
346 "
354 "
360 "
361 "
366 "
367 "
373 "
375 "
379 "
380 "
383 "
391 "
393 "
397 "
399 "
318 U/D Counter CD40193 RCA
319 One-shot CD4098 RCA
RCA
322 3-input OR CD4075 RCA
327 "
337 Decimal CD4017 RCA
Counter
357 "
372 "
338 2-input NAND CD4011 RCA
349 "
350 "
385 "
386 "
378 2-input NOR CD4001 RCA
381 "
395 "
______________________________________
It will be readily apparent to those skilled in the relevant technologies that large scale integrated circuits may be used to provide the functions of a multiplicity of small scale integrated circuits, thereby achieving greater compactness and simplicity of construction. Illustrative examples of available integrated circuits which may be used in constructing the transmitter, receiver and transceiver of FIGS. 9, 10 and 11, respectively, are set forth below in Tables 6, 7 and 8, respectively, and are followed by descriptions of the operation of the digital transmitter, the digital receiver, and the digital transceiver.
TABLE 6
______________________________________
Illustrative integrated circuits useable in the digital transmitter:
Element
Title IC Type Source
______________________________________
240 Push-to-talk -- --
switch
241 Input Signal TL082 Texas Instru-
Processor ments
246 Output Signal "
Processor
242 Analog to MAX150 Maxim Inte-
Digital Converter grated Products
244 Delay RC Delay
245 Digital to AD7224 Maxim Inte-
Analog Converter grated Products
247 Tone Duration CD4013 RCA
Flip Flop
272 Divide-by-two "
248 Multitone CD22859 RCA
Generator
249 Random Access CDM6264 RCA
Memory
250 "
251 Multitone SSI202 Radio Shack
Detector
252 Dual one-of- CD4555 RCA
four Decoder
253 Write address CD4040 RCA
Counter
260 Free-running "
Counter
254 Tri-state CD4503 RCA
Buffer
255 "
256 Read Address CD40193 RCA
Counter
257 Dual Quad CD4508 RCA
Latch
259 "
258 Programmable 2732 National
Read Only Memory Semiconductor
261 Oscillator CD4069U RCA
262 Memory Control Logic
(See Table 5)
263 Segment CD40163 RCA
Duration Counter
264 Segment "
Counter
265 2-input AND CD4081 RCA
266 2-input OR CD4071 RCA
267 3-input OR CD4075 RCA
273 "
274 Hex inverter CD4049 RCA
243 Hex Buffer CD4050 RCA
268 "
269 "
270 "
271 Divide-by- CD4068 RCA
223 CD4049
______________________________________
The following paragraphs describe the operation of the digital transmitter, the digital receiver, the digital transceiver and the memory control logic. Referring to FIG. 9, except where otherwise stated, when system power is turned "on", the various flip flops and counters in the digital transmitter of FIG. 9 assume random states. The system is initialized (the various flip flops, counters, etc. are forced into the required state) by a "power-up-reset pulse" generated from the positive-going edge of the logic power supply output. The "power-up-reset pulse" accomplishes the following: (a) Tone duration flip flop 247 is reset to preclude generation of extraneous tones at the time the transmitter is turned "on". (b) In memory control 262, flip flop 308 (FIG. 7) is set, designating that data will first be written into memory A 249. (c) The various flip flops and counters controlling the generation of write addresses (FIG. 7A), read addresses (FIG. 7B and 7C), segment duration counter 263, and segment counter 264 are all reset. When system power is turned "on" oscillator 261 starts generating a 3.579545 MHz signal. This signal is applied as a clock to free-running counter 260. It should be noted that free-running counter 260 is not reset by either the power-up-reset pulse or the data-valid pulse; hence, the pulses appearing at the four least significant bit outputs of free-running counter 260 at the instant of actuation of push-to-talk switch 240 are determined solely by the random timing of the switch closure. The four least-significant outputs of free-running counter 260 are applied to the inputs of latch/buffer 259. Several other control signals are derived by decoding the outputs of free-running counter 260: (a) The divide-by-four output serves as a clock for many functions in memory control logic 262. (b) The divide-by-eight output serves as a clock for multitone detector 251. (c) The output of free-running counter 260 is divided-by 223 by element 271 to produce a 3.579545/223 signal which is further divided-by-two in element 272 to produce a clock signal having a frequency of approximately 8 kHz. Still referring to FIG. 9, except where otherwise noted, closure of push-to-talk switch 240 generates a negative-going voltage edge. This edge is passed through debounce circuit 243 (a CMOS buffer with a suitable feedback resistor connected from its output to its input). Since the output of the buffer is of the same polarity as the applied voltage edge, any momentary bounce of the switch contacts (resulting in a series of voltage edges immediately after the original edge) will be ignored. The voltage edge at the output of debounce circuit 243 is inverted at 274 and is differentiated. The above mentioned pulse is delayed at 244 and causes the bits at the four least-significant outputs of free-running counter 260 to be stored in latch 259. Since write address counter 253 was reset by the power-up-reset pulse, and write clock is not applied to write address counter 253 until the closure of push-to-talk switch 240, the count 8192 output of write address counter 253 will be zero; hence, the tri-state buffer portion of latch 259 is enabled and the bits at the four least-significant outputs of free-running counter 260 will appear at the inputs of dual one-of-four decoder 252. The two least-significant bits at the output of tri-state buffer portion of latch 259 are decoded and the decoded output is applied to the row inputs of multitone generator 248. The two most-significant bits at the output of buffer 259 are decoded and the decoded output is applied to the column inputs of multitone generator 248. After a delay at 244 slightly greater than the propagation delay between setting latch 259 and the appearance of decoded signals at the row and column inputs of multitone generator 248 (thus assuring that the address inputs are settled), the pulse resulting from the closure of push-to-talk switch 240 sets tone duration flip flop 247. Immediately, multitone generator 248 produces a multitone signal whose frequencies are determined by the levels at the row and column inputs of multitone generator 248. The multitone signal described in the preceding paragraph is fed, via output signal processor 246, to the input of multitone detector 251. Approximately 45 milliseconds after closure of push-to-talk switch 240, a set of four pulses identical to those pulses applied to the row and column inputs of multitone generator 248 appear at the output of multitone detector 251. Approximately 7 microseconds after the appearance of the four pulses, a data-valid signal appears at a second output of multitone detector 251. The leading edge of the data-valid signal causes the four bits appearing at the output of multitone detector 251 to be stored in latch 257, and sets standby/active flip flop 301 (FIG. 7) in memory control 262 (FIG. 9), thus causing analog-to-digital converter 242 to be enabled. The leading edge of the data-valid signal is differentiated and the resulting pulse is applied as a reset to: Write Address counter 253, Read Address counter 256, Segment Duration counter 263, Segment counter 264, Divide-by-two 272 and Up/down counter 359 (FIG. 7C). The five last listed counters remain in reset until write address counter 253 reaches a count of 8192 (memory A is full and approximately one-second of the multitone signal has been sent to the receiver). Referring still to FIG. 9, except where otherwise noted, the leading edge of the data-valid signal sets in motion a series of steps in memory control 262 which causes 8 kHz write clock pulses to be fed to write address counter 253. Write address counter 253 is incremented by each write clock pulse. The outputs of write address counter 253 are connected to the data inputs of tri-state buffer 254. As was previously noted, memory control logic causes the first page (one second, 8192 bytes of data) to be written into memory A 249 beginning immediately after push-to-talk switch 240 is closed. When power to the digital transmitter is turned "on", input signal processor 241 begins to process the audio signal received from a microphone or other source. This signal is processed to remove noise spikes, the bandwidth of the incoming signal is limited to eliminate aliasing, and the amplitude of the signal is set to the level required at the input of analog-to-digital converter 242. Early in the write portion of the 8 kHz clock cycle, analog-to-digital converter 242 is instructed to sample the incoming audio signal and to convert that sample to an eight bit digital word. After a short delay to let the information at the address inputs of memory A 249 settle, the output of analog-to-digital converter 242 is stored in memory A 249 by the application of a WR command to the WR input (not shown in FIG. 9) of memory A 249. At the start of the next write portion of the 8 kHz clock cycle, the process is repeated and the digital word representing the next sample of the incoming audio is stored in the second address location of memory A 249. This process continues until information is written into all 8192 memory locations or push-to-talk switch 240 is released. Several things occur as a result of a count of 8192: (a) Write address counter 253 is reset (b) Tone duration flip flop 247 is reset; hence, the multitone signal informing the receiver of which scrambling algorithm is in use is terminated. (c) Write A/write B flip flop 308 (FIG. 7) in memory control 262 is toggled so that the next 8192 bytes of data will be stored in memory B 250. Read address counter 256, segment duration counter 263 and segment counter 264 are inactive until memory A 249 is filled (a count 8192 output is generated by write address counter 253). Read address counter 256 is set to the starting address in memory A 249 from which the first byte of data is to be read. The address in memory A from which the data is to be read is obtained from read-only memory 258 at the address pointed to by the four bits recovered from the multitone preamble to the message. As was previously mentioned, multitone detector 251 detects and decodes the multitone signal transmitted as a preamble to the message. These bits are stored in latch 257 from the time they are decoded until the end of the message is signalled by the release of push-to-talk switch 240. One bit of data stored at each address in read-only memory 258 is a control bit which determines whether read address counter 256 is to count up or count down from the starting address to read the first segment of data from memory A 249. In this simplest embodiment of the digital transmitter, read address counter 256 would count up or count down [as instructed by the control bit (D.sub.c) from the starting address specified in programmable read-only memory 258]. Segment duration counter 263 counts 1024 clock pulses (one segment duration) and advances segment counter 264. The new count at the output of segment counter 264 increments the address input to read-only memory 258 so that the next segment of data is read from the address in memory A 249 defined by the data at the newly specified address in read-only memory 258. As was the case in the first segment read out of memory, a control bit (D.sub.c) in read-only memory 258 at the newly specified address will cause the data in memory A 249 to be read out in the forward (count up) or reverse (count down) order. The above described process continues until eight segments have been read out of memory A 249. At this point, memory B 250 will have been filled so the system reconfigures itself to read the data stored in memory B 250 and to write data into memory A 249. The process of alternately writing into memory A 249 and then into memory B 250 while reading from the previously filled memory continues until push-to-talk switch 240 is released and all of the data stored in the memories has been transmitted. The output of digital-to-analog converter 245 is filtered to remove the quantizing noise in the reconstituted signal and to limit the bandwidth of the output signal to suit a voice-grade telephone circuit. Output signal processor 246 also has provision for setting the level of the output signal. Release of push-to-talk switch 240 generates a pulse which causes memory control 262 to stop the flow of clock pulses to write address counter 253 and to disable analog-to-digital converter 242. In memory control 262, up/down counter 318 (FIG. 7) is incremented when a byte of data is written into memory and is decremented when a byte of data is read from memory. The pulse occurring at the release of push-to-talk switch 240 modifies the logic in memory control 262 so that no further data (only amplifier noise would be present) is digitized and stored in memory. The generation of read addresses and transmission of data continues until the last segment (or partial segment) of data is transmitted. As each byte of data is read out of memory, the up/down counter in memory control 262 is decremented. The design of the selected up/down counter 318 (FIG. 7, RCA type CD40193) is such that when the count is 000--00, attempting a further count down results in the generation of a "borrow" signal. The "borrow" signal is inverted at 331 (FIG. 7) and enables AND gate 328 (FIG. 7). Since the system is in the transmit mode (T is high), the presence of a "borrow" signal and the fact that push-to-talk switch 240 is released causes the output of said AND gate 328 to go high, thereby triggering EOM (end-of-message) timer 319 (FIG. 7) which generates an end-of-message command having a duration of sixty milliseconds (60 ms). The leading edge of the end-of-message command is applied to the set input of tone duration flip flop 247 via OR gate 266 and delay 244 (all in FIG. 9) causing the generation of a multitone signal representing the digital word 0000. This signal informs the receiving station that all data of a particular message has been transmitted; hence, the receiver is commanded to leave the receive mode and to return to the "standby" mode. This signal is generated in the following manner: (a) Continuing in reference to FIG. 9, unless otherwise noted, the outputs of latch/buffer 259 are returned to ground by "pull-down" resistors (not shown in the diagram). (b) At a write address counter 253 count of 8192, the low level present at the enable input of the tri-state buffer portion of latch/buffer 259 is replaced by a high level and the output of tri-state buffer 259 is a high impedance for the remainder of the message transmission. (c) The leading edge of the EOM (end-of-message) signal sets tone duration flip flop 247 via OR gate 266 and delay 244. Setting tone duration flip flop 247 initiates the generation and transmission of a multitone signal signifying that all data constituting the particular message has been transmitted. It will be noted that the positive-going end-of-message pulse waveform is applied to the EN (enable) input of the tri-state buffer portion of latch/buffer 259 via OR gate 273 for the 60 millisecond duration of the end-of-message pulse thereby causing the output of latch/buffer 259 to present a high impedance (open circuit) to the inputs of dual one-of-four decoder 252. (d) Since the four inputs to dual one-of-four decoder 252 are returned to ground through pull-down resistors, the inputs to multitone generator 248 are 0000; hence, the transmitted multitone signal will represent 0000. (e) The inverted end-of-message signal present at the Q output of end-of-message timer 319 (FIG. 7) is applied to input of AND gate 265 (FIG. 9) thus blocking any action by the transmitter in response to the second data-valid signal. It should be noted that this circuit configuration does not preclude using 0000 to define a scrambling algorithm in normal system operation. (f) The end-of-message multitone signal is terminated by the TE EOM (trailing-edge end-of-message) signal from EOM timer 319 (FIG. 7) via OR gate 267. (g) At the termination of the end-of-message signal, the transmitter enters a "standby" mode and remains there until push-to-talk switch 240 is again depressed. It should be noted that during a pause in a message (push-to-talk switch 240 is held down but no words are spoken) the random sounds picked up by the microphone will be transmitted. The block diagram of the digital receiver (FIG. 10) presents the several functions performed in receiving and unscrambling a private digitized message. The following paragraphs describe the various functions which must be performed to recover a scrambled digital message. Proceeding in reference to FIG. 10, except where otherwise noted, a power-up-reset pulse is generated by differentiating the leading edge of the positive logic supply voltage. The power-up-reset pulse resets several flip flops in memory control 425. These flip flops inhibit operation of all counters other than free-running counter 423 by interrupting the flow of clock pulses to the counters. Oscillator 427 starts at the instant power is turned "on" and continues to generate Fc pulses until power is turned "off". Free-running counter 423 generates Fc/4 and FC/8 clock pulses without interruption during the interval power is supplied to the receiver. Input processor 401 processes all signals appearing at its input during the interval receiver power is "on". However, no data is processed by analog-to-digital converter 402 while the receiver is in the "standby" mode (awaiting the arrival of a valid multitone signal). Approximately 45 milliseconds after the appearance of a valid multitone signal at the input of multitone detector 407, a four bit digital word identical to the word applied to the data inputs of multitone generator 248 in the digital transmitter (FIG. 9) will appear at the data outputs of multitone detector 407 (FIG. 10). Approximately seven microseconds after the appearance of the recovered data bits, a data-valid signal will appear at an output of multitone detector 407. The data-valid signal is applied to one input of AND gate 420. AND gate 420 is enabled by the Q output of data-valid flip flop 410. It will be remembered that data-valid flip flop 410 was reset by the power-up reset pulse or reception of an end-of-message signal (the Q output of a reset flip flop is at a logic high). The positive-going leading edge of the data-valid pulse appearing at the output of AND gate 420 is differentiated and the resulting pulse performs the following functions: Resets write address counter 413, Resets read address counter 416, Resets segment duration counter 429, Resets segment counter 426, and Resets up/down flip flop 359 (FIG. 7B), Resets divide-by-two 418. It will be remembered that counters and flip flops come up in random states when power is applied to a digital system; hence, it is necessary to initialize the system (place all counters and flip flops in the required state) to begin operation. For this reason, the leading edge of the data-valid signal is applied to memory control 425. The leading edge of the data-valid signal is slightly delayed and performs the following functions in memory control 425: (A) Enables the flow of clock pulses to write address counter 413. It will be remembered that in the digital transmitter, the multitone signal was terminated and the transmission of data was begun when 8192 bytes of data had been written in memory A 249 (FIG. 9). (B) Inhibits the flow of control signals to analog-to-digital converter 402 (FIG. 10) so that no data is presented to the input of memory A 405 until 8192 write clock pulses have been counted by write address counter 413. (The end of this period coincides with the termination of the multitone preamble and the start of transmission of data from the digital transmitter). (C) Inhibits the flow of addresses and control pulses to memory A 405 and memory B 406. Occurrence of a count of 8192 by write address counter 413 initiates the following sequence of events: (a) Enables generation of the clock and control pulses required to convert the data present at the output of input signal processor 401 to digital form and to write the data into memory A 405. (b) Data is written into memory A 405 beginning at the lowest address (000 . . . 00) and incrementing the address one count for each byte of data written. As in the case of the digital transmitter, the 8 kHz clock cycle is divided into two equal periods to permit one write period and one read period during the 125 microsecond duration of each 8 kHz clock cycle. Upon occurrence of the first write period of the 8 kHz clock, data is written into the first address in memory A 405. [Fc/4 pulses (895 kHz) serve as a clock for several functions in memory control 425. Fc/8 serves as a clock for multitone detector 407]. When memory A 405 is filled (8192 bytes of data), memory control 425 causes the data representing the incoming signal to be written into memory B 406. During the next read period of the 8 kHz clock, reading of data from memory A 405 is initiated. During the following write period of the 8 kHz clock cycle, data representing the incoming signal is written into memory B 406. The process of writing data into memory B 406 and reading data from memory A 405 continues until memory B 406 is filled. Writing of data into one memory while reading data from the other memory continues for the duration of the incoming message. An up/down counter 318 (FIG. 7) in memory control 425 (FIG. 10) is incremented when a byte of data is written into memory and is decremented when a byte of information is read from memory; hence, reading of data from memory will continue for a maximum of one second after the last data is received. This system cannot be permitted to enter the "standby" mode when the last byte of data is read from memory but must remain in the "active" receive mode until an end-of-message command (a multitone signal designating 0000) has been received. This system constraint is provided as it is quite possible that the person using the system may pause for several seconds between utterances. Examination of the block diagram of the digital receiver (FIG. 10), reveals that the data-valid signal emanating from multitone detector 407 is inverted at 408 and is applied as a clock to data-valid flip flop 410. Since the data-valid signal is a positive-going pulse, the trailing edge of the inverted data-valid pulse sets said flip flop. Data-valid flip flop 410 is reset by the power-up-reset pulse or the trailing edge of an end-of-message signal. Therefore, AND gate 420 is enabled at the time of occurrence of a first data-valid pulse and passes the leading edge of that data-valid pulse. Since data-valid flip flop 410 was set by the trailing edge of the first data-valid pulse, AND gate 420 is disabled (the Q output of data-valid flip flop 410 is low); hence, a second data-valid signal, without an end-of-message signal having been previously received, will not initialize the system for reception of a message. This arrangement permits the use of the multitone signal representing 0000 as a message preamble as well as an end-of-message command. As was previously mentioned, the data representing the incoming signal is written into memory in the order in which it is received. Storage of data starts at address zero and write address counter 413 (FIG. 10) is incremented as each byte of data is written into memory. This organization of data dictates that the data be read from memory in an order prescribed by an unscrambling algorithm defined by the received multitone preamble of the current message. This algorithm will restore the scrambled message segments to the proper sequence. In the digital transmitter (FIG. 9), closure of push-to-talk switch 240 (FIG. 9) caused the bits present at the four least-significant outputs of free-running counter 260 (FIG. 9) to be stored in latch 259 (FIG. 9) and a pair of tones determined by these four bits were generated by multitone generator 247 (FIG. 9). This multitone signal was detected and decoded by multitone detector 251 (FIG. 9). The resulting four bit digital word was used to select a particular scrambling algorithm from transmit read-only memory 258 (FIG. 9). The above mentioned multitone signal was transmitted to the digital receiver (FIG. 10), and was detected and decoded by receiver multitone detector 407. Four bits, identical to those which programmed multitone generator 247 in the digital transmitter (FIG. 9), appear at the output of receiver's multitone detector 407 (FIG. 10). The leading edge of the accompanying data-valid signal at an output of multitone detector 407 (FIG. 10) causes these bits to be stored in latch 409. Continuing in reference to FIG. 10, except where otherwise noted, the four recovered data bits are applied to address inputs of read-only memory 417. Since segment counter 426 was reset by the leading edge of the data-valid signal via memory control logic 425 and OR gate 428, all zeros will appear at the data outputs of segment counter 426. These bits are connected to the three least-significant address inputs of read-only memory 417. The address in read-only memory 417 defining the starting address in memory A 405 from which the first byte of the first segment is to be read is defined by the four bits recovered from the received multitone signal. The data space at each address in read-only memory 417 is eight bits wide; however, only three of these bit locations are used as address information. A fourth bit at every address determines whether a segment is to be read in a forward direction (that is, the way the original segment of information was spoken) or in the reverse direction (that is, the reverse of the way in which the segment of information was spoken). To simplify system design, the following convention is chosen: 1=count down (read out the data in the particular segment in the reverse of the order in which the segment of information was spoken); 0=count up (read the data in the particular segment in the order in which it was spoken). In this simplest implementation of the system, segment duration counter 429 is incremented as each byte of data is read from memory. Segment duration counter 429 produces an output at a count of 1024 bytes thereby incrementing segment counter 426. Incrementing segment counter 426 advances the address input of read-only memory 417 to the address from which the next segment of data is to be read. Incrementing segment counter 426 continues until eight segments of data have been read from memory. When a count of eight is reached, the counter is reset, and counting is resumed. At the end of a message, or at a pause in the message, reading of data from memory continues until up/down counter 318 (FIG. 7) in memory control generates a "borrow" signal. This indicates that all data has been read from memory. Examination of the digital transceiver block diagram (FIG. 11) reveals that the transceiver includes apparatus identical to the transmitter with the addition of three single-pole, double-throw switches (S.sub.1, S.sub.2, and S.sub.3 which are controlled by push-to-talk switch 537 and may be mechanically ganged therewith), and the inclusion of the algorithms required for the recovery of the intelligence of the received scrambled message and the end-of-message processing circuitry of the digital receiver (FIG. 10). Referring to FIG. 11, (which comprises FIGS. 11A and 11B, taken together), except where otherwise indicated, the transceiver control logic is so arranged that when system power is turned "on" the system always enters the R (receive) mode. Depressing push-to-talk switch 537 causes the three switches (these switches may be solid-state or they may be implemented as contacts of relays) to enter the T (transmit) mode. In the R (receive) mode, the three switches perform the following functions: S.sub.1 selects the signal source designated "line in" in anticipation of receiving a message from a compatible privacy transmitter; All received signals are passed through input processor 501 to remove any voltage spikes which might damage the circuitry, remove any out-of-band signals and set the amplitude of the incoming signal at a level compatible with the requirements of A to D converter 502; S.sub.2 causes information from input signal processor 501 to be fed to the input of multitone detector 507; and S.sub.3 causes the signal from output signal processor 504 to be fed to an amplifier driving headphones or a speaker to convert the signal to an audible form. In the transmit (T) mode, the three switches perform the following functions: S.sub.1 causes the signal from the originating source, such as a microphone, to be fed to input signal processor 501; S.sub.2 selects the signal from multitone generator 514 as the input for multitone detector 507. A signal is present at the output of multitone generator 514 only during the one-second message preamble. S.sub.3 causes the signal developed by output processor 504 to be fed to a communication link via a "line driver". Continuing in reference to FIG. 11, except where otherwise noted, while in the receive mode, the presence of a valid multitone signal at the input of multitone detector 507 for at least 45 milliseconds causes four bits to appear at outputs of multitone detector 507 and after an additional 7 microseconds, a data-valid signal appears at a further output of multitone detector 507. The data-valid signal performs the following functions: The leading edge of the data-valid signal causes the four data-bits recovered from the transmitted multitone signal to be stored in quad latch 515. The leading edge of the data-valid signal is differentiated and the resulting pulse: Resets write address counter 519, Resets read address counter 522, Resets segment duration counter 532, Resets segment counter 530 and Resets divide-by-two 531. In memory control 529 [memory control being discussed more fully in a later section], various control flip flops are set by the leading edge of the data-valid pulse so that write clock pulses are fed to write address counter 519. Thus, measurement of the period from the time of arrival of the data-valid pulse to the start of transmission of scrambled data (8192 clock pulses, approximately one-second later) is facilitated. Since the transceiver is in the receive mode, data is not written into memory during this period as the flow of control pulses to memory A 505 is inhibited. At the end of the one-second message preamble, the incoming message signal is converted into eight-bit digital words by A to D converter 502 and is written into memory A 505 in the order in which the data is received, starting at memory location zero. When 8192 bytes of information have been written into memory A 505, write A/write B flip flop 308 (FIG. 7) in memory control 529 (FIG. 11) is toggled so that the next 8192 bytes of data are written into memory B 506. This write A/write/B sequence continues until all incoming data is written into memory. It will be recalled that the process leading to the writing of data into memory was started by the leading edge of the data-valid pulse at an output of multitone detector 507. The four data bits recovered from the multitone signal (identical to those determining the particular multitone signal transmitted as a message preamble) are stored in latch 515. The four bits are applied to address inputs (A.sub.8, A.sub.9, A.sub.10 and A.sub.11) of read-only memory 523. The three outputs of segment counter 530 are connected to the least significant address inputs of read-only memory 523. Since segment counter 530 was reset by the leading edge of the data-valid pulse and no clock pulses have been fed to segment counter 530, the three outputs will all be zero; Hence, the four bits recovered from the multitone signal transmitted as a preamble to the received scrambled message will determine the location in read-only memory 523 from which the starting address in memory A 505 for recovery of the first segment of data is to be read. The bytes of data stored at each address in read-only memory 523 are eight bits wide; however, only three of these bits are connected to the present inputs of read address counter 522. A fourth bit at every memory location defines the direction in which read address counter 522 will count. That is, if the fourth bit is a 1 (one) read address counter 522 will be decremented from the starting address by a read clock pulse. Similarly, if the fourth bit is a 0 (zero) read address counter 522 will be incremented by a read clock pulse. Segment duration counter 532 is incremented when a byte of data is read from memory and produces an output when 1024 bytes (one segment) of data have been read. This output clocks segment counter 530. The three data outputs of segment counter 530 are connected to the three least significant address inputs of read-only memory 523. Segment counter 530 generates an output signal when eight segments of information have been read from memory. This signal is used at the end of a transmission to continue reading data from memory until the last byte of data has been read. As each byte of data is read from memory, it is converted to analog form by digital-to-analog converter 503. Quantizing noise is removed from the recovered analog signal by a low-pass filter in output signal processor 504. Output signal processor 504 also amplifies the recovered signal to a level suitable for driving a speaker or a headset. It should be noted that in the present configuration, the transceiver system will remain in the receive mode until the last byte of data has been read from memory and an "end-of-message" multitone signal has been received. The system described automatically returns to the "standby" mode upon receipt of an end-of-message signal and completion of reading data stored in memory. Whether the transceiver is in the receive or standby mode, closure of push-to-talk switch 537 will cause the system to enter the transmit mode. Closure of push-to-talk switch 537 results in the following: (a) Switches S.sub.1, S.sub.2, and S.sub.3 are placed in the T (transmit) position; (b) The bits then present at the four least-significant outputs of free-running counter 527 are stored in latch 526; and (c) In memory control 529 the circuitry is reconfigured to afford a transmitting capability. Further, during the first second after closure of push-to-talk switch 537, the tri-state buffer portion of latch 526 is enabled; hence, the four bits stored in latch 526 appear as inputs to dual one-of-four decoder 518. One section of said dual one-of-four decoder 515 decodes the two least-significant bits from latch 526 and the decoded output is applied to the row inputs of multitone generator 514. The second section of dual one-of-four decoder 518 decodes the two most-significant bits from latch 526 and the decoded output is applied to the column inputs of multitone generator 514. A flip flop 324 (FIG. 7) in memory control 529 is set to place the system in the transmit mode. Continuing in reference to FIG. 11, except where otherwise noted, a delay at 512 slightly longer than the propagation delay through latch 526 and dual one-of-four decoder 518 is in the path of the pulse derived from the closure of push-to-talk switch 537. Hence, the bits present at the row and column inputs of multitone generator 514 will have settled before tone duration flip flop 509 is set by the pulse resulting from the closure of push-to-talk switch 537. Setting tone duration flip flop 509 enables multitone generator 514. The output of multitone generator 514 is a multitone signal defined by the four bits randomly latched at the four least-significant outputs of free-running counter 527. The resulting multitone signal is fed via switch S.sub.3 to the line driver where the signal is amplified and processed to suit the specifications of the transmission medium (radio link, telephone circuit, etc.). A sample of the transmitted multitone signal is fed to multitone detector 507 via switch S.sub.2. Approximately 45 milliseconds after the start of transmission of the multitone signal, four bits identical to those latched at the output of free-running counter 527 appear at the data outputs of multitone detector 507. Approximately 7 microseconds after the appearance of the data output, a data-valid signal appears at a further output of multitone detector 507 and causes the four bits to be stored in latch 515. The leading edge of the data-valid signal is differentiated and the resulting pulse: (a) Sets transmit/receive flip flop 324 (FIG. 7) in memory control 529 indicating that the system is to operate in the transmit mode; (b) Resets the following counters: Write address counter 519, Read address counter 522, Segment duration counter 532, Segment counter 530, Divide-by-two 531; and Up/down flip flop 359 (FIG. 7B); (c) Enables the flow of clock pulses to write address counter 519; and (d) Strobes the recovered data bits into latch 515. During the first second after recognition of a valid multitone signal, clock pulses are fed to write address counter, 519, A to D converter 502 is enabled and data is written into memory A 505. At the end of the first second of signal storage: (a) Transmission of the multitone signal is terminated. (b) Writing of data into memory B 506 is initiated and writing of data into memory A 505 is terminated. (c) The four bits of data stored in latch 515 are applied to address inputs of read-only memory 523. Data stored at the particular address in read-only memory 523 specifies the address in memory A 505 from which the first byte of the first segment of the message is to be read. The data stored at that particular address in read-only memory 523 also specifies whether read address counter 522 is to be incremented or decremented during the reading of the particular segment of the stored message. (d) The trailing edge of the data-valid pulse sets data-valid flip flop 511 via inverter 508. Upon completion of reading all of the data stored in memory A 505, reading of the data stored in memory B 506 is begun and writing of the next received data into memory A is started. The process of alternately writing data into and reading data from each of the two memories continues until push-to-talk switch 537 is released. The reading of data from memory continues after the release of push-to-talk switch 537 until memory control 529 signals that the last byte of data has been read from memory. When the last byte of data has been read from memory, memory control 529 generates an "end-of-message" pulse having a duration of 60 milliseconds. Since the system is in the transmit mode, the leading edge the "end-of-message" pulse generated by memory control logic 529 enables tone duration flip flop 509 via OR gate 513 and delay 512. Release of push-to-talk switch 537 also resets count 8192 flip flop 314 (FIG. 7) in memory control 529; hence, the tri-state buffer portion of latch 526 is enabled. However, the EOM (end-of-message) pulse 319 (FIG. 7) is applied to the EN (enable) input of tri-state buffer .phi. portion of latch 526 via OR gate 538 for the 60 millisecond duration of the EOM (end-of-message) pulse. Thus, the tri-state buffer portion of latch 526 remains disabled for the duration of the EOM command. Under these conditions, the output of the tri-state buffer portion of latch 526 is a high impedance. The inputs of dual one-of-four decoder 518 are returned to ground by pull-down resistors (not shown on the block diagram); hence, the output of multitone generator 514 will represent the digital word 0000. (the selected "end-of-message" signal). The "end-of-message" signal will be terminated by the trailing edge of the "end-of-message" pulse generated in memory control 529. Since the system was still in the transmit mode when the transmission of the "end-of-message" signal was initiated, the resulting multitone signal will be fed to multitone detector 507 via switch S.sub.2. Multitone detector 507 will recover four bits (0000) and a data-valid signal. As will be remembered, data-valid flip flop 511 was set by the trailing edge of the data-valid signal resulting from detecting and decoding of the multitone preamble to the message just transmitted; hence, AND gate 525 is disabled by the presence of the low level at the Q output of data-valid flip flop 511. This circuit configuration assures that a second data-valid pulse will not cause generation of erroneous signals. The output of "end-of-message" detector 516 is passed by NAND gate 524 and the "received-end-of-message" pulses are generated as shown. The leading edge of the "received-end-of-message" pulse is not used in the transmit mode. The trailing edge of the "received-end-of-message" pulse performs the following functions: (a) Resets data-valid flip flop 511; (b) Resets receive/transmit flip flop 324 (FIG. 7) in memory control 529 leaving the transceiver in the receive mode; and (c) Resets standby/active flip flop 301 (FIG. 7) in memory control 529 leaving the system in the standby mode. At this point, the transceiver will enter the active/receive mode upon receipt of a valid multitone signal or will enter the transmit mode upon closure of push-to-talk switch 537. MEMORY CONTROL LOGIC The explanation of memory control logic functions will be discussed relative to the transceiver of FIGS. 11A and 11B, collectively referred to as "FIG. 11". Memory control logic 529 is so designed that when power is turned on or an assigned function (transmit a message or receive a message) is completed the system enters the "standby" mode with all flip flops and counters in the proper inital configuration. Closure of push-to-talk switch 537 signals that the system is to operate in the transmit mode. On the other hand, reception of a valid multitone signal from a remote transmitter while the transceiver is in the "standby" mode will cause the transceiver to operate in the receive mode until an "end-of-message" multitone signal is received and will then return to the standby mode. The following paragraphs will discuss the operation of the transceiver memory control logic 529 (FIG. 11) in detail. It should be mentioned that the information supplied is equally applicable to either the stand-alone transmitter or receiver. OPERATION OF MEMORY CONTROL LOGIC IN THE TRANSMIT MODE In the following description, references will be to FIG. 11, (comprised of FIG. 11A and FIG. 11B, together), except where otherwise noted. Closure of push-to-talk switch 537 results in the following: (a) Transmit/receive flip flop 324 (FIG. 7) is set to place the transceiver in the transmit (T) mode. Setting transmit/receive flip flop 324 results in the following actions: (i) Switch S.sub.1 is placed in the transmit (T) position so that the message signal (from a microphone or other signal source) is fed to input signal processor | ||||||