Methods and apparatus for interfacing an encryption module with a personal computer5517569Abstract An encryption module for encrypting financial and other sensitive data may be conveniently interposed in series between a personal computer and the keyboard associated therewith. An application program designed to run on the PC is configured to prompt the user to enter his PIN or other confidential data into the encryption module; consequently the confidential data need not be transmitted in an unencrypted fashion, and need not reside on the PC hard drive in an unencrypted form. Claims I claim: Description TECHNICAL FIELD
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Port No. Function
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pa0 card swipe input/output (channel 1)
pa1 card swipe input/output (channel 2)
pa2 modem interrupt
pa3 read/write*
pa4 ale
pa5 cs
pa6 output to "system validation" LED
pa7 (smart card) read/write data
pb0 keypad row 1
pb1 keypad row 2
pb2 keypad row 3
pb3 keypad row 4
pb4 buffer enable
pb5 smart card clock
pb6 smart card control
pc0 d0 parallel data interface to modem
pc1 d1 parallel data interface to modem
pc2 d2 parallel data interface to modem
pc3 d3 parallel data interface to modem
pc4 d4 parallel data interface to modem
pc5 d5 parallel data interface to modem
pc6 d6 parallel data interface to modem
pc7 d7 parallel data interface to modem
pd0, pd1 interface to pentec bar code reader data loader
pd2 pc clock
pd3 pc data
pd4 keyboard clock
pd5 keyboard data
pe0 keypad column 1
pe1 keypad column 2
pe2 keypad column 3
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Referring now to FIGS. 12-14, keypad 1102 is suitably connected with the various ports associated processor 1212 as set forth in FIG. 14. Refer now to FIGS. 12-13 and 15, control gate 1222 suitably comprises an analog switch, for example a module no. 74HC4066 manufactured by Motorola, Inc. Switch 1222 suitably comprises four internal switches a-d, which are suitably simultaneously controlled by the output of port pb4, such that internal switches a-d are either all open or all closed in accordance with the logic value of the output of port pb4. Generally speaking, in essentially all operational states of module 214, internal switches a-d will remain open, effectively isolating keyboard 206 from box 204. During the transparent mode (discussed below), internal switches a-d will typically remain closed, permitting normal communication between the keyboard and the PC. With continued reference to FIGS. 12-13 and 15, the buffer enable signal from port pb4 of processor 1212 is suitably applied to control gate 1222. In addition, the keyboard clock and keyboard data signals are transmitted between ports pd4 and pd5, respectively, of microprocessor 1212 to a bus 1219 extending from switch 1222 to keyboard 206 via connector 210. Similarly, the PC clock and PC data signals are transmitted between ports pd2 and pd3, respectively, of microcontroller 1212 to a databus 1218 extending between control gate 1222 and box 204 (FIG. 1) via connector 212. Referring now to FIGS. 12, 13 and 16, a first embodiment of magnetic strip reader circuit 1206 associated with magnetic strip reader 1104 (FIG. 11) suitably comprises a magnetic reader head 1602, for example a 1.6 microhenry inductor coil, respective first and second amplifiers 1604 and 1606, for example model no. LM324a operational amplifiers, respective comparators 1608 and 1610, for example model no. LM393, and an inverting schmidt trigger 1612, for example port no. 74HC14. More particularly and with continued reference to FIG. 16, a transaction card of the type bearing a magnetic strip is suitably slid through magnetic strip reader 1104 of module 214 (FIG. 11) such that the magnetic strip magnetically engages reader head 1602. The output of coil 1602 is suitably applied to the inverting input of amplifier 1606 which suitably exhibits a gain on the order of 20. The output of amplifier 1604 is suitably applied to the non-inverting input of amplifier 1606. The output of amplifier 1606 is suitably applied to the non-inverting input of comparator 1608 and to the inverting input of comparator 1610. By applying a determined threshold voltage to the inverting input of amplifier 1608, and by also applying a predetermined threshold voltage to the non-inverting input of amplifier 1610, a series of logic hi and logic low pulses are applied to the input of schmidt trigger 1612, which inputs are effectively rectified, squared and sharpened into a binary square wave by the schmidt trigger/comparator combination. The output of schmidt trigger 1612 is a function of the output of coil 1602 and corresponds to the data which is magnetically encoded into the magnetic strip which is drawn through magnetic card reader 1104. The output of schmidt trigger 1612 corresponds to the channel 1 swipe data applied to port pa0 of processor 1212. The magnetic head reader circuit of FIG. 16 is particularly useful in the context of cards bearing magnetic strips which comprise a single "track", or single column of magnetically encoded information. Alternatively, many magnetic strips of the type typically found on transaction cards comprise two or more separate magnetic columns embedded within the magnetic strip. In such cases, it may be desirable to employ dual magnetic reader coils in the context of card reader slot 1104. More particularly and referring now to FIG. 17, an alternate embodiment of circuit 1206 suitably comprises respective first and second reader coils 1603a and 1603b which are suitably configured to read the corresponding first and second magnetic rails (not shown) comprising the dual rail magnetic strip associated with a transaction card. In the alternative embodiment shown in FIG. 17, the circuit essentially comprises two of the circuits shown in FIG. 16 configured to generate respective outputs 1702 and 1704 which are suitably applied to respective ports pa0 and pa1 of processor 1212. Referring now to FIGS. 18-20 and with momentary reference to FIG. 12, microcontroller 1212 suitably comprises a random access memory (RAM) 1802, a read only memory (ROM) 1902 and an erasable electronically programmable read only memory (EEPROM) 2002. More particularly, RAM 1802 suitably comprises, inter alia, respective memory sectors 1804-1836 corresponding to various addresses in RAM 1802. As discussed below in conjunction with the operational states of module 214, various predetermined data are suitably stored and retrieved in data sectors 1804-1836 during operation of module 214. With continued reference to FIG. 19, the operating code (operational program) which controls the operation of module 214 is suitably stored in a first sector 1904 in ROM 1902. Moreover, various interrupt sectors, useful in the operation of module 214 are suitably stored in a second sector 1906 within ROM 1902. Referring now to FIG. 20, EEPROM memory map 2002 suitably comprises non-volatile memory for use in storing encryption keys associated with the encryption algorithm employed in the context of the present invention to encrypt confidential data. More particularly, EEPROM 2002 suitably comprises a first sector 2004 corresponding to future encryption keys, a second sector 2006 corresponding to the serial number of the initial encryption key, and a third sector 2008 corresponding to an encryption counter. In accordance with one aspect of the present invention, any suitable encryption algorithm may be employed by module 214, module 300, or PC 110 in the context of the present invention, which algorithm provides adequate security against unauthorized detection of the underlying confidential data. Referring now to FIGS. 21-38, the operation of system 100, and particularly the operational states of module 214, will now be described. With particular reference to FIG. 21, upon powering up of module 214, a reset signal is applied to reset port 1310 of processor 1212 (Step 2102). Upon entering the reset condition, system initialization is executed (Step 2104). More particularly and with momentary reference to FIG. 22, system initialization Step 2104 suitably entails various initialization Steps (2104b), including, inter alia: 1. Initializing the current mode to transparent mode, for example by setting current mode register 1804 (see FIG. 18) to the transparent mode condition, as discussed in greater detail below; 2. Initializing previous mode register 1806 to "no mode"; 3. Initializing the system interrupts to appropriate trigger characteristics; 4. Enabling interrupts from the PC interface bus (e.g. connector 212); and 5. Initializing the PC interface temporary buffer 1808 to "empty". The relevancy of the foregoing initialization steps are discussed in greater detail below in conjunction with ensuing description of the operation of module 214. Upon completing system initialization, the system enters a system redirect state (Step 2106), whereupon the system then enters the appropriate operational mode; in the context of system startup, the system will default to transparent mode, as set forth above in conjunction with system initialization Step 2104(b). More particularly, a preferred embodiment of the present invention employs an interrupt-based processing scheme within module 214. Thus, as the system flows through the main operational loop set forth in FIG. 21, the system will from time to time receive interrupts from PC 110. Upon receipt of a "mode change" interrupt command from PC 110, processor 1212 causes module 214 to terminate the then current mode, and enter system redirect (Step 2106), from which the appropriate new operational mode may be entered. From the main control loop governing the operation of module 214 shown in FIG. 21, the system may enter any one of a number of operational states as a result of a number of predicate instructions. More particularly, the system may enter certain operational states as controlled by the executable code resident within sector 1904 of ROM 1902. In addition, the system may enter certain operational states as a result of commands received from PC 110, as set forth in more detail in conjunction with FIG. 23. Referring now to FIG. 23, PC 110 from time to time sends interrupt commands to module 214 via connector 212 (Step 2302). Upon receipt of a PC interrupt, the interrupt data packet received from PC 110 is suitably stored in sector 1808 of RAM 1802 (Step 2304). The system then determines if the complete message (interrupt data packet) was received from PC 110; if not, the system returns to main loop 2100. If a complete message is received at module 214, the system determines if the data corresponds to a command instruction or whether the message corresponds to other than a command instruction (Step 2308). If the message corresponds to data other than a command instruction, the message is suitably stored in data output buffer 1810 of RAM 1802 (Step 2310), for subsequent processing, e.g., modem transmission to host computer 102. Thereafter, the contents of PC interface temporary buffer 1808 are reset to empty (Step 2320), then the system again returns to its pre-interrupt state (Step 2322). Returning now to Step 2308 of FIG. 23, if the data received is a command instruction, the system determines if the command instruction corresponds to a mode change (Step 2312). If not, the data is stored in command register 1812 of RAM 1802 for possible subsequent use within the then current mode (Step 2316); the system then proceeds to Step 2320, as described above. If the message received from PC 110 corresponds to a mode change command ("Yes" branch from Step 2312), the then current mode is written into previous mode register 1806 (Step 2314), and the newly received mode is written into current mode register 1804 of RAM 802 (Step 2318). The system then proceeds to Step 2320, as described above. With continued reference to FIG. 21, upon receipt of a message from PC 110, processor 1212 interrogates current mode register 1804 and, in accordance with the contents of register 1804, answers the appropriate operational mode from main loop 2100. In the context of startup operation, the system is suitably configured to enter transparent mode (Step 2110). Referring now to FIG. 24, transparent mode 2110, just as with various other operational modes described below, determines whether a subsequent mode change has been received since entering transparent mode 2110 (Step 2402). If a mode change is received, the system enters the system redirect state (Step 2106); (see also FIG. 21) and enters the newly selected mode. If a mode change has not occurred, processor 2112 interrogates previous mode register 1806 to determine if the previous mode corresponds to transparent mode (Step 2404). If the previous mode corresponds to transparent mode, the system proceeds to Step 2410. If the previous mode was not transparent mode, the system commands the keyboard to clear its internal buffers and to set previous mode register 1806 to transparent (Step 2408). More particularly, if the previous mode was not transparent mode, it is possible that spurious keystrokes may have been entered into keyboard 206, which keyboard data may be stored in buffers internal to keyboard 206 and not shown in FIG. 2. In order to prevent data corresponding to these spurious keystrokes from being transmitted to PC 110, the keyboard internal buffers are cleared (Step 2408). Thereafter, the system enables the interface between keyboard 206 and PC 110 (Step 2410). More particularly, and with reference to FIGS. 12, 13, and 15, Step 2410 of FIG. 24 suitably entails processor 1212 generating a buffer enable signal at port PB4, and transmitting the buffer enable signal to control gate (switch) 1222. In response, internal switches A-D of switch 1222 are closed, establishing direct communication between PC 110 and keyboard 206 through connector 212, bus 1218, switch 1222, bus 1219, and connector 210. Thereafter, the system continues to cycle through transparent mode 2110, permitting normal operation of keyboard 206 with respect to PC 110. The system will continue to cycle through transparent mode 2110 until a subsequent message is received from PC 110. Returning now to FIG. 21, the system may also receive a command to enter scan mode (Step 2112), for example in response to a scan mode request from PC 110 (see Step 806, FIG. 8), whereupon processor 1212 causes module 214 to enter the scan mode of operation (Step 2114). More particularly and referring now to FIG. 25 (scan mode 2114) generally involves "scanning" the circuitry associated with keypad 1102 (FIG. 14) to detect data (e.g. PIN) entered into keypad 1102 by the user. With continued reference to FIG. 25, scan mode operation involves, inter alia, initializing PIN entry buffer 1814 of RAM 1802 to empty (Step 2502), to prepare the PIN buffer to receive data which is about to be entered onto keypad 1102 by the user. The system detects whether a subsequent mode change command has been received (Step 2504); if so, the system returns to system redirect Step 2104. If no mode change has occurred, module 214 waits until a keypress is detected (Step 2506) or, alternatively, until a mode change is detected (Step 2504). More particularly, processor 1212 scans ports PB0-PB3 and ports PE0-PE2 (See FIG. 13) corresponding to rows 1-4 and columns 1-3 of keypad 1102, respectively (See FIG. 14). When a keypress is detected, the system determines if the depressed key corresponds to one of the numbers 0-9 (Step 2508); if so, module 214 suitably sends a signal to PC 110 to cause a "dummy" indicia of the depressed key to screen 202 (FIG. 2). More particularly, the operational program stored in sector 1904 of ROM 1902 (FIG. 19) of processor 1212 suitably includes an operating code which permits module 214 to communicate with PC 110 in a manner which emulates the manner in which conventional keyboards (e.g. keyboard 206) typically communicate with box 204. In a preferred embodiment of the present invention, the operating code governing the operation of module 214 is suitably configured in accordance with any suitable protocol, for example the protocol employed by IBM in its PCs or any other suitable derivative or variant thereof, to thereby permit module 214 to communicate with box 204 in a manner which emulates conventional communication between keyboard 206 and box 204, data transmission and other communication between module 214 and box 204 may be conveniently and efficiently carried out in a manner which is essentially transparent to box 204; that is, when box 204 receives data and/or information from module 214, box 204 interprets the data just as though box 204 had received it from keyboard 206. Similarly, when box 204 transmits data and/or information which is received by module 214, box 204 configures the data/information packages in the same manner in which box 204 would normally configure the data for receipt by keyboard 206. By leveraging presently known data transmission protocols in this manner, module 214 may be conveniently interposed in series between the keyboard and the keyboard port on the PC of essentially all PCs which comport with industry recognized protocol schemes. With continued reference to FIG. 25, if a keypress corresponds to a 0 through 9, the system waits until the key is released (Step 2518) before capturing the data. In this way, the system desirably avoids capturing repetitive data which may often be generated by many keypads which are specifically configured to continuously generate repetitive keystroke data when a particular key is held down by the user. Return now to Step 2508, if the keypress was not a 0 through 9, the system determines if the keypress corresponds to an "Enter" (Step 2512); if so, a message corresponding to an "Enter" command is transmitted from module 214 to PC 110 (Step 2514), indicating that entry of the confidential data (e.g. PIN) is complete. If, on the other hand, the keypress does not correspond to an "Enter", the system determines the identity of the keypress. In the context of the illustrated embodiment, if the keypress does not correspond to a 0 through 9, and further does not correspond to an "Enter", the system concludes that the keypress corresponds to a "Cancel" (Step 2516). Thus, module 214 transmits a message to PC 110 indicating that entry of the confidential data has been canceled by the user. Upon release of the depressed key by the user (Step 2518), the system determines if the keypress corresponds to a 0 through 9 (Step 2520); if so, the particular numeric keypress is suitably stored in PIN entry buffer 1814 of RAM 1802 (Step 2524), and the system returns to Step 2504 to await the next keypress. If the keypress corresponds to a "Cancel" (Step 2522), the systems restores PIN entry buffer 1814 to empty (Step 2528) and returns to Step 2504 to await either a mode change or a subsequent keypress. If the keypress corresponds to an "Enter" ("Yes" branch of Step 2522), module 214 suitably encrypts the data stored in PIN enter buffer 1814 (Step 2526), as discussed in greater detail below in conjunction with FIG. 26. Although the illustrated embodiment is described in the context of numeric (i.e., "0" through "9") PIN data, it will be appreciated that the confidential data entered into module 214 may be of any suitable form, e.g., numeric, alpha, alphanumeric, ASCII, binary, or any other suitable modality. Referring now to FIG. 26, the encryption operation 2526 suitably proceeds as follows. Once the confidential data (e.g., PIN) is entered onto keypad 1102 by the user, processor 1212 retrieves the data from personal account number register 1818 of RAM 1802 and the PIN from buffer 1814 (Step 2602). These data, alone or in conjunction with other data, are suitably combined and encrypted in any suitable matter (Step 2602). In a preferred embodiment, these data may be suitably combined in accordance with ANSI specification X9.24-1992. The data is suitably encrypted in accordance with ANSI standard X3.92-1981 or any other desired encryption technique. More particularly, the foregoing combination and encryption algorithms are desirably resident in operational program sector 1904 of ROM 1902, and operate in conjunction with encryption key information suitably stored in EEPROM 2002 (See FIGS. 19 and 20). By storing the encryption key data in nonvolatile memory (i.e., EEPROM), system integrity and security is enhanced. With continued reference to FIG. 26, upon encrypting the data in accordance with Step 2602, the encrypted data is suitably written into the next successive location in encrypted PIN sector 1816 of RAM 1802 (Step 2604). Thereafter, the address corresponding to the location in sector 1816 wherein the encrypted data is written is transmitted to PC 110 (Step 2606). More particularly, and with momentary reference to FIG. 2, once the data is encrypted within module 214, the location of the encrypted data is transmitted to PC 110 via connector 212, such that unencrypted confidential data need not be transmitted from module 214 to PC 110 in order to effect a transaction. After encrypting the data, processor 1212 suitably creates a new unique key for use in a subsequent encryption process and stores the new key in future encryption key sector 2004 of EEPROM 2002 (Step 2608). In accordance with one aspect of the present invention, the new encryption key may be generated in accordance with any suitable scheme which is compatible with the encryption algorithm executed in Step 2602. In accordance with a preferred embodiment, a new unique encryption key may be generated in accordance with ANSI X9.24-1992. Upon transmitting indicia of the encrypted data from module 214 to PC 110, PC 110 continues to execute the application program residence therein, as described above in detail in connection with FIGS. 4-10. Returning now to the main control loop 2100 of module 214 (FIG. 21), module 214 may also elect to enter card swipe mode 2118 (Step 2116). More particularly, and with momentary reference to FIG. 7, PC 110 may request Module 214 to enter the card swipe operational mode, for example at a point during the execution of the application software resident in PC 110 where such application software prompts the user to swipe his transaction card through card swipe slot 1104 of module 214 (FIG. 11), for example as discussed above in connection with Step 716. Referring now to FIG. 27, upon entering the swipe operational mode, processor 212 suitably initializes (clears) respective swipe data input buffers 1820, 1822 of RAM 1802 (Step 2702). The system then looks for a mode change (Step 2704), and returns to system redirect state 2106 if a mode change is detected. Otherwise, the system sets a swipe timeout counter to a predetermined maxtime during which the transaction must engage the card reader (Step 2706). In a preferred embodiment, the predetermined value of this maxtime, on the order of 15 seconds, is suitably stored in swipe time-out register 1824 of RAM 1802. The time-out counter is successively decremented (Step 2708) until the software timer resident in sector 1824 reaches zero (Step 2710), whereupon the data then resident in buffers 1820, 1822 are transmitted to PC 110 (Step 2714). Alternatively, rather than waiting until the maxtime counter counts down to zero, the "swiped" data may be transmitted to PC 110 when processor 1212 determines that respective input buffers 1820, 1822 are full (Step 2712). Upon the first to occur of the timing out of these swipe timeout timer (Step 2710) or a detection that the swipe input buffers are full (Step 2712), the data within card swipe buffers 1820, 1822 are transmitted to PC 110 (Step 2714). With momentary reference to FIGS. 12 and 16-17, recall that magnetic strip reader circuit 1206 "reads" the data from the magnetic strip on a transaction card through magnetic head reader 1602 (or magnetic head readers 1603(a), 1603(b) in FIG. 17), whereupon reader circuit 1206 applies an output signal (corresponding to one or both of "ch 1 swipe" and "ch 2 swipe") to ports pa0 and pa1 of processor 1212, respectively, as discussed in detail above. More particularly and with reference to FIGS. 16 and 28, as a transaction card bearing a magnetic strip is drawn through card reader slot 1104 (see FIG. 11), magnetic reader head 1602 outputs alternating high and low voltage levels corresponding to the data encoded on the magnetic strip. Upon the detection of a first output level from schmidt trigger 1612, for example a logic high value, a hardware timer (not shown) resident in processor 1212 is stopped, and the time at which this timer is stopped is suitably saved in swipe timer * register 1826 of RAM 1802 (see FIG. 18) (Step 2802). The card swipe timer is again reset to zero and restarted, awaiting the detection of a next predetermined voltage level from schmidt trigger 1612 (Step 2802). In conjunction with the timer data retrieved in Step 2802, processor 1212 determines if the output of schmidt trigger 1612 corresponds to a predetermined logic state (e.g. a zero or a one) (Step 2804). This logic data may then be stored in successive bit locations in the appropriate swipe input buffer (e.g., buffer 1820, 1822) (Step 2804). The system them determines if the swipe input buffer(s) is full (Step 2806). If the swipe input buffer is full, a buffer full flag is suitably set in swipe buffer full flag register 1828 of RAM 1802 (FIG. 18) (Step 2808), which permits processor 1212 to determine when the swipe input buffer(s) is full (see Step 2712, FIG. 27). Returning now to Step 2806 of FIG. 28, if the swipe input buffer(s) is not full, the aforementioned software timer is reset to a maximum bit interval value (Step 2810), and the process returns (Step 2812) to the point at which it left the process set forth in FIG. 27, whereupon the process of FIG. 28 is repeated on a bit-by-bit interrupt basis until all the appropriate data is "read" from the magnetic strip on the transaction card. Note, however, that the entire process of accumulating the card swipe data described in conjunction with FIG. 28 occurs in a very short period of time, for example ten milliseconds to one second, as a card is drawn through card reader slot 1104 (FIG. 11). Returning now to FIG. 21, module 214 is also configured to enter print mode 2122 from main loop 2100 (Step 2120) for example upon a request to do so from PC 110 (see Step 816, FIG. 8). Referring now to FIG. 29, print operation mode 2122 suitably entails initializing the printer (Step 2902), for example to establish various hardware and software parameters associated with the printing process. In this regard, and as briefly discussed above, the printer may be affiliated with PC 110, for example by connecting a printer directly to box 204, or by connecting the printer to PC 110 via a suitable networking configuration. Alternatively, the printer may interface directly with the encryption module, for example at connector 310 of module 300 (FIG. 3 or, alternatively, at peripheral device module 1200 of module 214 as shown in FIG. 12. With continued reference to FIG. 29, the system determines if a mode change has occurred (Step 2904) and, if so, returns to system redirect Step 2906. The system then determines if the data to be printed is currently available, for example by interrogating data output buffer 1810 (FIG. 18) (Step 2908). If the data is not available, the system returns to Step 2902 to await the data to be printed. If the data is available ("Yes" branch of Step 2908), the system determines if the printer is ready (Step 2930). In this regard, the printer to be checked will likely be connected to module 214, inasmuch as it would not typically be necessary to execute print operation 2122 if the printer were connected to PC 110. Stated another way, if PC 110 is equipped with a printer, the print operation may be controlled directly by PC 110, while the print operation as set forth in FIG. 29 is appropriately controlled by module 214 if the printer employed in the context of the present invention is interfaced with module 214. With continued reference to FIG. 29, if the printer is not ready, module 214 suitably sends a command to the PC indicating that the printer associated with module 214 is not ready. In this regard, PC 110 may prompt the user to correct the printer situation, for example as described above in conjunction with FIG. 7. If the printer associated with module 214 is ready, the data resident in data output buffer 1810 is transmitted to the printer, for example via serial bus 1211 (see FIG. 12). In accordance with the preferred embodiment, the data to be printed is transmitted to the printer in serial fashion; hence, the process set forth in FIG. 29 is desirably repeated until the data present in data output buffer 1810 is sequentially transmitted to the printer. Returning now to main loop 2100 (FIG. 21) and with reference to FIG. 30, module 214 is suitably configured to enter modem mode 2126 (Step 2124), for example in response to a request to do so from PC 110 (see Step 710, FIG. 7). As briefly discussed above, the present invention may be configured to transmit data and information from PC 110 to host computer 102 in any convenient manner, for example via a modem associated with PC 110 or, alternatively, modem 1202 associated with module 214 (or modem connector 308 associated with module 300; FIG. 3). If data is transmitted from PC 110 via a modem associated with PC 110, it would not generally be necessary for module 214 to execute modem operation 2126; rather, the modem operation may be effectively carried out by PC 110. If, on the other hand, modem operation is to be effected through a modem interfaced with module 214, it may be particularly advantageous for processor 1212 to control the modem operation. With continued reference to FIG. 30, modem operation 2126 suitably entails an initialization of modem 1202 (Step 3002). Module 214 then determines if a mode change has occurred (Step 3004) and, if so, the system returns to system redirect 2106. If a mode change has not occurred, the system determines if data output buffer 1810 contains the data to be transmitted via modem (Step 3006). If the data is not resident in buffer 1810, the system returns to Step 3004 and continues cycling between Steps 3004 and 3006 until the data is written into buffer 1810 or until a mode change occurs. When data output buffer 1810 contains the appropriate data to be transmitted via modem, processor 1212 retrieves the data from output 1810 and transmits the data via modem to host computer 102 (Step 3008). When it is desired for module 214 to receive data via modem, for example from host computer 102, processor 1212 may be suitably configured to retrieve the data from modem 1202, for example at modem interrupt port pa2. Referring now to FIG. 31, PC 110 suitably transmits a request to module 214 to transmit data via the modem connected to module 214. More particularly, a modem interrupt message is applied to port PA2 of module 1212 by modem 1202. Module 214 then determines if the message corresponds to a "data received" interrupt (Step 3102) or a modem transmit interrupt (Step 3104). If a data received interrupt occurs ("Yes" branch of Step 3102), indicating that data has been received at modem 1202, the data received at modem 1202 is retrieved by processor 1212 and transmitted to the PC via connector 212 (Step 3106). If the modem interrupt message corresponds to a modem transmit request (Step 3104), processor 1212 retrieves the data to be transmitted from buffer 1810 and applies the data, for example on a byte-by-byte basis, to modem 1202 (Step 3108). If the modem interrupt corresponds to neither a data received or a data transmit message, an error message is suitably sent to the PC (Step 3110). After data which is received at modem 1202 is retrieved and sent to PC 110 (Step 3106), and after data is sent by processor 1212 from buffer 1810 to modem 1202 (Step 3108), the system returns (Step 3112) to the low level process of FIG. 30, and the process is repeated for each successive interrupt generated by modem 1202. Referring now to FIGS. 21 and 32, module 214 may be suitably configured to enter bar code operational mode 2130 (Step 2128), for example in response to a request to do so from PC 110. Bar code operation 2130 suitably entails determining whether a mode change has occurred (Step 3302) and, if so, returning to system redirect Step 2106. If a mode change has not occurred, data may be input from a general purpose module 1210, for example a bar code reader (Step 3204). Once the bar code or other data is received by module 214, it may be appropriately transmitted to PC 110, as desired (Step 3206). Referring now to FIGS. 21 and 33, module 214 may be suitably configured to execute a smart card operation 2134 (Step 2132), for example in response to a request from PC 110 to do so. In this regard, although many of the various functional features associated with module 214 (e.g. modem operation 2126, print operation 2122, swipe operation 2118, and the like) are initiated in response to a request from PC 110 in accordance with the embodiment described herein, it will be appreciated that the various operational states of module 214 may suitably be effected in any desired manner, for example by entering appropriate commands directly into module 214. With continued referenced to FIG. 33, smart card mode 2134 suitably entails determining whether a mode change has occurred (Step 3302) and, if so, returning to system redirect Step 2106. If no mode change has occurred, the system determines if data is to be read from a smart card (Step 3304). In this regard, and as briefly stated above, such a request may come from PC 110, or may be otherwise effected by the user, for example by entering a particular code or depressing other buttons (not shown) onto keypad 1102 (FIG. 11). If data is to be read from a smart card ("Yes" branch of Step 3304), data is retrieved by processor 1212, for example via smart card reader 1208 (FIG. 12). Upon retrieving the data from the smart card, the data may be transmitted to PC 110 (Step 3306). As discussed above, module 214 may also be configured to write data onto a smart card. In this case, the appropriate data to be written onto the smart card may be suitably retrieved from data output buffer 1810 and applied to smart card circuit 1208 (Steps 3308, 3310). Referring now to FIGS. 21 and 34, module 214 in the PC application software discussed above in conjunction with FIGS. 4-10 may be suitably configured such that the application software resident in PC 110 must first validate module 214 before permitting the transmission of encrypted data or otherwise performing functions described herein. More particularly, in view of the importance of maintaining security in the context of real time funds transfer authorization, it may be desirable to permit PC 110 (e.g., through software) to confirm that module 214 embodies satisfactory security features before effecting transactions. With continued reference to FIGS. 21 and 34, module 214 may be suitably configured to enter a system validation mode 2138 (Step 2136), for example in response to a request from the user or from PC 110 to do so. System validation mode 2138 entails, inter alia, a determination of whether a mode change has occurred (Step 3402) and, if so, the system may be configured to return to system redirect Step 2106. Module 214 may then be configured to receive and/or retrieve validation data from PC 110, which validation data either confirms that the application software running on PC 110 is compatible with module 214; alternatively, the validation data may permit module 214 to run a self-check to determine if adequate security mechanisms are in place. Module 214 may then confirm that it is compatible with the software resident on PC 110 (Step 3406). If the system determines that either module 214 or the application program running on PC 110 are not "valid" according to predetermined validation criteria, module 2]4 may be configured to either disable itself or to disable the software running on PC 110 (Step 3408). Referring now to FIGS. 21 and 35, module 214 may suitably be configured to execute a bit operation 2142 (Step 2140), for example in response to a request from PC 110 or the user to do so. Bit operation 2142 suitably determines if a mode change has occurred (Step 3502) and, if so, returns the system to system redirect Step 2106. If a mode change has not occurred, module 214 may execute any number of built-in tests (bits) (Step 3504), for example testing various data transmission and retrieval processes, testing the presence and/or functionality of various peripheral devices, or executing the various wraparound and/or auditing facilities set forth in FIG. 1. From time to time during the operation of PC 110, it may be desirable to transmit encrypted data from module 214 to PC 110. With continued reference to FIG. 21 and referring also to FIG. 36, module 214 may thus be configured to selectively enter retrieval mode 2146 (Step 2144), for example in response to a request to do so from the user or from PC 110. Retrieval operation 2146 suitably entails, inter alia, determining whether a mode change has occurred (Step 3602) and, if so, returning the system to system redirect Step 2106. If a mode change has not occurred, indicating that the system remains in retrieve mode, module 214 waits for a request from PC 110 for the encrypted data, which request may include the address in sector 1816 of RAM 1802 (FIG. 18) where the desired encrypted data is stored (Step 3604). Upon receipt of a request from PC 110 to transmit encrypted data, module 214 retrieves the encrypted data from an appropriate location in memory (e.g., encrypted PIN holding area 1816), and sends the encrypted data to PC 110 (Step 3606). Upon doing so, processor 1212 may suitably reset encrypted PIN holding area 1816 back to empty. Although the subject application has been described herein with reference to the appended drawing figures, it will be appreciated that the scope of the invention is not so limited. Various modification in the design and implementation of various components and method steps discussed herein may be made without departing from the spirit and scope of the invention, as set forth in the appended claims.
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