Scrambler and unscrambler for serial data4087626Abstract Serial data is scrambled at a transmitting terminal by storing it in sequential locations in a first random access memory, while previously stored information is read out of a second random access memory using a pseudo-random address counter. Whenever one memory is filled and the other memory is emptied, the roles of the memories are transposed. Similar apparatus at a receiving terminal is operated in synchronism and phase to unscramble the received data. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
Table I
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INTERLEAVER
State of State of
Clock Numerical Pseudo-Random
Pulse Seq. Counter Seq. Counter
Number (or Bit (or Bit
(or Time) Number) Number)
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1 31 31
2 30 15
3 29 7
4 28 3
5 27 17
6 26 24
7 25 12
8 24 22
9 23 27
10 22 29
11 21 14
12 20 23
13 19 11
14 18 21
15 17 10
16 16 5
17 15 2
18 14 1
19 13 16
20 12 8
21 11 4
22 10 18
23 9 9
24 8 20
25 7 26
26 6 13
27 5 6
28 4 19
29 3 25
30 2 28
31 1 30
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The output of numerical sequence counter 46 may be applied through "and" gate 50 and "or" gate 52 to the address input of memory 26, or, may be applied through "and" gate 54 and "or" gate 56 to the address input of memory 36. The output of pseudo-random sequence counter may be applied through "and" gate "58" and "or" gate 56 to the address input of memory 36, or, may be applied through "and" gate 60 and "or" gate 52 to the address input of memory 26. The paths taken by the outputs of counters 46 and 48 to the address inputs of the memories 26 and 36 are determined by the enabling signals applied to "and" gates 50, 54, 60 and 58 from outputs Q and Q of flip-flop 20. While the paths from counters 46 and 48 to the address inputs of memories 26 and 36 are shown by individual lines and individual gates, it will be understood that they each represent five parallel lines and five parallel gates for the five-bit addresses in the present examples described. Memories 26 and 36 have write command inputs 62 and 64, respectively, and have read command inputs 66 and 68, respectively. The write and read commands alternate at a "frame" rate, the rate at which flip-flop 20 is triggered. The frame rate is equal to the bit rate from clock 14 divided by 31 in divider 18. (The divisor 31 is used in the present example instead of 32 because while each memory 26 and 36 will normally have storage locations for 2.sup.n =32 bits, simple economical pseudo-random sequence counters have outputs for 2.sup.n -1 addresses, or 31 addresses, omitting the all-zeros address). Therefore, a write command is applied to a memory for a period of time sufficient for the memory to be filled with 31 binary bits. Then the read command is applied for a period of time sufficient for all 31 stored bits to be read out from the memory. OPERATION OF FIG. 1 The operation of FIG. 1 will be described during the frame when the flip-flop 20 provides a true output at Q, and then during the next frame when the flip-flop 20 provides a true output at Q. The Q signal supplies a write command at 62 to memory 26, and enables gate 24, so that input data at 10 is written into the memory at addresses in numerical sequence determined by the output of counter 46 applied through enabled gate 50 and gate 52 to the memory. During the same frame, the Q signal supplies a read command to memory 36, and enables output gate 38 to pass data read out from the memory at addresses having a pseudo-random sequence determined by the output of counter 48 passed through enabled gate 58 and gate 56 to the memory. At the end of the Q frame when memory 26 is filled and memory 36 is emptied, the flip-flop 20 is triggered and it provides a Q output for the following Q frame. During the Q frame, memory 36 receives a write command at 64 and gate 34 is enabled so that data from 10 is written into memory 36 at addresses in numerical sequence determined by the output of counter 46 passed through enabled gate 54 and gate 56 to the memory. During the same Q frame, the Q signal supplies a read command to memory 26, and enables output gate 28 to pass data read out from the memory at addresses having a pseudo-random sequence determined by the output of counter 48 passed through enabled gate 60 and gate 52 to the memory. It is thus seen that during frame Q, data is stored in numerical sequence in memory 26 while data is read out of memory 36 from locations having addresses in a pseudo-random sequence. Then, during frame Q the roles of memories 26 and 36 are transposed. All the data passed from line 12 to the transmission channel (not shown) is time-division scrambled or interleaved for purposes of privacy and/or error reduction. DESCRIPTION OF FIG. 2 FIG. 2 is a simplified diagram of a complete transmission system including a scrambler like FIG. 1 at a transmitting terminal, a transmission channel 70, 72, 74 and an unscrambler like FIG. 1 at a receiving terminal. Note that the numerical counter 46 and the pseudo-random counter 48 in the scrambler are transposed as pseudo-random counter 48' and numerical counter 46' in the unscrambler. The transmission channel includes, in addition to a path 70 for data, a path 72 conveying clock pulses from clock 14 to the receiving terminal, and a path 74 conveying framing pulses from divider 18 to the flip-flop 20' at the receiving terminal. Any other suitable known method of keeping the receiving terminal in synchronism and phase with the transmitting terminal may be employed. Data paths in use during the Q frame are shown by heavy lines. Data paths in use during the Q frame are shown by light lines. During the Q frame, the pseudo-randomly scrambled data sent over the transmission channel 70 is read into memory 26' in memory locations having the same pseudo-random pattern as the data had in transmitting memory 36. At the same time, during the Q frame, the data previously pseudo-randomly stored in receiving memory 36' is read out from numerically sequential memory locations, thereby ordering the serial data back into the original unscrambled sequence it had at input 10 at the transmitting terminal. Of course, during the following Q frame, the roles of memories 26 and 36 are transposed, and the roles of memories 26' and 36' are transposed, and the paths followed by data are light lines in FIG. 2. While the system described is one in which the data paths accomodate bit-serial data, it will be understood that the data paths shown may represent a plurality of parallel paths to accommodate character-serial or word-serial data. In this case, the memory addressing components will serve memories 26 and 36 each constituted by a plurality of parallel-connected integrated circuit memories, each one storing one bit in each addressable storage location.
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