Voice controlled disappearing audio delay line3970791Abstract A delay line which disappears under voice control is comprised of a pluray of shift registers delays the incoming voice signal to permit transmission of the voice scrambler preamble. The delay is removed over a period of time during speech transmission by removing a segment of the delay line each time a pause of a specified length is detected in the speech. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
Bit 1 (MSB) T26
Bit 2 T24
Bit 3 T22
Bit 4 T10
Bit 5 T18
Bit 6 (LSB) T16
The output of the digital-to-analog converter 24 at pin D4-12 is fed through impedance matching amplifier B2 to the low pass filter B1. The output of the low pass filter B1 is further amplified in the second stage of amplifier B2 to provide the voice signal at output terminal 17. The circuit that controls scrambler from receive to transmit is scrambler control circuit 15. The scrambler keyline at terminal T34 is normally at some negative voltage, between -6 volts and -13 volts, and the scrambler control circuit places the keyline at ground when the scrambler is placed in the covered transmit mode (turned on). Referring now to FIG. 2B the 0 to 15 volt 8KHz square wave from FIG. 2A2 is fed to two decade counters 50 and 52 which divide the 8KHz signal twice down to 80Hz. The voice signal in an input terminal 54 is fed to the voice operated switch which consists of a threshold adjust 56, amplifier 58, and multivibrator 60. The VOX threshold adjust 56 should be adjusted for a -13dbm. The VOX output from terminal 10 of multivibrator 60 is applied to terminal 10 of NOR gate 62 and terminal 14 of NOR gate 64. When the VOX output is in the 1 state the output from NOR gate 64 is in a 0 state and the clock gate 70 is closed. When the VOX output shifts to a 0 state AND gate 70 is opened and the 80Hz square wave is applied to input terminal 1 of binary counter 72. Binary counter 72 divides the 80Hz signal by 16, providing a 5Hz square wave output at terminal 11. When the binary counter 72 output at terminal 6 goes through its negative transition, the first stage of the dual multivibrator 78 generates a positive pulse of 150 microsecond duration. As the trailing edge of this 150 microsecond pulse is generated, the second multivibrator stage 80 generates a positive pulse of the same duration. The output pulse from the second multivibrator stage 80 is the SHIFT pulse. The SHIFT pulse from multivibrator 80 is fed to shift gate 82. If the VOX output is 0 (no voice is present), and if no end of message has been recognized the SHIFT pulse is inverted in NAND gate 84 and passed through AND gate 86 to provide the SHIFT pulse for multiplexer 18. When the VOX output goes positive the output of NOR gate 62 goes to 0. This negative transition causes mulivibrator 63 to generate a pulse of 300 microsecond duration which appears at output terminals 6 and 7. The output pulse from terminal 7 is inverted in inverter 65 and is the INTERNAL RESET pulse that is applied to reset binary counters 72 and 73. This INTERNAL RESET pulse is also applied to scrambler control gates 75 and 77. The output pulse from terminal 6 of multivibrator 63 is fed to AND gates 81 and 83 to provide RESET PULSE ONE and TWO for multivibrator 18. If a reset is required the 300 microsecond pulse from terminal 6 of multivibrator 63 is also fed to reset turn-off latch 79 which will cause NOR gate 64 input 15 to change to a 0 state. When the VOX output is 0 the output of NOR gate 62 is a 1 and is fed to turn-off gate 85. Gate 85 is open when a 1 is present at pin 5. This permits any turn-off pulses to set turn-off latch 79. When turn-off latch 79 is set a 1 input is provided for NOR gate 64 which provides a 0 to pin 14 of clock gate 70. Therefore clock gate 70 is closed. When multiplexer 18 has reached stage 10 or higher, the STOP CODE control signal is generated and fed through input lead 87 and applies a 1 state signal to terminal 15 of STOP CODE GATE 89. Gate 89 is opened and permits the 5Hz output from binary counter 72 to enter binary counter 73. When binary counter 73 receives 8 consecutive positive transitions without being reset by the INTERNAL RESET (meaning no voice signal has appeared for 1.6 seconds), the output, pin 6, of counter 73 will go positive which causes multivibrator 86 to generate a positive pulse of 200 microseconds which appears at its output terminal 6. The output pulse from terminal 6 of multivibrator 86 is the STOP PULSE. The STOP PULSE is used to operate the scrambler control latches and shift control latch, which will be described in more detail below. The STOP PULSE from multivibrator 86 is also fed to reset the END OF MESSAGE LATCH (EOM). The Q bar output at terminal 4 of the EOM latch, 88, is fed to EOM CLOCK GATE 94. When a signal is received at EOM CLOCK GATE 75 input terminal 14 from EOM latch 88, gate 94 is opened and the 80Hz clock signal from counter 52 is applied to the input of EOM counter, 96. After the EOM counter, 96, receives 64 cycles of the 80Hz clock, which occurs after 800 milliseconds, the output at terminal 4 is a positive transition which is fed to and causes multivibrator 98 to generate a positive pulse of 200 microseconds duration which provides a TURN-OFF PULSE at terminal 10. When the EOM latch, 88, is reset, multiplexer reset control gate 91 is open. Therefore if a voice signal starts while the EOM latch, 88, is reset the resulting INTERNAL RESET PULSE is passed through multiplexer reset control gate 91 to the multiplexer 18. This signal places the multiplexer 18 in its extended reset state. In this state the digitized voice signal is delayed for 2.688 seconds, to allow the scrambler to pass its postamble and preamble prior to the delayed voice signal entering the scrambler. The TURN-OFF PULSE from latch 96 is also fed back as a reset pulse to EOM latch, 88. When the EOM latch, 88, is set, the EOM CLOCK GATE 94 is closed. This TURN-OFF PULSE also goes to turn-off gate 93 and the scrambler control gate 95. Both control gates 93 and 95 are controlled by scrambler control latch 97. If the turn-off gate 93 is open the TURN-OFF PULSE then will be fed to turn-off gate 85. If turn-off gate 85 is open (no voice signal present) the turn off pulse is fed to and sets turn-off latch 79. This provides a 1 state input to NOR gate 64 and a 0 state input to clock gate 70 which shuts off the 80Hz signal to binary counter 72. During the transmission of a message, a shift pulse is generated every 200 milliseconds during which no voice signal is present. This shift pulse will be transferred to multiplexer 18 if a message is in progress, an EOM signal has not occurred, and no voice signal is present when the shift pulse is generated. The shift pulse generated by multivibrator 80 will pass through shift gate 82 if the output of NOR gate 64 is in the 1 state (no voice present) and if the output from latch 88 is a 1 (no EOM signal). The shift pulse will pass through shift gate 86 if the Q output at terminal 4 of shift latch 99 is in the 1 state. Shift latch 99 will have been reset by the start of a message providing a MULTIPLEXER RESET PULSE. The recognition of an EOM causes the STOP PULSE to set shift latch 99 and thereby prevents shift gate 86 from passing the shift pulse to the multiplexer 18. When shift latch 99 is set, the multiplexer reset control gate 91 is opened. This allows the internal reset pulse to reset multiplexer 18 if the EOM latch, 88, is also set. The EOM latch, 88, is reset for 800 milliseconds following recognition of an EOM. During this period the INTERNAL RESET PULSE cannot reset the multiplexer. The shift latch 99 is returned to the reset state by the resetting of multiplexer 18 by either a RESET ONE or RESET TWO. This resetting pulse is the MULTIPLEXER RESET PULSE, previously described, which occurs only at the beginning of a message. At the start of a message, an INTERNAL RESET PULSE is generated by multivibrator 63. This pulse reaches scrambler control latch 101 through control gate 75 when the Q output at terminal 4 of the EOM latch, 88, is a 1 (at any time within 800 milliseconds after the STOP PULSE). This pulse sets the scrambler control latch 101 which turns on the scrambler by feeding an output signal to scrambler control circuit 15 (shown in FIG. 2-A). During the 800 milliseconds following recognition of the EOM scrambler control gate 75 is closed and scrambler control gate 77 is open. If a message starts during this 800 millisecond period, the internal reset pulse sets scrambler control latch 97 which opens scrambler control gate 95. The TURN-OFF PULSE which appears at the end of the 800 microsecond period, passes through scrambler control gate 95 and sets scrambler control latch 101 which turns on scrambler circuit C1-A (FIG. 2A). When the EOM is recognized the STOP PULSE from multivibrator 86 resets scrambler control latches 97 and 101 turning off scrambler control circuit 15. If no message starts within 800 milliseconds after the STOP PULSE, the TURN-OFF PULSE is passed through the open turn-off gate 93. Turn off gate 93 is opened by the reset state of scrambler control latch 97. This pulse is then provided to turn off gate 85. The purpose of multiplexer 18 is to control the parallel data streams into each of the 6 delay lines. The multiplexer controls the initial delay line feed point when a message begins by being reset in its normal mode (RESET ONE) or its extended mode (RESET TWO). The schematic of multiplexer 18 is shown in FIG. 2C. When a reset one pulse reaches the multiplexer it sets the RESET LATCH 1, 105, and is also fed through OR gates 107, 109 and is the MULTIPLEXER RESET PULSE. The reset pulse is fed to and resets all three of the dual 4-bit shift registers 111, 113, and 115, sets the STOP CODE LATCH 117, resets the SHIFT LATCH 99 (FIG. 2B), and sets the LAST STAGE LATCH 119. While the RESET LATCH 1, 105, is set, its terminals 5 and 3 are in the one state. The output of OR gate 121 then opens data gate 7 in each of the six delay lines. The output of OR gate 121 also provides a one state to the inputs or stage 8 of the multiplexer shift register. The first shift pulse occurring after a RESET ONE pulse will reset the RESET LATCH 1, 105, and clock all stages of the multiplexer shift register. The effect of the first shift pulse on the multiplexer output will be to close data gate 7 in each delay line and open data gate 8. The following shift pulse will cause the single open data gate in each of the delay lines to close and open the following gates. As each successive shift pulse occurs, the data gates will sequentially open and close until either the last gate (stage 22) is reached, or the message ends. The following message will provide a RESET ONE or a RESET TWO pulse. When a RESET TWO pulse reaches the multiplexer it sets RESET LATCH 2, 123, and also passes through the reset NOR gates 107, 109 to become the MULTIPLEXER RESET PULSE. While RESET LATCH 2, 123, is set, its output is a 1, data gate 22A in each delay line is open. The first shift pulse and each succeeding shift pulse after the RESET TWO pulse will have the same effect on the multiplexer described in the RESET LATCH 1 theory discussed above. The multiplexer shift register consists primarily of three dual 4-bit shift registers 111, 113 and 115 connected serially. Each output stage is applied to an inverter 127. As shown in the embodiment there are 22 stages in the multiplexer shift register. The output of only one of these 22 stages is in the 1 state at any time, permitting only 1 data gate in each delay line to be open. When the output of stage N of the pg,15 multiplexer shift register is 1, the corresponding inverter provides a 0 state to the read-write terminal of the N-1 stage of the delay line. When the multiplexer is reset, the output of either stage 1 or stage 7 of the multiplexer shift register is 1, depending upon which reset pulse occurs (RESET TWO or RESET ONE, respectively). When stage 1 is in the 1 state the digitized message is delayed for 2.688 seconds, allowing both the postamble and the preamble of the scrambler to be transmitted before the start of the message reaches the scrambler. When stage 7 is in the 1 state a delay of 1.92 seconds is used. This permits only the preamble of the scrambler to be transmitted before the start of the message reaches the scrambler. The purpose of the stop code circuit as described previously is to activate the end of message recognition circuit when a delay of less than 1.6 seconds exists. After the end of message recognition has been activated (STOP CODE GATE 89 is open and no voice signal appears for 1.6 seconds), a STOP PULSE will be generated and an end of message recognized. By ensuring that less than 1.6 seconds of delay remains when the end of message recognition circuit is activated, no digitized message can be skipped over in the delay lines when the STOP PULSE turns off the scrambler. When the output of multiplexer stage 10 is in the 1 state, STOP CONTROL GATE 129 is open. The next arriving SHIFT PULSE resets the stop code latch 117, if this latch is not already reset. When the stage 22 output of the multiplexer shift register at terminal 2 of shift register 115 goes to 1 state the LAST STAGE GATE 131 is open and the SHIFT PULSE which sets stage 22 of the multiplexer shift register to "1" passes through the LAST STAGE GATE 131 and resets the LAST STAGE LATCH 119. Further SHIFT PULSES are prevented from affecting the feed point of the delay lines and the read-write terminal of stage 21 of each delay line is held at 0. The next MULTIPLEX RESET PULSE to arrive after the LAST STAGE LATCH 119 has been reset will set it again. FIG. 2D shows the delay line. There are six identical parallel delay lines and each function in like manner. The data input is coupled through an inverter 135 and buffer 137 to gates 22a through 22n in parallel. When an extended reset is observed only data gate 22a is opened. Digital data is passed into delay line shift register stages 20a through 20n in each of the six parallel delay lines. Each delay line shift register stage is 1024 bits long. At a clock rate of 8KHz, the data stream which enters data line shift register 22a at input 10 of 20a will exit at terminal 6, 128 milliseconds later. Two clock pulses, phase 1 and phase 2, drive each delay line shift register stage. The clock pulses are approximatey a 2 microsecond, negative going transition from +4.5 volts to -11.4 volts at 8KHz. Clock phase 1 is leading clock phase 2 by 62.5 microseconds. Power is supplied through resistor network 139, 141, 143 shown in schematic form in FIG. 9. The next SHIFT PULSE causes the multiplexer to close data gate 22a and open data gate 22b. When data gate 22b is open the read-write terminal 7 of delay line shift register stage 20a is held at 0. This 0 state prevents the output of shift register stage 1 at terminal 6 from passing data to shift register stage 22b. This circuit is redundant as no information data should be in stage N when a SHIFT PULSE occurs to shift the input to stage N+1. The embodiment of the invention described uses a six-bit, parallel, analog-to-digital and digital-to-analog conversion technique with a conversion rate of 8000 per second. The principle of the invention also applies to any analog-to-digital and digital-to-analog conversion technique. The digital information, whether in serial or parallel configuration, can be delayed by the use of shift registers, and the feedpoint of the shift register(s) can be controlled by the occurrence of pauses in the speech in such a way as to bypass much of the "useless" digital information contained in the speech pauses. This bypassing need only occur long enough to make up for the delay incurred by the preamble transmission. The principle of the invention also applies to an analog delay line such as a series of capacitor-coupled devices (bucket brigade). The delay line could be made up of a series of analog shift registers. The feedpoint of such a delay line would be any one of the inputs to the individual stages of the delay line. This feedpoint could be controlled in the same manner as the preferred embodiment. The signal passing through the feedpoint, instead of six parallel bits, would be a series of analog voltages varying at the sampling rate required to reproduce the audio signal being delayed. Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.
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