Audio scrambling system for scrambling and descrambling audio signals5668879Abstract A scrambling system includes a scrambling apparatus and a descrambling apparatus for scrambling and descrambling digital audio codes having plural sub-band units. Each sub-band unit includes at least a scale factor and a quantized sample data which is quantized after scaling with the scale factor. In the scrambling apparatus, a sample period during which the quantized sample data is present is detected, and only the quantized sample data is scrambled at the sample period. In particular, the quantized sample data and data other than the quantized sample data are separated, and the separated quantized sample data is applied to a scrambler, and the other data is applied to a delay circuit. The separated and scrambled quantized sample data and the delayed data are synthesized. The descrambling apparatus also detects a sample period during which the quantized sample data is present, and descrambles only the scrambled quantized sample data at the sample period. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 1
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Inversion
control Sample
signal data Output of EX-OR
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0 0 0
0 1 1
1 0 1
1 1 0
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The full adder 212 then adds the sample data output from the exclusive-OR 211 and the inversion control signal corresponding to that sample data. The 16-bit data after being added with the one bit inversion control signal may result in overflow to produce a seventeenth bit, but the overflown seventeenth bit data will be ignored. To describe the operation of the level invertor 21, an example of the process inverting the sample data values is shown in FIG. 5. FIG. 5 shows sample data, each is 3-bit long and expressed by two's complement binary. The dynamic range in this example ranges from 101 (-3 in decimal) to 011 (3 in decimal). It is noted that the most-significant bit is used for expressing plus sign when it is "0", and minus sign when it is "1". In this inversion process, the median value of the dynamic range, i.e., the median between the maximum and minimum sample data values, is selected as the reference value against which each sample data value is folded. Because 000 is the median of the dynamic range in this example, the inversion process is referenced to 000. This is also true of the 16-bit coded two's complement binary code used in this embodiment. It is to be noted that the level invertor 21 may be configured in any way achieving an inversion process similar to that shown in FIG. 5, and shall not be limited to the configuration shown in FIG. 2. For example, a ROM (read-only memory) storing the inversion results as the outputs from each address may be used. By the process executed by the level invertor 21 of this embodiment, the result of inverting the sample data is output when the input inversion control signal is 1, and the input sample data is output without processing when the inversion control signal is 0. In other words, only the sample data specified by the inversion control signal is inverted from 0x0000, the median value of the dynamic range. Because audio sample data has a sign (positive or negative), the inverted sample data simply has the signs inverted, and the absolute value of the amplitude does not change. In addition, reserved code management relating to the reserved code 0x8000 can also be achieved. As a result, the data processed by the level invertor 21 does not end up with an abnormally high volume level, and reserved code management using 0x8000 as the reserved code can be applied. This effect can also be achieved when the scrambling apparatus 12 consists solely of an level invertor 21. A specific example of a 16-bit data is given below.
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(a) EX-OR 211 input:
1111 0110 0101 1010
(b) Inversion control signal:
1
(c) Ex-OR 211 output:
0000 1001 1010 0101
(d) Adder 212 output:
0000 1001 1010 0110
(e) EX-OR 211 input:
1111 0110 0101 1010
(f) Inversion control signal:
0
(g) Ex-OR 211 output:
1111 0110 0101 1010
(h) Adder 212 output:
1111 0110 0101 1010
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Items (a), (b), (c) and (d) show a case when the inversion control signal is "1", and items (e), (f), (g) and (h) show a case when the inversion control signal is "0". Adder 212 adds the inversion control signal and the exclusive-OR 211 output. Thus, items (c) and (d) differs only at the last two bits. As apparent to those skilled in the art, the signals at items (a) and (d) are two's complement binary. Operation of the scramble device 22 is described next. The inputs to the scramble device 22 are the sample data from the level invertor 21, and the 14-bit scramble control signal corresponding to the sample data. Before proceeding with the description of operation, the next-most-significant bit must first be defined. This "next-most-significant bit" refers to the highest order bit having a symbol differing from that of the most-significant bit. When the most-significant bit (MSB) value is [0], then the next-most-significant bit (NMSB) is the highest order bit with a value of [1] in the same sample data. For example, when the sample data is [0000 1011], which is equal to an amount "11" in the decimal system, it is noted that the first four zeros from the left do not positively participate in defining the number, but are there to merely fill in the places. Thus, the left four bits are referred to as meaningless bits and the right four bits are referred to as meaningful bits. It can be said that the next-most-significant bit is the most-significant bit in the meaningful bits, and in the above example, it is the fifth bit from the left. In the above example [0000 1011], if, after the scrambling process, any one or more of the four zeros from the left should turned to "1", then, the sample data would be increased greatly, resulting in abrupt loud sound. For example, if the received and scrambled signal should turn out to be [0100 1011], then, the amount "11" would be erroneously increased to "11+64", resulting in unexpected loud sound which is unpleasant to the listener's ear. One feature of the present invention is to prevent scrambling operation and eventually descrambling operation of the meaningless bits. For detecting the meaningless bits and meaningful bits, the present invention has a detector 221 for detecting the next-most-significant bit. According to the preferred embodiment of the present invention, not only the meaningless bits, but also the most-significant bit in the meaningful bits, which is called the next-most-significant bit, is also prevented from being scrambled and descrambled. Thus, according to the present invention, the detector 221 produces a masking signal, as shown in FIG. 6B, in which the portion corresponding to the meaningless bits plus the next-most-significant bit is aligned with Os for masking purpose, and the remaining portion is aligned with is for unmasking purpose that is for being subject to receive scrambling. In FIG. 6B, the first two bits from the left are not provided in the masking signal, because these two bits are always the bits which should not be scrambled and should always be masked. When the MSB is [1], the NMSB is the highest order bit with a value of [0] in the same sample data. In detector 221, the MSB is sequentially compared with each of the subsequent bits until the least-significant bit (LSB), and the first bit having a value different from that of the MSB is defined as the NMSB. Thus, in another 8-bit sample data [1111 0101] where the MSB is the first (left-most) bit with "1", the NMSB is the fifth from left bit. Because the closer the NMSB is to the MSB, the higher the sound level of the sample data, the NMSB may be said to control the sound level of the sample data. The detector 221 first detects the NMSB of the 16-bit sample data, generates a 14-bit masking signal wherein all lower-order bits than the detected NMSB are 1 for unmasking purpose, and all other bits are 0 for masking purpose, and then outputs the 14-bit masking signal. The format of the masking signal shall not be so limited, however, and can be any format wherein at least the NMSB and all higher order bits have a value of 0 for masking purpose. The masking signal is output from the detector 221 and input to the comparator 222 which also receives data from full adder 212. The comparator 222 compares the 16-bit reserved code (such as control code) and the 16-bit sample data, only at the masked portion, that is the two highest bits and the 0-value bit position of the masking signal. If all of the compared bits in the masked portion match, comparator 222 generates a process flag "0", indicating that the sample data resembles the reserved code so that scrambling should not be carried out with respect to the detected sample data. If the compared bits do not match, comparator 222 generates a process flag "1", indicating that the scrambling can be effected with respect to the detected sample data. The comparator 222 may store the reserved code(s) internally, or the reserved code(s) may be input from an external source, such as a reserved code memory 224 shown in FIG. 2. The audio signal, scramble control signal, masking signal output from the detector 221, and the process flag output from the comparator 222 are all input to the encryption device 223. The structure of the encryption device 223 is shown in FIG. 3. As shown in FIG. 3, the encryption device 223 comprises an exclusive-OR processor 31, a switching device 32, and an AND element 33. The masking signal and scramble control signal are input to the AND element 33, which performs a logical AND operation on the inputs and outputs the result. Thus, only the scramble control signal in the unmasked portion can path through AND element 33. If the process flag is `1`, the switching device 32 is enabled to directly output the input from the AND element 33. If the process flag is `0`, switch device 32 is disabled to cut off the data from the AND element 33, and instead produces a 14-bit `0` code. The exclusive-OR processor 31 then applies an exclusive-0R operation to the lowest fourteen bits of the sample data in accordance with the 14-bit output from the switching device 32, and outputs a 16-bit word of which the two highest bits are the two highest bits of the sample data, and the lowest fourteen bits are the 14-bit exclusive-OR result. Thus, the sample data is scrambled. A specific example of a 16-bit data is given below.
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(i) Detector 221 input:
1111 0110 0101 1010
(j) Masking signal: 00 0111 1111 1111
(k) Reserved code from 224:
1000 0000 0000 0000
(l) Process flag: 1
(m) Scramble control signal:
10 1011 1011 1110
(n) AND 33 output: 00 0011 1011 1110
(o) SW 32 output: 00 0011 1011 1110
(p) EX-OR 223 output:
1111 0101 1110 0100
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The same signal as the signal in Item (h) is used in Item (i). The reserved code in Item (k) and the scramble control signal in item (m) are selected merely as examples. The process flag is "1" because the input signal in Item (i) and the reserved code in item (k) do not match at the first upper five bits, i.e., the bits in the masked portion. Thus, it is understood that the input signal is not the reserved code, at all. AND element 33 outputs scramble control signal only in the unmasked portion, that is the lower eleven bits. Thus, the exclusive-OR operation by the exclusive-OR processor 31 is done only with respect to the lower eleven bits of the sample data. Note also that the encryption device 223 is not limited to the construction shown in FIG. 3. Any configuration using a DES, RSA, or other encryption method may be used insofar as the sample data at the `1` position of the masking signal is randomized or scrambled when the process flag is `1`. The process executed by the scramble device 22 described above is described below with reference to FIGS. 6A and 6B, which illustrate the process executed by the detector 221 of the scramble device 22 of the scrambling apparatus 12 of this first embodiment. Shown in FIGS. 6A and 6B are the sample data 61 and 62; next-most-significant bits 611 and 621; masking signals 612 and 622; masked portion 613 and 623; and unmasked portion 614 and 624. It is noted that the sample data 61 in FIG. 6A is the same as that shown in Item (i) above. When the sample data 61 is input to the detector 221, the NMSB 611, which is the highest order `0` bit in the sample data because the MSB is `1`, is detected. Next, a masking signal of which all bits lower than the NMSB 611 are `1`, i.e., the eleven bits to the right of the NMSB 611 in FIG. 6A, is output. The encryption device 223 later adds a random number only to those bits with a value of `1` in this masking signal. The bits to which the random number is added are shown in unmasked portion 614. As shown in FIG. 6B, the same process is executed for sample 62, as well as for the other sample data. The position of the NMSB in the sample data is therefore not changed by the randomization process applied by the detector 221 and encryption device 223. Because this NMSB controls the level of the sample data, no data change in any of the bits will take place in the masked portion during the scrambling. Thus, the volume of the sound will not become abnormally high when the processed audio signal is reproduced, and audio scrambling that does not result in an extremely unpleasant sound when reproduced can be achieved. Because in some modification, the position of the next-most-significant bit may be unchanged, it is also not necessary to transmit secondary data identifying the processed position, for example. In addition, this result can be achieved without the comparator 222 and the switching device 32 of the encryption device 223. FIG. 7 also shows the process executed by the comparator 222 of the scramble device 22 of the scrambling apparatus 12 according to the first embodiment. Shown in FIG. 7 are the reserved code 71; sample data 721 and 731; masking signals 722 and 732; and comparison positions 723 and 733. When the sample data 721 and the corresponding masking signal 722 are input, the comparator 222 compares the upper two bits and the bit positions where the masking signal is `0` in the sample data 721 and reserved code 71. In this example, the comparator compares the five high bits at comparison position 723. Because there is a mismatch in this case, the process flag is output with a value of "1", and the encryption device 223 thus adds a random number to the low eleven bits of sample data 721. When the sample data 731 and the corresponding masking signal 732 are input, the comparator 222 compares the sample data 731 of the position where the masking signal is `0` with the reserved code 71. In this example, the comparison compares the three high bits at comparison position 733. Because there is a match in this case, the process flag is output with a value of `0`, and the encryption device 223 does not add a random number to the sample data 731. By this process by the comparator 222 and the encryption device 223, sample data of which the bits at the comparison position match the reserved code 71 is not processed, the reserved code 71 is therefore not converted to another code, and other codes are not converted to the reserved code 71. Sample data of which the bits at the comparison position do not match the reserved code 71 are processed, but only the bits not in the comparison position are processed. As a result, the sample data and the reserved code remain different even after processing is completed, and the sample data is not converted to the reserved code. Moreover, the reserved code outside the dynamic range, and codes of which several bits from the MSB side are equal, are codes near the end of the dynamic range, and the frequency of these codes appearing is extremely low due to the characteristics of the digital audio signal. For example, the probability of the high four bits of the sample data matching the high four bits of the 0x8000 code is small. As a result, virtually all codes can, in practice, be encrypted, and safety (security) is not greatly impaired. It is to be noted that the reserved code is described as 0x8000 in this example, but shall not be so limited. When the reserved code differs from 0x8000, the comparator 222 is structured to similarly compare the selected reserved code with the sample data. As a result, reserved code management can be achieved with any selected reserved code. Furthermore, while only one reserved code has been used in the above description, the invention shall not be so limited. When plural reserved codes are used, all reserved codes are compared with the sample data. The process flag is set to `0` in this case if there is a match with any one of the reserved codes, and is set to `1` when no reserved codes match. This makes it possible to maintain reserved code management when plural reserved codes are used. In addition, the above processes have been described as applied to audio signals of plural sample data, but the invention shall not be so limited, and can be applied to any type of digital data comprising plural equal-length code words while still maintaining reserved code management. By the scramble device 22 thus described, an abnormally high sound level does not result after processing, sufficient security can be maintained, and reserved code management of any reserved code can be applied in the scrambling process. The level invertor 21 and scramble device 22 are connected for processing in the scrambling apparatus 12 of this embodiment, thus achieving a scrambling apparatus whereby an abnormally high sound level does not result after processing, reserved code management of any reserved code can be applied, and security can be enhanced by further combination of any appropriate apparatus. The operation of the descrambling apparatus 16 of this embodiment is described next. FIG. 4A is a block diagram of this descrambling apparatus 16. As shown in FIG. 4A, the descrambling apparatus 16 comprises a level invertor 21', scramble information allocation device 23', and descrambling device 42. Note that the level invertor 21' and scramble information allocation device 23' shown here operate identically to the level invertor 21 and scramble information allocation device 23 shown in FIG. 2. FIG. 4B is a block diagram of the de-randomizing device 42, comprising a detector 221', comparator 222', and decryption device 423. Note also that the detector 221' and comparator 222' operate identically to the detector 221 and comparator 222 shown in FIG. 3. In addition, note that the decryption device 423 performs the inverse of the encryption applied by the encryption device 223. The decryption device 423 for the encryption device 223 shown in FIG. 3 can be achieved by exactly the same operation and configuration as the encryption device 223. As shown above, the same part of the data scrambled by the scrambling apparatus 12 is inversely converted by the descrambling apparatus shown in FIGS. 4A and 4B, and the data can therefore be correctly decoded. By the present embodiment described above, a scrambling system can be provided whereby an abnormally high sound level does not result when scrambled audio information is reproduced; the security of the scrambled audio information can be sufficiently assured; and reserved code management of any desired reserved codes can be achieved. It should be noted that while the first embodiment above has the scramble device 22 provided after the level invertor 21 in the scrambling apparatus 12, and the level invertor 21' is provided after the descramble device 42 in the descrambling apparatus 16, the invention shall not be so limited, and the same effect can be obtained by reversing this order. In addition, it is possible to provide only one of these components and still obtain the same effect while simplifying the circuit construction. Furthermore, the embodiment comprises a comparator 222 and switching device 32 in both of the scramble device 22 in the descrambling apparatus 16 and the descramble device 42 in the scrambling apparatus 12, but the invention shall not be so limited. When there is no reserved code used, the comparator 222 and switching device 32 can be eliminated with no adverse effect on operation. In addition, this embodiment comprises a detector 221 in the scramble device 22 of the descrambling apparatus 16 and in the descramble device 42 of the scrambling apparatus 12, but the invention shall not be so limited. The detector 221 can be eliminated by using a fixed value or a value selected during use for the masking signal, in which case the change in the sound level will be held constant before and after scrambling, or the change can be controlled, and the circuit can be simplified. Reserved code management can, of course, be maintained in this case, too. The comparison position is also determined by the masking signal input to the comparator 222 in this embodiment, but if the NMSB of the reserved code is the second highest bit as in 0x8000, determination of the comparison position shall not be so limited and the comparison position may be fixed to the two highest bits. Why this is possible is described below. In a masking signal for sample data of which the two highest bits match the reserved code, all fourteen bits are set to `1`. The comparison by the comparator 222 therefore applies only to the highest two bits. For sample data of which the two highest bits do not match the reserved code, there will obviously be no match no matter how many bits are compared. Furthermore, because the encrypted bits are at most the low fourteen bits, this relationship can be maintained during the decrypting process, too. As a result, it is sufficient to only compare the two highest bits, and, in addition to the benefits described above, it is also possible to simplify the scrambling system. The scramble device 22 of the embodiment above is also described using a 14-bit masking signal of which all bits lower than the NMSB are `1` and all other bits are `0`, but shall not be so limited. It is also possible to randomize only the bits lower than the NMSB. As a result, the format of the masking signal may be any desired format, including a data format of which all bits lower than the NMSB are `0` and all other bits are `1`, and a data format indicating the position of the NMSB. In the first embodiment of the invention, when the reserved code matches the sample of the two highest bits and the `0` position of the masking signal, the process flag is set to `0`, but is otherwise set to `1` The invention shall not be limited, however, and the process flag may be any information identifying whether there is a match or mismatch between the reserved code and the bit sample of the position indicated by the masking signal as unencrypted. Because the encryption device 223 of the first embodiment described above may be any construction whereby the sample data of the position where the masking signal is `1` is randomized when the process flag is `1`, a different embodiment of the encryption device 223 shown in FIG. 3 is described below. FIG. 8A is a block diagram of an encryption device 223' which is a modification of that shown in FIG. 3, and applies block encryption. As shown in FIG. 8A, this encryption device 223 comprises a separator 81, block encryption device 82, and synthesizer 83. The audio signal, process flag, and masking signal are input to the separator 81, which outputs as processed data the data of the position where the masking signal is `1` when the process flag of the sample data is `1`, and outputs the remaining data as unprocessed data. The block encryption device 82 then encrypts and outputs the processed data. The synthesizer 83 then synthesizes the unprocessed data and the output from the block encryption device 82; this operation is controlled by inputting the process flag and the masking signal to the synthesizer 83 to inverse the operation of the separator 81. FIG. 8B is a block diagram of a decryption device 423' applying block encryption. As shown in FIG. 8B, this decryption device 423' comprises a separator 81', block decryption device 84, and synthesizer 83'. The operation of the separator 81' and synthesizer 83' are identical to those of the encryption device 223 described above, and is therefore omitted here. The block decryption device 84 essentially inverses the encryption process of the block encryption device 82. The same benefits can be obtained by these encryption device 223' and decryption device 423' as described above. The scrambling apparatus 12 and descrambling apparatus 16 of the first embodiment above have been described as processing 16-bit sample data, but the invention shall not be limited. When processing n-bit sample data, it is sufficient to simply adapt the process applied in 16-bit units above to n-bits. Furthermore, the scrambling system of the first embodiment above has been described as processing a digital audio signal of plural sample data units, but the invention shall not be limited and can be applied to any digital data signal of plural equal-bit-length code units. In such applications, reserved code management can still be maintained. SECOND EMBODIMENT The second embodiment of an audio scrambling system according to the invention is described below with reference to the accompanying figures. Shown in FIG. 9 is a block diagram of the audio scrambling system according to the second embodiment, comprising a digital audio generator 91, MPEG audio coding device 92, scrambling apparatus 93, transmission apparatus 94, transmission path 95, receiving apparatus 96, descrambling apparatus 97, MPEG audio decoding device 98, and digital audio processor 99. The operation of the scrambling system of this second embodiment is described below. The operation of the digital audio generator 91, transmission path 95, and digital audio processor 99 of this embodiment is identical to the operation of the digital audio generator 11, transmission path 14, and digital audio processor 18 of the first embodiment scrambling system above, and detailed description is omitted. The MPEG audio coding device 92 applies coding to data compress the digital audio signal output from the digital audio generator 91, and outputs the result as the MPEG audio. MPEG audio and the operation of the MPEG audio coding device 92 are described in further detail below. Next, the scrambling apparatus 93 scrambles the MPEG audio output from the MPEG audio coding device 92; the operation of this scrambling apparatus 93 is also described below. The output from the scrambling apparatus 93 is then transmitted by the transmission apparatus 94 over the transmission path 95, and is received by the receiving apparatus 96. The descrambling apparatus 97 then descrambles the MPEG audio signal. This descrambling apparatus 97 essentially reverses the scrambling operation of the scrambling apparatus 93, and is described in further detail below. The MPEG audio decoding device 98 then decodes the MPEG audio signal, and outputs the resulting digital audio signal. MPEG audio is described first. MPEG (Moving Picture Expert Group) is the common name of ISO-IEC/JTC1/SC2/WG11, the working group for international standardization of high efficiency coding methods for digital moving picture and audio signals. The MPEG audio signal is one data type coded according to this standardized method; there are three different methods known as Layer I, Layer II, and Layer III. The MPEG audio standard is specifically detailed in MPEG CD 11172-3 ("Coding Of Moving Pictures And Associated Audio For Digital Storage Media At Up To About 1.5 Mbit/s," part 3, Audio), the entire content of which is expressly incorporated by reference herein. The operation of an MPEG audio coding device generating a Layer I type MPEG audio signal is described briefly below. First frame data comprising plural sample data is converted into frequency domain and divided into plural sub-bands. The highest amplitude in each sub-band is then determined, and the sample data of each sub-band is scaled with this maximum amplitude. The data of the scaled sub-bands is then quantized to produce the quantized sample data. The bit allocation data identifying the number of quantization bits used for this quantization operation, the scale factors identifying the maximum amplitude of each sub-band, and the quantized sample data of each sub-band are then synthesized to produce the MPEG audio signal. The MPEG audio signal also contains header information containing the coding method and other data. In the actual coding of a Layer I MPEG audio signal, one frame contains 384 data samples (equivalent to 8 msec. at a 44.1-kHz sampling rate), and each frame is divided into 32 sub-bands. Each sub-band therefore contains twelve samples. The bit stream is generated by this bit allocation, scaling, and quantization process applied to all incoming data. The format of the bit stream of one Layer I frame of the MPEG-1 standard audio signal is shown in Table 2.
TABLE 2
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Bit stream format
for a Layer I MPEG-standard audio signal
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header 32 bits
error.sub.-- check
16 bit of 0 bit
allocation [ch] [sb]
(12) * 4 bits * 32
scale.sub.-- factor [ch] [sb]
(12) * 6 bits * (32 max)
sample[ch] [sb] [s]
(12) * (015 bit) * (12 * 32 max)
ancillary.sub.-- data
xbit
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(Note: indicates "through".)
In Table 2, allocation [ch] [sb] is the bit allocation information, scale.sub.-- factor [ch] [sb] is the scale factor, and sample [ch] [sb] [s] is the quantized sample data; `ch` indicates the channel; `sb` indicates the sub-band index, and is used to identify which sub-band the data corresponds to by appending a number to each sub-band; `s` is the sample index, and is used to identify which sample the data corresponds to by appending a number to each sample; `32 max` indicates that information is not transmitted when the bit allocation information (allocation [ch] [sb]) is `0`. FIG. 10 is a block diagram of the audio scrambling system according to the second embodiment of the invention. As shown in FIG. 10, this audio scrambling system comprises a separator 101, scrambling processor 102, synthesizer 103, period sample detector 104 and delay 105. The operation of this apparatus is described below. A Layer I MPEG audio signal is input to the separator 101 and also to the period sample detector 104. The period sample detector 104 detects a period.sub.-- sample in which the quantized sample data exists, and produces a HIGH level signal during the detected period.sub.-- sample, as shown in FIG. 13. The steps for detecting the period.sub.-- sample will be described in detail later in connection with FIGS. 14-18. The separator 101 separates the input signal into the quantized sample data (sample [ch] [sb] [s]) and data other than the quantized sample data (header, error.sub.-- check, allocation [ch] [sb], scale.sub.-- factor [ch] [sb], ancillary.sub.-- data) by the use of a period.sub.-- sample pulse from period sample detector 104; and outputs the separated components. The quantized sample data and the scramble information are input to the scrambling processor 102, which uses the scramble information to scramble the quantized sample data. Delay 105 is provided to delay the data other than the quantized sample data by a time period necessary for processing in the scrambling processor 102. Finally, the synthesizer 103 synthesizes the scrambled quantized sample data input thereto from the scrambling processor 102, and the data other than the quantized sample data input thereto from the delay 105 so that the quantized sample data is located in the same position as in the original signal, thereby generating the Layer I MPEG audio signal which is output therefrom. As shown in FIG. 13, the bit stream of layer I of the MPEG audio portion has a header in which layer, protection.sub.-- bit, mode and mode.sub.-- extension are present. The bit stream of the MPEG audio layer I further has an error.sub.-- check, allocation [ch] [sb], scale factor [ch] [sb], sample [ch] [sb] [s], and ancillary.sub.-- data. Next, the steps for making the period.sub.-- sample pulse, also shown in FIG. 13, will be described. Referring to FIG. 14, the following steps are taken. Step S1: 32 bits of header data is read and stored in "header". Step S2: (mode.sub.-- extension +1)*4 is stored in "bound". Step S3: It is detected whether the data in the mode is equal to b`11` or not. (Here, b`**` represents a binary expression.) Step S4: When the mode is not equal to b`11`, 2 is stored in "nch". Step S5: When the mode is equal to b`11`, 1 is stored in "nch". Step S6: It is detected whether the protection.sub.-- bit is equal to 1 or 0. Step S7: When the protection.sub.-- bit is equal to 0, 16 in the data stream bits are skipped. When the protection.sub.-- bit is equal to 1, no skipping is effected. Step S8: It is detected whether the data in the layer is equal to b`00`, b`01`, b`10` or b`11`. Step S9: Layer I process is carried out when the detected layer is equal to b`11`. Step S10: Layer II process is carried out when the detected layer is equal to b`10`. Referring to FIG. 15, the following steps are taken in the layer I process. Step S11: Allocation process is carried out. Step S12: Scale factor process is carried out. Step S13: Sample process is carried out. The description on the layer II process will be omitted, but it is noted that the period.sub.-- sample is extracted between the sample.sub.-- code and sample. Referring to FIG. 16, the following steps are taken in the allocation process S11 to exactly skip the bit stream length equal to the allocation area. Step S20: Allocation [ch] [sb] is repeated for a selected number of times determined by [sb] in which sb changes from 0 to ("bound"-1). Step S21: Allocation [ch] [sb] is repeated for a selected number of times determined by [ch] in which ch changes from 0 to ("nch"-1) while [sb] is taking a certain value. Step S23: Next four bits in the data stream is read and is moved to allocation [ch] [sb]. Thus, step S23 will be repeatedly carried out for "bound" x "nch" times. Step S24: Allocation [sb] is repeatedly carried out for a selected number of times determined by [sb] in which sb changes from "bound" to 31. Step S25: Next four bits in the data stream is read and is moved to allocation [0] [sb]. Step S26: The data in allocation [0] [sb] is copied to allocation [1] [sb]. Referring to FIG. 17, the following steps are taken in the scale factor process S12 to exactly skip the bit stream length equal to the scale factor area. Step S30: Scale factor [ch] [sb] is repeated for a selected number of times determined by [sb] in which sb changes from 0 to 31. Step S31: Scale factor [ch] [sb] is repeated for a selected number of times determined by [ch] in which ch changes from 0 to ("nch"-1) while [sb] is taking a certain value. Step S32: It is detected whether or not the allocation [ch] [sb] is equal to 0 or not. Step S33: When the allocation [ch] [sb] is not equal to 0, six bits in the data stream are skipped. Referring to FIG. 18, the following steps are taken in the sample process S13 to generate the period.sub.-- sample pulse. Step S40: The leading edge of the period.sub.-- sample pulse is defined. Step S41: Sample [ch] [sb] [s] is repeated for a selected number of times determined by [s] in which s changes from 0 to 11. Step S42: Sample [ch] [sb] [s] is repeated for a selected number of times determined by [sb] in which sb changes from 0 to ("bound"-1) while [s] is taking a certain value. Step S43: Sample [ch] [sb] [s] is repeated for a selected number of times determined by [ch] in which ch changes from 0 to ("nch"-1) while [s] and [sb] are taking a certain value. Step S44: Allocation [ch] [sb] bits in the data stream are skipped. Step S45: Sample [ch] [sb] [s] is repeated for a selected number of times determined by [sb] in which sb changes from "bound" to 32. Step S46: Allocation [0] [sb] bits are skipped. Step S47: The trailing edge of the period.sub.-- sample pulse is defined. In summary, to obtain the position of the quantized sample data, it is first determined from the header that the MPEG audio signal is an MPEG-1 Layer I signal. Then, the error.sub.-- check symbol is detected. The data size of scale factor [ch] [sb] and sample [ch] [sb] [s] is obtained from allocation [ch] [sb], and the position of the quantized sample data is obtained from this information. Note that the method of obtaining the position of the quantized sample data is not limited to the described method, and other methods may be used. For example, if the presence of the error.sub.-- check data is not variable, it is not necessary to use the protection.sub.-- bit in the header. FIG. 11 is a block diagram of the audio descrambling apparatus 97 according to the second embodiment of the invention. As shown in FIG. 11, the audio descrambling apparatus comprises a separator 101', period sample detector 104', descrambling processor 112, delay 105' and synthesizer 103' The operation of this apparatus is described below. The audio descrambling apparatus 97 is designed for processing a Layer I MPEG audio signal scrambled by the scrambling apparatus 93 shown in FIG. 10. The operation of the separator 101', period sample detector 104', delay 105' and synthesizer 103' is identical to the operation of those shown in FIG. 10, and further detailed description thereof is omitted below. The quantized sample data and the scramble information are input to the descrambling processor 112, which uses the scramble information to descramble the quantized sample data. The scramble information input to the descrambling processor 112 at this time is the same as the scramble information used to scramble the quantized sample data now being descrambled, and the descrambling operation of the descrambling processor 112 is the inverse of the scrambling operation of the scrambling processor 102. It should be noted that the scrambling method of the scrambling processor 102 of the audio scrambling system of the second embodiment, and the inverse of this operation applied as the descrambling method of the descrambling processor 112 of the audio descrambling system of the second embodiment, are not specifically defined herein. This is because the same effect can be obtained irrespective of the scrambling and descrambling method used insofar as the information is scrambled using a suitable scrambling technique, e.g., a block encryption method using the scramble information as the key, or an exclusive-0R operation on a random number where the scramble information is the random number, and descrambled using a process that reverses the scrambling process. Furthermore, the scrambling apparatus 102 and descrambling apparatus 112 are comprised to scramble or descramble only the quantized sample data using the separator 101 and synthesizer 103, but the invention shall not be so limited. If the scrambling apparatus is comprised to scramble only the quantized sample data and not scramble the other data, it may be comprised in various other ways, including using an encryption device for processing only that position identified by the detection data. By the second embodiment thus comprised, only the quantized sample data (sample [ch] [sb] [s]) is scrambled, and the scale.sub.-- factor is not changed by the scrambling process. As a result, the quantized sample data of each sub-band is randomized, but the maximum amplitude is retained when the data is decoded; an abnormal frequency component is therefore not produced, and the sub-band data does not become abnormally high. Moreover, the amplitude does not become abnormally high overall, and audio scrambling which does not create a sound that is excessively unpleasant to the ear can be achieved. The descrambling apparatus 97 descrambles the scrambled sample by reversing the scrambling process, and can thereby correctly reproduce the MPEG audio data scrambled by the scrambling apparatus 93. The audio scrambling system according to this second embodiment has been described with reference to a Layer I MPEG audio signal formatted as shown in Table 2, but the invention shall not be so limited and can be applied with a Layer II MPEG audio bit stream or other audio signal format comprising a header identifying the compression method and plural sub-band data units where each sub-band unit contains the bit allocation information, the scale factor, and a quantized sample data quantized with the number of bits identified by the bit allocation information after scaling by the scale factor. A different process must be used in audio coding a Layer II MPEG audio signal so that the coding efficiency is greater than the coding efficiency in Layer I audio coding, and a bit stream with a different format is produced. This bit stream format is the same as the Layer I bit stream format, however, in that it contains a header identifying the compression method and plural sub-band data units, and each sub-band unit contains the bit allocation information, the scale factor, and a quantized sample data quantized with the number of bits identified by the bit allocation information after scaling by the scale factor. Furthermore, any desired audio signal format comprising a scale factor and a quantized sample data scaled using this scale factor may be used, including: audio signals with no header information and a fixed coding method; and audio signals which contain no header information or bit allocation information, and in which the location of the quantized sample data is fixed in the bit stream. The same benefits can be obtained when such signals are processed insofar as the data separator is designed to separate the quantized sample data from the other data. In the audio scrambling system of the second embodiment described above, the separator 101 separates all quantized sample data from the other data, and the scrambling processor 102 and descrambling processor 112 process all quantized sample data. However, the separator 101 may be alternatively designed to separate quantized sample data of specific sub-band data units and the other data, and the scrambling processor 102 and descrambling processor 112 may be designed to process only the quantized sample data of specific sub-band data units. If the system is designed to process only the quantized sample data of sub-band data not in at least the high frequency band, data security will not be greatly impaired because at least the middle frequencies, which define the greatest part of the audio data, are randomized by the scrambling operation of the scrambling processor 102, as shown in FIG. 19. Referring to FIG. 19, Step S48 detects whether or not the present sub-band number [sb] is contained in a previously selected group U. If yes, the leading edge of the period.sub.-- sample pulse is defined at Step S49. If no, then no period.sub.-- sample is defined. Then, at Step S50, again it is detected whether or not the present sub-band number [sb] is contained in the previously selected group U. If yes, the trailing edge of the period.sub.-- sample pulse is defined Step S51, and if no, no period.sub.-- sample is defined. The same operations are carried out at Steps S52, S53, S54 and S55. In this manner, the period.sub.-- sample pulse is provided not to every sample data, but only to selected sample data that has the sub-band number [sb] contained in the previously selected group U. As a result, a scrambling apparatus whereby the unpleasant auditory effects of the scrambled audio are further reduced can be provided because no noise is generated in the high frequency band, and the descrambling apparatus will still be able to correctly restore the audio scrambled by the scrambling apparatus. It is also possible to control what sub-band data is processed by a control signal input from an external source. In this case, it is possible to control both the degree of auditory unpleasantness resulting from the scrambled signal, and the security of the signal. It is noted that the flow chart shown in FIGS. 14-19 is applicable not only to the period sample detector 104 in the scrambling apparatus 93, but also to the period sample detector 104' in the descrambling apparatus 97. The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
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