Encoding circuit and method of detecting block code boundary and establishing synchronization between scrambler and descrambler6385319Abstract The present invention comprises the bus reset detection circuit 6 detecting a bus reset signal from the network initiation/control state machine, the bus reset identification code generation circuit 8 and the bus reset identification code detection circuit 11 detecting a bus reset identification code and the bus reset signal generation circuit 16 which outputs a bus reset signal to the network initiation/control state machine. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
[EXPRESSION 1]
0 0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 1
1 0 1 0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0 0 0
T= 0 0 1 0 1 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0
0 0 0 0 1 0 1 0 0 0 0
0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 1 0 1 0 0
0 0 0 0 0 0 0 1 0 1 0
The establishing procedure of the synchronization between the scrambler register 23 and the descrambler register will be described below with reference to FIG. 13. The scrambler and the descrambler use the same signals as for a control signal and a main signal, the operation of establishing the synchronization between the scrambler and the descrambler is performed at the time of transmitting a control signal. In the case of being for synchronization between the scrambler and the descrambler, a train bit for adjusting the value of the descrambler register is set in the descrambler 15. In this case, the value of the descrambler register D(10:0) is expressed by the expression of D.sub.k+1 (10:0)=T.multidot.D.sub.k (10:0)+C. Here, C is expressed using a descrambler output S", Q" and a train bit by the expression of C=[0,0,0,0,S" and train,0,S" and train,0,Q" and train,0,Q" and train].sup.t. At the time of the initiation of the port, at first, a Request/Grant(S R Q P)=(0001) is inputted as a control signal, a train bit is set. Of this case, the variations of the values of a scrambler and a descrambler and descrambler outputs are shown in FIG. 14. At the time of CKL=0, for example, since the value of scrambler register is (10000000000) and the value of descrambler is (01001011111), suppose that the synchronization between the scrambler and the descrambler is not established. Therefore, the descrambler output (S" R" Q" P") is (0010), and this code is different from the inputted control signal (0001). Since a train bit is set and adjustments for descrambler register are added, the value of the descrambler are adjusted as CLK proceeds. At the time of CLK=5, the synchronization between a scrambler and a descrambler is established, both of register values is (10101001000), a descrambler output which is the same with an inputted code (0001) is obtained. Hereafter, as far as the same control signal being inputted, even in a state of a train bit being set, the synchronization is not lost. But in the case where the control signal is changed, the synchronization is lost, therefore, before the control signal is changed, a train bit is reset. Consequently, at the time of the completion of the initiation of port, a train bit was previously reset. However, even after the completion of the initiation of the port, since an error of a block boundary and loss of the synchronization between the scrambler and the descrambler due to the noises and the like may be generated, it is necessary to perform the detection of a block code boundary, setting of a train bit and the reestablishment of the synchronization between a scrambler and a descrambler even after the completion of the initiation of the port. In the prior art, codes are randomized on the transmitting side, in the case where an error of a block boundary and loss of the synchronization between a scrambler and a descrambler are generated, since a code of the transmitting side can not be recognized on the receiving side, an error of a block boundary and loss of the synchronization can not be detected. Therefore, a timing of performing the re-detection of a block boundary and the re-establishment of the synchronization between a scrambler and a descrambler after the completion of the initiation of the port is ambiguous. Moreover, in the case where an error of a block boundary and loss of the synchronization between a scrambler and a descrambler are generated, even if they can be detected, performing the procedure of the initiation of the port again means that changes (set/reset and reset/set) of a Port_Status signal are generated two times until the usual operation is restored. Specifically, it is not efficient since the initiation of the network and the arbitration of the transmitting speed must be performed two times. SUMMARY OF THE INVENTION It is an objective of the present invention to solve the problems described above. Moreover, the objective of the present invention is to provide a technology of an encoding circuit for the purpose of performing the re-detection of a block code boundary and the re-establishment of the synchronization between a scrambler and a descrambler without performing the procedure of initiation of the port in the case where an error of a block code boundary and loss of the synchronization between a scrambler and a descrambler are generated due to the noises and the like during the usual operation. An encoding circuit of the present invention for achieving the objective described above is characterized in that it comprises a bus reset detection circuit (reference numeral 6 of FIG. 1) detecting a control signal outputted from the network initiation/control state machine is a bus reset signal which performs the initiation of the network, a bus reset identification code generation circuit (reference numeral 8 of FIG. 1) generating a bus reset identification code for replacing a code of a first several clocks interval of a continuous bus reset signal, and still more for detecting a bus reset and a block code boundary on the receiving side, a bus reset identification code detection circuit (reference numeral 11 of FIG. 1) detecting a bus reset identification code and setting a train bit of a descrambler and a bus reset signal generation circuit (reference numeral 16 of FIG. 1) outputting a pseudo bus reset signal to the network initiation/control state machine during the re-establishment of the synchronization of a descrambler. An encoding circuit of the present invention is characterized in that it comprises a bus reset detection circuit (reference numeral 6 of FIG. 5) detecting a control signal outputted from the network initiation/control state machine is a bus reset signal which performs the initiation of the network and generating a trigger signal which performs re-detection of block code boundary, a block code boundary detection circuit (reference numeral 12 of FIG. 5) setting a train bit after the re-detection of block code boundary and a bus reset signal generation circuit (reference numeral 16 of FIG. 5) outputting a pseudo bus reset signal to the network initation/control state machine during the re-establishment of the synchronization of the descrambler. According to the present invention as described above, the re-detection of a block code boundary and the re-establishment of the synchronization between a scrambler and a descrambler can be performed, and by an acknowledgment that a bus reset is outputted from the transmitting side using a signal which is not randomized to the receiving side, the initiation of the network and the initiation of the serial port can be performed at the same time using a bus reset signal performing the initiation of the network. BRIEF DESCRIPTION OF THE DRAWINGS This and other objectives, features and advantages of the present invention will become more apparent upon a reading of the following detailed description and drawings, in which: FIG. 1 is a block diagram showing an encoding circuit of the first embodiment of the present invention; FIG. 2 is a block diagram showing operations of nodes having encoding circuits of the present invention; FIG. 3 is a diagram showing examples of outputs of each functional block of the transmitting block; FIG. 4 is a diagram showing examples of outputs of each functional block of the receiving block; FIG. 5 is a block diagram showing an encoding circuit of the second embodiment of the present invention; FIG. 6 is a diagram showing a basic constitution and its connecting configuration of nodes; FIG. 7 is a flowchart showing the procedure of the initiation of the serial port; FIG. 8 is a list showing control signal codes and their significance; FIG. 9 is a block diagram showing a conventional transmitting/receiving section of a serial port; FIG. 10 is a list of conversion describing an operation of 4B/10B conversion; FIG. 11 is a diagram showing a constitution of a shift register which is used in the scrambler and the descrambler; FIG. 12 is a diagram showing the relationship (operation of scrambler) between a scrambler register and a main code or between a scrambler and a control code; FIG. 13 is a diagram showing the relation between a scrambler and a descrambler; and FIG. 14 is a list describing an example of an operation of a descrambler. DESCRIPTION OF THE EMBODIMENTS Next, the embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an encoding circuit of the first embodiment of the present invention. In FIG. 1, an encoding circuit is broadly divided into two (2) sections, the transmitting block 18 and the receiving block 19. The transmitting block 18 is composed of the selector A1, the scrambler 2, the 8B/10B conversion circuit 3, the 4B/10B conversion circuit 7, the selector C4, the parallel/serial conversion circuit 5, the bus reset detection circuit 6, the bus reset identification code generation circuit 8 and the selector B9. On the other hand, the receiving block 19 is composed of the serial/parallel conversion circuit 10, the block code boundary detection circuit 12, the 10B/8B conversion circuit 14, the 10B/4B conversion circuit 13, the descrambler 15, the bus reset identification code detection circuit 11, the bus reset signal generation circuit 16 and the selector D17. The selector A1 has a function of switching back and forth between a control signal and a main signal for the purpose of using a common scrambler by a control signal and a main signal. The scrambler 2 has a function of randomizing a data sequence of control signals or main signals. The 8B/10B conversion circuit 3 has a function of converting a main signal of 8 bits into a code of 10 bits. The 4B/10B conversion circuit 7 has a function of converting a control signal of 4 bits into a code of 10 bits. The bus reset detection circuit 6 has functions of detecting a bus reset signal in a control signal and outputting a signal of the purpose of switching the selector B9. The bus reset identification code generation circuit 8 has a function of generating a special code which is not used in a control signal and a main signal used for the purpose of detecting a bus reset signal on the receiving side. The selector B9 has functions of usually outputting a signal from the 4B/10B conversion circuit 7 and outputting a signal from the bus reset identification code generation circuit 8 for several clocks interval after a bus reset signal is detected by the bus reset detection circuit 6. The selector C4 has a function of switching back and forth between a main signal and a control signal. The parallel/serial conversion circuit 5 has a function of converting a parallel signal of 10 bits into a serial signal. The serial/parallel conversion circuit 10 has a function of converting a serial signal from the transmission path into a parallel signal. The block code boundary detection circuit 12 has functions of detecting a boundary of a block code (for example, a code of 10 bits) and outputting a parallel signal in a block unit from a boundary to another boundary after the detection of a boundary. The 10B/8B conversion circuit 14 has a function of converting a block code of 10 bits which is a main signal into a code of 8 bits. The 10B/4B conversion circuit 13 has a function of converting a block code of 10 bits which is a control signal into a code of 4 bits. The bus reset identification code detection circuit 11 has functions of detecting a bus reset identification code, setting a train bit, and furthermore, outputting a signal for the purpose of switching the selector D. The descrambler 15 has a function of converting a code randomized on the transmitting side into the original code which is not randomized. The bus reset signal generation circuit 16 has a function of generating a bus reset signal (0101) as a control signal. The selector D has a function of switching back and forth between an output of a descrambler and an output of the bus reset signal generation circuit. Suppose a constitution that two nodes, the node A and the node B as shown in FIG. 2, are connected by a serial port. The port C has a transmitting/a receiving block shown in FIG. 1. During the usual operation, due to the noises and the like, an error of a boundary in the block code boundary detection circuit 12 within the receiving block 19 or loss of synchronization of the descrambler 15 (for example, the node A1 of FIG. 2) is generated. In this case, since a main signal and a control signal outputted from the descrambler are different from signals which are expected, they are not processed by the network initiation/control state machine 21 of an upper layer. Specifically, the network initiation/control state machine 21 stops operation and becomes in a state of being locked(2). In the case where the locked state of the network initiation/control state machine 21 is continued more than a certain period of time (according to the IEEE 1394-1995, MAX_ARB_STATE_TIME=166.8us), the network initiation/control state machine 21 outputs a bus reset signal (0101) as a control signal for performing the initiation of the network(3). In the node A, the bus reset detection circuit 6 which has detected a bus reset signal outputted from the network initiation/control state machine 21 outputs a signal for several clocks interval (for example, 6 clocks interval) for the purpose of switching an output of the selector B9 from an output of the 4B/10B conversion circuit 7 to an output of the bus reset identification code generation circuit. The bus reset identification code generation circuit 8 generates and outputs a block code which is not used in a control signal and a main signal (for example, a code of 20 bits which alternately transmits two codes of K28.5+=0011111010 and K28.5-=1100000101). A bus reset identification code is serialized and outputted from the serial port without being randomized by the scrambler. An appearance of a signal in each interface of the transmitting block is shown in FIG. 3. In the case of a bus reset being generated, a bus reset signal (0101) is inputted as a control signal. Since a bus reset signal is randomized, a scrambler output and a 4B/10B conversion output do not have any regularities. When a control signal is changed into a bus reset signal, a bus reset detection circuit output is changed from "L" to "H", and after a certain period of time (for example, 6 clocks interval), changed from "H" to "L" again. A bus reset identification code is outputted from the selector C only for a certain period of time (for example, 6 clocks interval). A bus reset signal from the node A is inputted into the node B by way of the transmission path(4). In the receiving block 19 of the node B, a received serial signal is converted into a parallel signal by the serial/parallel conversion circuit 10, the detection of the coincidence with a bus reset identification code is performed by the block code boundary detection circuit 12, and a boundary of a block code is recognized again. Moreover, by the bus reset identification code detection circuit 11, a bus reset identification code is detected, and concurrently with a setting a train bit of the descrambler, an output of the selector D17 is switched from an output of the descrambler 15 to an output of the bus reset signal generation circuit 16. The descrambler 15 identifies an output of itself, in the case where a bus reset signal in series (0101) are detected, resets a train bit, and switches an output of the selector D from an output of the bus reset signal generation circuit 16 to an output of the descrambler 15. An appearance of a signal in each interface of the receiving block is shown in FIG. 4. When a bus reset identification code (for example, a code of 20 bits of K28.5+ or K28.5-) is detected in a serial/parallel conversion output, a bus reset signal (0101) is outputted as a control signal output by switching an output of the selector D to the side of the bus reset signal generation circuit concurrently with a train bit being changed from "LB" to "H". When the value of a descrambler output is locked (for example, 3 clocks in series) by a bus reset signal (0101), an output of the selector D is switched to the side of the descrambler as well as a train bit is changed from "H" to "L". The network initiation/control state machine 21 of the node B detects a bus reset signal from the node A (5) and transmits a bus reset signal for the purpose of starting the initiation of the network (6). A serial bus reset signal to which a bus reset identification code is added is outputted from the transmitting block of the node B by the operation similar to that of the transmitting block of the node A and inputted into the node A by way of the transmission path (7). The receiving block of the node A which receives a bus reset signal from the node B performs the re-detection of a block code boundary and the re-establishment of the synchronization between a scrambler and a descrambler and completes the initiation of the port during the bus resetting. Next, the second embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a block diagram showing an encoding circuit of the second embodiment of the present invention. In FIG. 5, an encoding circuit is broadly divided into two (2) sections of the transmitting block 18 and the receiving block 19. The transmitting block 18 is composed of the selector A1, the scrambler 2, the 8B/10B conversion circuit 3, the 4B/10B conversion circuit 7, the selector C4 and the parallel/serial conversion circuit 5. The receiving block 19 is composed of the serial/paallel conversion circuit 10, the block code boundary detection circuit 12, the 10B/8B conversion circuit 14, the 10B/4B conversion circuit 13, the descrambler 15, the bus reset signal generation circuit 16 and the selector D17. The selector A1 has a function of switching back and forth between a control signal and a main signal for the purpose of using the common scrambler by a control signal and a main signal. The scrambler 2 has a function of randomizing a data sequence of control signals or main signals. The 8B/10B conversion circuit 3 has a function of converting a main signal of 8 bits into a code of 10 bits. The 4B/10B conversion circuit 7 has a function of converting a control signal of 4 bits into a code of 10 bits. The bus reset detection circuit 6 has functions of detecting a bus reset signal in a control signal and outputting a trigger signal performing the re-detection of a block code boundary, and furthermore, outputting a signal for the purpose of switching the selector D9. The selector C4 has a function of switching back and forth between a main signal and a control signal. The parallel/serial conversion circuit 5 has a function of converting a parallel signal of 10 bits into a serial signal. The serial/parallel conversion circuit 10 has a function of converting a serial signal from the transmission path into a parallel signal. The block code boundary detection circuit 12 has functions of detecting a boundary of a block code (for example, a code of 10 bits) and outputting parallel signals in a block unit from a boundary to another boundary after the detection of a boundary, and furthermore, setting a train bit after the detection of a block code boundary. The 10B/8B conversion circuit 14 has a function of converting a block code of 10 bits which is a main signal into a code of 8 bits. The 10B/4B conversion circuit 13 has a function of converting a block code of 10 bits which is a control signal into a code of 4 bits. The descrambler 15 has a function of converting a code randomized on the transmitting side into the original code which is not randomized. The bus reset signal generation circuit 16 has a function of generating a bus reset signal (0101) as a control code. The selector D has a function of switching back and forth between an output of the descrambler and an output of the bus reset signal generation circuit. In the first embodiment of the present invention described above, a method that a first several clocks interval of a bus reset signal is replaced by a special code and transmitted so that the bus reset signal can be detected on the receiving side and the detection of a boundary of a block code and the re-establishment of the synchronization between a scrambler and a descrambler are performed by detecting this special code on the receiving side of the opposed node is employed. However, in the case where a bus reset signal was detected on the transmitting side, the problem of the prior art can be solved as well by the means that a trigger signal performing the re-detection of a block code boundary is outputted to the receiving side within the same node and a trigger signal performing the re-establishment of the synchronization between a scrambler and a descrambler is outputted after the re-detection of a block code boundary. Suppose a case that two (2) nodes of the node A and the node B having an encoding circuit of FIG. 5 are connected each other as in FIG. 2. In the node A, the bus reset detection circuit 6 which has detected a bus reset signal from the network initiation/control state machine 21 outputs a trigger signal for the purpose of starting the re-detection of a block code boundary and outputs a signal for the purpose of switching an output of the selector D17 to an output of the bus reset signal generation circuit 16. Moreover, a bus reset signal from the network initiation/control state machine 21 is randomized by the scrambler 2, and after this signal is block-encoded by the 4B/10B conversion circuit 7, this signal is converted into a serial signal and transmitted as a serial signal. The node B which has received this serial signal detects a bus reset signal and the network initiation/control state machine of the node B outputs a bus reset signal as a control signal. This bus reset signal is transmitted to the node A and converted into a parallel signal by the serial/parallel conversion circuit. In the block code boundary detection circuit 12 of the node A, the detection of a boundary is conventionally performed by detecting the coincidence with a control code C4 (=0010001111) or C11 (=1101110000). The block code boundary detection circuit 12 sets a train bit for the purpose of performing the re-establishment of the synchronization between a scrambler and a descrambler after the completion of the detection of a boundary. In the case where a stable (locked) bus reset code (for example, 3 clocks in series) from the descrambler 15 is obtained, a train bit is reset, an output of the selector D17 is switched to an output of the descrambler. According to an encoding circuit of the present invention described above in detail, even in the case where an error of a boundary of a block code and loss of the synchronization between a scrambler and a descrambler are generated after the initiation of the port due to the noises and the like, the initiation of the port, specifically, the re-detection of a block code boundary and the re-establishment of the synchronization between a scrambler and a descrambler concurrently with the initiation of the network can be performed. The entire disclosure of Japanese Patent Application No. 9-339036 filed on Dec. 9, 1997 including specification, claims, drawings and summary are incorporated herein by reference in its entirety.
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