Method and apparatus for secure transmission of video signals5555305Abstract Video signals are sampled at 4Fsc locked onto sub-carrier phase and frequency. The active picture lines of each field are divided into 6 blocks of 47 lines and the active line periods of those lines scrambled on a block by block basis by line order shuffling. The shuffling algorithm is generated by a line shuffling permutator driven by a PRBS generator (controls 36, 38). Active line period samples for one block are written in unscrambled form into a first memory block (32) and samples from the previous block are read out in scrambled form from a second memory block (34) for transmission. The complementary process takes place in the decoder. Claims We claim: Description FIELD OF THE INVENTION
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line no function
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623 2nd half- 23 2nd half
vertical blanking interval
311-335
23 2nd half, 310, 622,
blanked by encoder
623 1st half
24-27, 336-339 Videocrypt data
28-209, 340-621 carries active line parts scrambled
in 47 line blocks.
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Scrambling of lines within a block is effected by permuting the order of transmission of the lines within each block. The control word for the permutation generator changes from block to block according to the output of a pseudo-random binary sequence generator PRBS. The PRBS is preferably initialised once every TV picture according to a 20 bit seed value. Thus 12 values are generated by the PRBS each picture, one for each block. Because in the PAL system colour information is transmitted in phase relation between the burst and the active video subcarrier a very stable phase locked loop PLL is required. Active line periods are replaced by shuffled lines and chrominance noise will be present if there is any significant error. Permissible errors in timing are less than 1.5 nS which corresponds to a error of about 2.degree.. The required accuracy is helped by measuring phase error only during those lines with a colour burst (lines 7 to 309 and 320 to 621). The phase lock loop will be described in detail later in the description. Referring now to FIG. 4, the operation of the codec may be best understood by consideration of an experimental coder which does use a PRBS and permutation generator as store controller, producing direct and permutated address sequences as required. The architecture of the coder and decoder is necessarily almost identical, the major difference being that the line and field blanking intervals are delayed in the coder but not in the decoder and although the following description is directed to the coder the decoder operates in the same manner. To be compatible with conventional terrestrial transmitting standards the scrambled picture is transmitted as an analog signal. The received scrambled signal is first converted into digital format by analog-to-digital convertor 20. The ADC is regulated by a clock pulse generator CPG 22 to sample the received signal at 4F.sub.sc. The ADC and DAC in the decoder uses 8 bit video samples. The clock pulse generator is frequency and phase locked to the colour burst signal sampling at 45.degree. points as described previously. A suitable clock pulse generator is a voltage controlled crystal oscillator VCXO producing on 8F.sub.sc signal together with a divide-by-two circuit to produce an output signal at 4F.sub.sc with a 1:1 mark-space ratio. The ADC may be based on a TRW TDC 1007 ADC which can operate at frequencies up to 25 MHz. The coder ADC is a 10 bit ADC which is the standard for professional equipment. Stabilisation of the frequency and phase of the master clock signal relative to the colour burst of the sub-carrier is performed internally in the c.p.g. 22. A sync. separator 24 produces the necessary timing signals associated with the video wave form such as mixed sync. line pulses and identifies odd and even blocks. The output of the ADC is input in parallel to a blanking delay unit 26 which delays the blanking interval and to data inserter 28 which also receives the delayed output from the blanking delay 26. The data inserter 28 has an output directly to output Digital to Analog Convertor DAC 30 and also to 47 line stores A and B 32, 34. The stores are controlled by respective store controls 36, 38 which are controlled by clock and sync. signals provided by the sync. generator. The store controls control the reading and writing of data from and to the respective memory store and are provided with the scrambling sequence. The store controls comprise a PRBS generator and a permutation generator. The blanking delay element 26 of the coder is illustrated in greater detail in FIG. 10. The delay performs two functions: firstly, it provides a 125 line delay for the samples corresponding to the vertical and horizontal blanking; secondly it provides a variable delay for the samples comprising the active line periods of the active picture lines. This latter feature enables the shuffling to be performed with only two blocks of memory. FIG. 10 shows how a switchable delay 500 of 0, 1, 31 and 125 lines delay time is used for the 47 line block structure. The blanking delay 500 takes in the video from the ADC and passes it on directly or delays it by approximately 1, 31 or 125 lines; the exact delays required are 1135, 35187 or 141,877 samples. The delay is selected by two control lines d1 and d0 according to the following:
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d1 d0 delay
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0 0 0
0 1 1135
1 0 35187
1 1 141877
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An additional fixed delay for pipelining can be added to all the outputs without problem. The delay has to change on a sample by sample basis. Since all the delay values are odd, the delay could be achieved by demultiplexing by two into two 128k.times.8 static RAM devices. Thus each device would only be required to read or write in a clock period, with a corresponding relaxation of timing. If the samples are numbered 0 to 1134 on each line (except lines 312 and 624, which are numbered 0 to 1136), then samples containing the sync and burst waveforms, 1117 to 171, are always taken from the 125 line delay address. This delay is also used during the VBIs (lines 622 to 27 and lines 310 to 339) for samples 172 to 1116. The active samples 172 to 1116 of the lines from delay, those of Blocks 6 and 7 (lines 340 to 386 and 387 to 433) are taken with a 1 line delay, whilst all the other blocks are taken with a 31 line delay. FIG. 11 shows how the blanking delay operates in the coder to ensure that the VBI period is the correct number of lines, 30 or 31. FIG. 12 shows how the 4F.sub.sc samples are arranged with respect to each other around lines 624 and 312 which are the long 1137 sample lines. The scrambler coder operates by allowing incoming line and field blanking signals to pass straight through to the DAC to the output. The remaining active portions of the active lines (955 samples) are stored in the stores 32, 34. The first block, block 0 of FIG. 1(b) is stored in store 32 and the next block, block 1 is stored in block 34. It is important to note that the samples are stored in the stores in clear; that is in unscrambled form. As the lines of block 1 are being stored in store 34, the lines of block 0 are read out from store 32 under the control of control 36 in scrambled form. Thus, the read addressing is scrambled but the write addressing is in clear. When block 1 has been written into store 34 block 0 will have been read from store 32 and block 2 can be written, again in clear, to store 32 while block 1 is read from store 34. The output of the two stores is fed into DAC 30. The critical timing described previously is such that the scrambled active line portions are re-inserted into the unscrambled blanking intervals with a minimum degree of error. The descrambler operates in a complementary fashion. During each picture, the active picture lines of incoming scrambled video are written to either the "A" or "B" store in descrambled order using the same sequence of addresses as in the scrambler. As in the coder, the line order is provided by a PRBS and permutation generator which comprise Store Controls 36, 38 to produce the memory addressing and control signals. This effectively descrambles the incoming video signal. At the same time, samples written to the other store during the previous block are read out to the DAC to produce a descrambled output signal. Once again the two RAM stores swap between the writing and reading functions on alternate blocks. It is important to note that at the coder the scrambled active picture line output signals are delayed at the stores relative to their own line syncs and colour bursts. Similarly, in the decoder the output descrambled signal is delayed relative to the syncs and burst of the received scrambled signal in the stores. Synchronisation is achieved by delaying the blanking intervals appropriately in the coder. The stores used in the encoder and decoder may conveniently be 10 and 8 bit dynamic RAMs respectively. SRAMs or VRAMs may also be used. The DAC may be a 10 bit (encoder) or 8 bit (decoder) device for example a TRW TDC 1016 J which can operate at speeds of up to 20 MHz. Referring now to FIG. 5, the digital portion of a production decoder is illustrated. The corresponding encoder is substantially identical. An incoming scrambled video signal is first digitised in an ADC (not shown) and then fed to the phase lock loop 100, the Data retriever 110 and a multiplex and delay line 120. The data retriever 110 retrieves the Videocrypt data transmitted on lines 24-27 and 336-339. The mux and delay line is required to support the memory 160 which is a VRAM. The retrieved data is fed to the system CPU 130 which also interfaces with control logic 140 and PRBS 150. The control logic manages the timing of all elements of the system, with the exception of the memory 160 and delay line 120. The control logic is supplied with the system clock at 4F.sub.sc and horizontal and vertical sync. signals HSY and VSY. The memory 160 comprises two 47 line blocks which operate in the manner described in the previous example. Memory management 180 controls the read and write addressing and is described in greater detail with reference to FIGS. 7 and 8. The memory management is controlled by the permutation generator 190, itself under the control of PRBS 150 the PRBS and permutation generator are shown in greater detail in FIGS. 14a)-c) and 15. The construction of the permutation generator and the PRBS may be of any desired form and is well documented in the art. The memory again stores the active line period data in clear and the output is multiplexed back onto the unscrambled portions of the signal. Prior to D-to-A conversion and output the back porch of the signal is re-inserted at 200. The black level reinsertion circuit is shown in more detail in FIG. 6. The back porch reinsertion is necessary in the decoder to ensure that clamps in circuitry downstream have a clean backporch for clamping. If this is not done in a line shuffling system, transmission impairments such as multipath can cause the clamping process to introduce streaky noise. The colour burst is passed on to the PAL decoder in the receiver without modification so that automatic colour correction circuits, which measure the amplitude of the burst, operate correctly and is easier than generating a new burst. In FIG. 6 back porch reinsertion is performed using digital filtering techniques. The input video signal is fed through a chrominance band pass filter 400, to the output of which is added the prescribed black level value of 64 in adder 410. This signal is selected during the back porch by a control signal from the sync. separator which operates on multiplexer 420. The multiplexer has as its other input the digital video input delayed by compensating delay line 430 by the signal path delay through the filter 400 and adder 410. The delayed video is selected in the multiplexer at all times except the back-porch interval. FIGS. 4 and 5 have been described with reference to a 47 line block size. Suitable modification would be neccessary for the 56/59 line example referred to previously or any other block size and will be clear to one skilled in the art. FIG. 7 shows the write address circuitry for the decoder required to write a scrambled signal in clear in the memory. The circuit shown is suitable for a 56/59 line block size. FIG. 8 shows the read address circuitry for the decoder which reads from the memory to provide the output to a MUX 120 in FIG. 5. In this example the circuitry is suitable for a 56/59 line block structure to illustrate the additional circuitry required to cope with blocks of different sizes. Referring to FIG. 7 the 20 bit control word CW vis fed from the CPU to the PRBS 150 which controls the output of the line permutation generator 190. The generator 190 provides a six bit output to the address translator 210. As unequal block sizes are used 3 blocks overlap in the decoder as well as the encoder. The address translator moves the overlapping parts to an otherwise unused area of RAM. A block counter 220 steps from 0 to 4 and produces a shift input to the address translator to ensure that address are provided for the alternate block after each block of 47 lines. An odd/even counter 230 having an input from the block counter provides a 1 bit output to switch between memory blocks 32, 34 (FIG. 4) which is necessary as there is an uneven number of blocks per field. The 56/59 block example may operate with the two blocks of memory being field stores, in which case the odd/even counter can be clocked from the field pulse. As block size changes counter 220, which steps from 0 to 4 must provide a signal to the generator 190 that the block size increases to 59 lines for the 4th block. FIG. 8 shows how the odd/even counter 230 may be clocked in the 56/59 line example. A counter 340 steps between 0-55 and 0-58 depending on block size and provides an output to the address unit 310. The counter is cleared by a high output from OR gate 350 which has field pulse and end of block inputs. The end of block pulse is provided when the six inputs to either AND gate 360 or AND gate 370 go high, indicating that the count has reached 55 or 58 respectively. These outputs provide the input to OR gate 380 whose output is the `end of block` pulse. The output of gate 380 is also used to clock the block counter 320, which, in this instance, steps between 0-4. The remainder of the circuitry operates as described with reference to FIG. 7. The digital phase lock loop is shown in FIG. 13. The ADC, clock generator and sync. separator are referred to by the same references as FIG. 4. The digital output of ADC 20 is fed to a multiplier (controller generator) 600 which receives as its other input a pulse train at F.sub.sc derived from the 4F.sub.sc clock and a divide by four logic unit 610. The output from the multiplier is passed to a 32 byte accumulator 620, a two line averager 630 a limiter 640, pulse width modulator 650 and loop filter 660 which supplies a control voltage to the voltage controlled crystal oscillator of the clock pulse generator 22. The accumulator 620 and 2 line averager 630 are controlled by burst gate signals from the sync. separator 24. The accumulator 620 both adds and subtracts two succesive bytes, calculating 32 samples for each burst, corresponding to samples 11 to 42 in FIG. 3. The samples are taken from the middle of the burst. The averager determines the phase error of the PLL summing the accumulator output over the previous 2 lines and retaining the information for one line. The accumulator 640 reduces the dynamic range of the signal so that quantisation to eight bits is sufficient. The pulse width modulator 650 produces a binary sequence whose average corresponds to the measured error. The PWM 650 may alternatively be a pulse density modulator, a rate multiplier or a DAC. The digital burst phase detector may be implemented in a number of different ways and the embodiment illustrated is just one example. The sync. separator may be analogue or digital or a combination of the two. The control logic 140 in FIG. 5 and the sync separator 24 in FIG. 4 may be based on sync signals generated by analog sync separation. It has to be ensured that resynchronisation of the control logic occurs only when the system is out of tolerance with the incoming line pulses by more than a specified range of timing, as frequent resynchronising would disturb the decoded picture unnecessarily. The time difference between a respective line in two adjacent fields is monitored. If the pulse from the sync separator arrives one field later within duration of the synchronisation window the system is working satisfactorily and does not need to be re-synchronized. The time difference between two adjacent lines is not evaluated because of the non-integral number of samples per line. The size of the window can be reduced where Videocrypt data rate is high. A similar reduction of the time for which the window is open is also required, if two or more integrated circuits are used for scrambling in the encoder, to achieve a high time precision. In the decoder the window size is advantageously chosen according to the reception quality to have a minimum degree of interference caused by data reception quality (time precision requires a short window) and re-synchronization, i.e. image quality (requires long window). The synchronization window described can be switched off so that synchronization occurs every line. This can be used in an encoder where two Videocrypt chips with 8 bit video resolution are working in parallel to achieve a broader data bus, e.g. 10 bits for studio quality. In this case the horizontal reference for the second chip is generated by the master chip, whereby both chips work completely synchronously. FIGS. 9a) to 9c) to shows how the different permutation steps work. FIG. 9a) shows how blocks are written into the encoder memory in clear. The first block is transmitted in clear but the second block undergoes a first permutation under control of the PRBS and permutation generator and is transmitted in scrambled form. However, due to the write address circuitry described with reference to FIG. 7, the block is written in clear in the decoder memory. Similarly subsequent blocks undergo different permutations P2, P3 etc. but are written in clear into the decoder. FIG. 9b shows that the reading from the decoder and the outgoing signal are identical but that block 0 (ALBERT) is output at time n, the time of input block 2 (MICHEL) illustrating the two block delay in the 47 line examples. The embodiment as described transmits pictures fully scrambled on every field. In some instances it is desirable to use partial scrambling only. For example the program provider may wish to interest non-subscribers by showing them sufficient low quality pictures for them to subscribe. The embodiment may be operated in one of two further modes to achieve this aim without disrupting the regular decoded picture when changing the scrambling mode. The first option is a `clear delayed` mode in which the lines of each block are not scrambled but the picture is transmitted one block in advance. This has the effect that the bottom 47 lines of the picture appear at the top of the screen and the colour of the picture is false. Although very annoying to a regular subscriber, the viewer can discern sufficient detail to generate an interest in the programme being transmitted. The second mode is `flash mode` in which alternate fields are scrambled and the intervening fields transmitted in clear delayed mode. The effect on the transmitted signal is to have the clear delayed picture with a superimposed scrambled picture. In view of the nature of scrambling process, it is not possible to change between fully clear and fully scrambled modes without losing one block of information. Transmitting in one of these two semi-scrambled modes enables the pictures to be shown in part to non-subscribers without disturbing the decoded picture. Referring now to FIGS. 14a)-c) and 15 the permutation generator 190 and pseudo-random binary sequence generator PRBS 150 are shown in more detail. The pseudo-random generator PRBS 150 has e.g. n=20 binary outputs BITO . . . BIT19. The number of possible states of the pseudo-random generator PRBS is thus 2.sup.20 =1048576. A control word CW from the CPU interface 130 is applied to the pseudo-random generator PRBS via an input PZG-E, and a predetermined state is assumed on each occasion. This state which defines each output of the PRBS is referred to as a keyword KW. Every 40 ms a new control word different from the preceding and following control words is transmitted with the television signals and every 40 ms a part of this control word is applied to the pseudo-random generator. The permutation generator 190 of FIG. 14a) has a clear input, which is set to zero in an initialisation phase of the permutation generator and serves to define the circuit state of the circuit arrangement. The circuit arrangement 190 comprises a six-bit adder 192 with inputs A0 . . . A5, whose values are added to the values on the inputs B0 . . . B5 five of which, B1-B5 are provided by the five output bits 0, 7, 17, 12, 3 of the pseudo-random generator 150. The sixth input, B0, of the adder 5 is permanently at 5 volts and thus at the logical value `1`. The adder 192 has six outputs S0 . . . S5, which are connected to the data input of a clocked buffer register 194. The register 194 consists e.g. of two individual buffer register components which can buffer six bits. The Q outputs of the register 194 are connected to one input of six AND gates 196A . . . 196F respectively, whose other inputs are each connected to the clear input. This clear input is at logical `1` in the normal operating state. The outputs of the AND gates are respectively connected to the inputs A0 . . . A5 of the adder 192. Thus the values at the outputs of the adder 192 are fed back to the inputs. The intermediately buffered value in the register 194 is strobed in by a clock signal CLK on a clock input CK. The input CK of the register 194 is connected to a two input OR gate OR 198 to whose one input the clock signal CLK is applied and whose other input is connected to the output of an AND gate AND 202 which has three inputs. One of these inputs is connected to the CLEAR input of the circuit arrangement 190 the second to the ENABLE input EN and the third to the output AK-A of the address comparator 204. The bits 2, 6, 15, 8, 4 and 13 at the output of the pseudo-random generator PRBS 150 and the Q outputs of the register 194 are applied to a first logic circuit 206 in which these signals can be combined in various ways. The first logic circuit 206 has six outputs, two of which are applied directly to a second logic circuit 208 and the remaining four via a four bit adder 210. Output bits 10, 19, 5 and 14 of the pseudo-random generator 150 are also applied to the four bit adder 210. The remaining output bits 1, 16, 11, 18 and 9 of the pseudo-random generator 150 are applied to the second logic circuit 208. The first and second logic circuits 206 and 208 include E-BOX circuits, M-BOX circuits and/or adders. An M-BOX circuit is shown in FIG. 14b) and is essentially a reversing switch having the following truth table:
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Inputs Outputs
ME1 ME2 MBIT MA1 MA2
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0 0 0 0 0
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 1 0
1 0 1 0 1
1 1 0 1 1
1 1 1 1 1
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A detailed circuit diagram of an E-BOX circuit is shown in FIG. 14c). The E-BOX comprises an AND gate with two inputs and an Exclusive-OR gate, likewise with two inputs. The truth table for the E-BOX is as follows:
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Inputs Outputs
EE1 EE2 EBIT EA1 EA2
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0 0 0 0 0
0 0 1 0 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 0
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The six PERMUTATION ADDRESS outputs of the second logic circuit form the six outputs of the permutation generator. At these outputs of the circuit arrangment 2 there can thus be generated 2.sup.6 =64 different permutation addresses PA0 . . . PA63. A television field consists of e.g. a=6 blocks, each with 47 lines Z0 . . . Z46, i.e. 282 video lines as described previously. The sequence of the lines within each such block is permutated by the permutation generator. The address comparator 204, whose six inputs are connected to the PERMUTATION ADDRESS outputs of the circuit arrangement 190 now checks the allowability of a permutation address. In the present example the addresses PA47 . . . PA63 represents impermissible addresses, since a block only has 47 lines. If a generated permutation address is impermissible, the address comparator generates a control signal, which is applied to the AND gate AND 202 and causes the generation of a new address. Impermissible permutation addresses are thus automatically filtered out and not used for the switching of the sequence of television lines. A very large number of different permutations can be generated with the described permutation generator according to FIG. 14. It can be shown that the permutation generator can generate 720896 different permutations according to the issuance of 1048576 control words from the PRBS 150. This means that 720896/log2=19.46 bits of the 20 bits of the pseudo-random generator PRBS are used effectively. The efficiency of the permutation generator thus amounts to 2.sup.19.46 /2.sup.20 *100%=68.8%. FIG. 15 shows a further, simplified embodiment of a permutation generator with a pseudo-random generator PRBS with n=16 outputs, a six bit adder 192 as in FIG. 14a) with its outputs fed back to its inputs, an XOR component 6 with six XOR gates and a further six bit adder 18 with six PERMUTATION ADDRESS outputs. Such a permutation generator, which has less than sixty implemented gate elements, is cost-effective, of small structure and nevertheless provides a very large number of different permutations. The pseudo-random generator PRBS 150 in FIGS. 14a) and FIG. 15 is constructed as a feedback shift register or as a circuit which generates pseudo-random numbers in accordance with the Johnson theory. The generation of pseudo-random numbers with such a generator is also used as a solution to the so-called "unranking" problem in the generation of a plurality of permutations. Various modifications to the embodiments described are possible and will occur to those skilled in the art. For example the block size may vary. The system has been described in terms of the PAL standard and is suitable for all the major PAL standards, i.e. system I,B,G,D and H. For system M PAL, used in Brazil, the number of active picture lines per field is only 243 and the number of shuffled lines per field may be 240. This may be arranged as six blocks of 40 lines, 4 blocks of 60 lines or 5 blocks of 48 lines. The number of pixels per line is only 909 and the subcarrier frequency Fsc=3.57561149 MHz. For system N PAL, used in some South American countries, the system is very similar to the system I PAL embodiment described, except that the lower sub-carrier frequency, 3.58205625 MHz requires a lower sample rate of 917.0064 samples per line. For the NTSC standard such as is used in the United States of America and Japan, the number of lines per field and the block arrangement is the same as for system M PAL outlined above. In both cases the smallest block size is most desirable to minimise noise caused by field distortion and hum. The subcarrier frequency is higher, 3.579545 MHz and thus the sampling frequency and number of samples per line higher, 14.31818 MHz and 910 respectively. In both the system M and NTSC solutions outlined, 3 data lines are included in the active picture lines, the three unshuffled lines. These lines carry Videocrypt data. One line of the vertical blanking interval is also required for data. Alternatively, a data compression algorithm could be used to compress the data onto three lines. The SECAM standard, used for example in France, is a 625 line system and uses the same block structure as the PAL example described. However, the phase locked loop requires modification. This may be achieved in two manners. Firstly, the PLL may be line locked, and secondly, one of the two colour difference sub-carriers only may be used and the system arranged as for the PAL example. In this case, the sub-carrier used could be the (R-Y) carrier, the higher frequency of the two, which has a frequency of 4.406250 MHz giving 1128 pixels per line. Alternatively, the 4.250000 MHz sub-carrier could be used giving a sampling frequency of 17 MHz. The system may be adapted for use with other standards such as the MAC family and extended to high definitions standards. It may be convenient to increase the number of blocks to 12.times.47 lines for future HDTV broadcasts or to increase the block size to 94 lines. Such modifications all fall within the scope of the invention which is defined in the following claims.
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