Method of and apparatus for modifying a video signal to inhibit recording thereof4488176Abstract Video signal lines are added to or omitted from the ends of individual fields of a video signal to produce a modified video signal whose field length varies at a slow rate. The modified video signal can be broadcast and received by conventional television equipment, normal television reception and viewing being not noticeably affected by the variable field length. However, recording of the modified video signal is inhibited because the field length is not constant. The modified video signal is produced by directly modifying the scanning of televising equipment, or by storing the lines of the video signal in a store and reading them in a controlled manner therefrom. A decoder, for producing a constant field length video signal from the modified video signal, is also disclosed. Claims What is claimed is: Description This invention relates to modifying a video signal to inhibit recording thereof on a video signal recorder, such as a video tape recorder (VTR), whilst still permitting reproduction of the video signal on a conventional broadcast television receiver.
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f = 35.79545 MHz
fh =
##STR1##
fs = 14.31818 MHz ff = 59.94 Hz
fl = 1.1014 MHz O/E = 29.97 Hz
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FIG. 4 illustrates the memory unit 203 in greater detail. This unit comprises 104 TTL 64 kbit RAMs (random access memories), together with associated ECL to TTL and TTL to ECL coverters, shown as a single block 400. The RAMs are cyclically controlled and addressed, by address and control signals supplied by the control circuit 204, for write-in and read-out of the digital video signal. In view of the relatively slow speed of each memory access cycle, the digital video signal is written into and read from the RAMs 13 8-bit words at a time, 1 bit of each word being written into or read from a respective one of the 104 RAMs. Accordingly, the 8-bit video signal words from the A-D converter and latch 202 are shifted into a shift register 401 under the control of the signal fs, and the words are transferred 13 at a time to a latch 402 under the control of the signal fl, to be written into the RAMs. Conversely, the 8-bit words are read out from the RAMs and stored in an output latch 403 13 at a time under the control of the control circuit 204, and are loaded in parallel from the latch 403 into a shift register 404 under the control of the signal fs to constitute the digital modified video output of the memory unit 203. The number of 13 words written into and read from the RAMs is selected in view of the speed of the RAMs and the number of 910 samples per horizontal line of the video signal, to provide a convenient number of 70 memory access cycles each horizontal line. The control circuit 204 is shown in FIG. 5. The control circuit 204 includes a modulo-65, counter 501, a PROM 502, and a latch 503 for producing control signals and selecting address signals, by means of an address selector 504, for each memory access cycle. The counter 502 is clocked by the signal f to increment its count, and for each count the PROM 502 is addressed to produce a set of control signals which are latched in the latch 503 under the control of the signal f. The control signals in the latch 503 control the cyclical operation of the RAMs (block 400) and latch 403 of the memory unit and the selection of a write address from a bus 505 or a read address from a bus 506 for supply to the RAMs. The write address on the bus 505 is produced by a 16-bit synchronous counter 507 which is clocked by the signal fl, so that the incoming video signal words are written cyclically into successive memory locations. The read address on the bus 506 is produced by adding to the current write address, in a modulo 2.sup.16 adder 508, an offset which is selected by a selector 509 from a latch 510 or a latch 511, and latching the sum in a latch 512 under the control of the signal fl. The selector 509 is controlled by a signal `SELECT` produced at the Q output of a D-type flip-flop 513, which signal is also supplied to a microprocessor 514. The microprocessor 514 supplies the offsets to the latches 510 and 511, and supplies a read address to a latch 515, via a common bus 516 under the control of respective latch loading signals on lines 517. The microprocessor also supplies a signal N/V to the data input D of the flip-flop 513. A comparator 518 compares the read address on the bus 506 with the read address stored in the latch 515 and, when the compared addresses are the same, produces an output signal which is gated with the signal fl in an AND gate 519 to produce a signal EQ which is supplied to the clock input CK of the flip-flop 513 and as an interrupt signal to the microprocessor 514. The microprocessor 514 is also supplied with a vertical interval start address from a latch 520; this is the write address on the bus 505 which exists at the start of a vertical interval of the video signal and which is latched in the latch 520 under the control of the signal ff. The control circuit 204 also includes a random noise source 521 and a flip-flop 522. A random noise signal, such as the noise voltage of a diode or resistor constituting the source 521, is clocked by the signal fh to the Q output of the flip-flop 522, which output is coupled to the microprocessor 514. The control circuit 204 operates as follows. As already explained, the incoming video signal words are written cyclically into the memory, and the start address of each vertical interval is stored in the latch 520. Reading of the video signal words from the memory takes place generally sequentially after a delay, or offset, which is determined by the signal SELECT to supply the offset from one of the latches 510 and 511 to the adder 508, where the selected offset is added to the write address to produce the read address. Each offset is an integral multiple of 70, so that video signal lines are read from the memory a whole number of line periods after being written into the memory. From each vertical interval start address which it obtains from the latch 520, as described more fully below the microprocessor 514 determines a read address at which the offset may be changed and stores this read address in the latch 515, and determines an appropriate offset and stores this in that one of the latches 510 and 511 which is not currently selected by the selector 509. With continued reading from the memory, the comparator 518 eventually detects equality of the current read address produced by the latch 512 and the read address stored in the latch 515, in response to which the signal EQ becomes 1 and then again becomes 0 with the next falling edge of the signal fl supplied to the gate 519. This 1-to-0 transition of the signal EQ triggers the flip-flop 513 via its clock input CK, to transfer the logic level of the signal N/V at its D input to its Q output, whereby the logic level of the signal SELECT is changed and the offset stored in the previously non-selected latch 510 or 511 is selected by the selector 509. The 1-to-0 transition of the signal EQ also constitutes an interrupt to the microprocessor 514. In response to the interrupt, the microprocessor 514 reads the new state of the signal SELECT, supplies to the latch 515 a new read address which it has determined and sets the signal N/V to be opposite to the new state of the signal SELECT. The new address which is latched in the latch 515 is different from the current read address, so that the comparator 518 no longer detects equality and the signal EQ remains 0. The microprocessor 514 determines the offsets for the latches 510 and 511 and the read addresses for the latch 515 in order to achieve the desired variation of the field length of the video signal. The direction of each change of the field length, i.e. whether the field is shortened or lengthened, is determined by the output of the flip-flop 522. The field length variation is effected by not reading or by re-reading the last, for example, 2 or 4 lines of a particular field, whereby the field in the modified video signal is respectively shortened or lengthened by 2 or 4 lines. It has been found that progressive changes in the field length of the modified video signal achieved in this manner, within the limits imposed by the size of the memory and whilst maintaining a long-term average of 525 lines per frame, do not adversely affect reproduction by a conventional television receiver of a television picture from the modified video signal. Although the variable field length results in lines being omitted from or repeated at the bottom of the reproduced picture, this is insignificant and not normally noticeable because normal television receivers are arranged to overscan by several lines. In order to avoid objectionable picture jitter due to the changing field length, the microprocessor 514 is arranged to change the field length relatively slowly. It has been found that changing the length of one frame (two fields) by two lines, with at least two frames between such changes, results in a subjectively negligible picture jitter. In other words, the average rate of change of the field length is typically not greater than one line per three fields. The operation of the control circuit 204 is explained further below by way of example and with reference to the flow chart in FIG. 6. It is assumed for example that the signal SELECT=1 for reading from the memory a particular field using an offset contained in the latch 510. It is also assumed that this field is to have the conventional number of 2621/2 lines, and that accordingly the microprocessor 514 has previously stored the vertical interval start address of the next field, obtained from the latch 520, in the latch 515, and has stored the same offset in the latch 511 as is contained in the latch 510. It is further assumed that the microprocessor has previously determined from the latch 520 the vertical interval start address of the next-but-one field and has read the output of the flip-flop 522 and the signal O/E. The latter signal is supplied to the microprocessor 514 to ensure that the omission and duplication of lines in the modified video signal does not disrupt the normal phase sequence of the color subcarrier reference burst contained in the video lines. If the output of the flip-flop 522 indicates that the next field is to be shortened, for example by two lines, the microprocessor determines as the next address for the latch 515 the vertical interval start address of the next-but-one vertical interval reduced by an amount equivalent to two video signal lines, and determines as the next offset for the latch 510 an offset equal to the offset stored in the latch 511 increased by an amount equivalent to two video signal lines. If, on the contrary, the output of the flip-flop 522 indicates that the next field is to be lengthened, for example by two lines, the microprocessor determines the vertical interval start address of the next-but-one field as the next address for the latch 515, and determines as the next offset for the latch 510 an offset equal to the offset stored in the latch 511 reduced by an amount equivalent to two video signal lines. When the current read address reaches the vertical interval start address in the latch 515, the comparator 518 establishes an identity, the flip-flop 513 is clocked to change the signal SELECT to 0 in accordance with the signal N/V=0 supplied at this time by the microprocessor 514, and an interrupt (block 600, FIG. 6) to the microprocessor is generated. With the new signal SELECT=0 the selector 509 selects the offset from the latch 511 for continued reading from the memory, but as this offset is the same as that in the latch 510 reading continues sequentially. In response to the interrupt, the microprocessor reads (block 601) the signal SELECT and determines (block 602) its new state. In this case the signal SELECT=0, in response to which the microprocessor 514 sets (block 603) the signal N/V to 1 (opposite to the signal SELECT) and then outputs (block 604) this new value of the signal N/V, the determined offset to the latch 510, and the determined address for the latch 515 to this latch. Subsequently the microprocessor reads (block 605) another vertical interval start address from the latch 520, and also reads the signal O/E and the output of the flip-flop 522. From this information the microprocessor determines (block 606) the next offset for the latch 511 and the next address for the latch 515, as already described. For example, if the next field is to have the usual length of 2621/2 lines, the microprocessor uses the relevant vertical interval start address for the latch 515 and the same offset as is in the latch 510 for the latch 511. The microprocessor 514 then waits (block 607) for the next interrupt, in response to which the above sequences are repeated to the block 602. As now the signal SELECT=1, a block 608 is reached in which the signal N/V is set to 0, and then in a block 609 this signal N/V and the determined offset for the latch 511 and address for the latch 515 are output to these latches, thereby reaching the block 605. The above sequences are repeated as described above. From the description above it should be appreciated that, for a field which is to be shortened for example by two lines, the comparator 518 establishes an identity, and the interrupt is generated, two lines before the start of the next vertical interval, and as a result of the switch-over of the selector 509 the offset is changed suddenly by two lines so that reading continues with this next vertical interval. Thus the last two lines of the field are not read from the memory. Conversely, for a field which is to be lengthened for example by two lines, the comparator establishes an identity, and the interrupt is generated, at the start of the next vertical interval, and as a result of the switch-over of the selector 509 the offset is changed suddenly by two lines so that the last two lines of the field are read again from the memory before reading continues with the vertical interval. Thus the field length of the modified video signal is varied by omitting lines from or adding duplicated lines to the end of individual fields. As has already been observed, this variation of the field length, if effected slowly as described, is not noticeable in the normal reproduction and viewing of the video signal on a conventional television receiver, but prevents recording of the video signal on video tape recorders which rely for their operation on the video signal to be recorded having a constant field and frame length. FIG. 7 illustrates a modified and simplified form of the arrangement described above, which can be used where a television program source 70, which includes a control and synchronizing pulse generator unit 71, is located at the same location as the encoding equipment, which in this case consists of a control unit 72. In this case the television picture image is continuously available from the program source 70, which for example comprises a studio television camera or a cine film so that the memory unit 203 described above, and the associated conversion and latching circuitry, can be dispensed with. Accordingly, in the arrangement of FIG. 7 the control unit 72 directly controls the unit 71 to provide the modified video signal on a line 73 with the described variable field length. This control is effected in real time by directly controlling a video line counter of the unit 71 to modify the field length by omitting scanning or duplicating scanning of video lines. Accordingly, the video signal on the line 94 is directly modified. As explained above, the modified video signal can not be recorded on a video tape recorder because it has a variable field and frame length. Unlike the prior art arrangements, in which reconstruction of the normal vertical interval can be easily effected at low cost, thereby enabling recording of the video signal and defeating the encoding process, the modified video signal of the present invention can not be readily and economically converted to a form suitable for recording. In fact, a decoder for converting the modified video signal to a suitable form for recording must be virtually as complicated as the encoder described above with reference to FIGS. 1 to 6. Whilst the expense of a single encoder as described above can be justified for a television transmission system, the comparable expense of a decoder for individual use with a video tape recorder would generally be considered exorbitant. FIG. 8, however, illustrates in a block diagram a possible form of such a decoder, which comprises a low pass filter 800, timing extractor 801, A-D converter and latch 802, memory unit 803, control circuit 804, latch and D-A converter 807, and a filter and equalizer 808, which are arranged in a similar manner to the arrangement of the encoder as shown in FIG. 2. In addition, the decoder comprises a selector 806 which is controlled by the control circuit 804 to supply a video blanking level to the unit 807 to replace lines which are omitted from the modified video signal. As illustrated, the control circuit 804 is supplied with synchronizing signals from the timing extractor 801, from which it determines the locations of omitted and duplicated lines in the modified video signal. From this description and the foregoing description of the manner in which the encoder operates, it will be apparent to those skilled in the art how the decoder may be implemented in detail to produce a standard video signal from the modified video signal. Although particular embodiments of the invention have been described in detail, numerous changes, adaptations, and variations may be made without departing from the scope of the invention, which is defined in the claims.
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