Method and apparatus for generating encryption stream ciphers6252958Abstract A method and apparatus for generating encryption stream ciphers. The recurrence relation is designed to operate over finite fields larger than GF(2) and is maximal length. An output equation generates the output based on a plurality of elements in the shift register used to implement the recurrence relation. The recurrence relation and the output equation are selected to have distinct pair distances such that, as the shift register shifts, no particular pair of elements of the shift register are used twice in either the recurrence relation or the output equation. Claims I claim: Description BACKGROUND OF THE INVENTION
TABLE 1
Exponential Table
i xx0 xx1 xx2 xx3 xx4 xx5 xx6 xx7 xx8 xx9
00x 1 2 4 8 16 32 64 128 77 154
01x 121 242 169 31 62 124 248 189 55 110
02x 220 245 167 3 6 12 24 48 96 192
03x 205 215 227 139 91 182 33 66 132 69
04x 138 89 178 41 82 164 5 10 20 40
05x 80 160 13 26 52 104 208 237 151 99
06x 198 193 207 211 235 155 123 246 161 15
07x 30 60 120 240 173 23 46 92 184 61
08x 122 244 165 7 14 28 56 112 224 141
09x 87 174 17 34 68 136 93 186 57 114
10x 228 133 71 142 81 162 9 18 36 72
11x 144 109 218 249 191 51 102 204 213 231
12x 131 75 150 97 194 201 223 243 171 27
13x 54 108 216 253 183 35 70 140 85 170
14x 25 50 100 200 221 247 163 11 22 44
15x 88 176 45 90 180 37 74 148 101 202
16x 217 255 179 43 86 172 21 42 84 168
17x 29 58 116 232 157 119 238 145 111 222
18x 241 175 19 38 76 152 125 250 185 63
19x 126 252 181 39 78 156 117 234 153 127
20x 254 177 47 94 188 53 106 212 229 135
21x 67 134 65 130 73 146 105 210 233 159
22x 115 230 129 79 158 113 226 137 95 190
23x 49 98 196 197 199 195 203 219 251 187
24x 59 118 236 149 103 206 209 239 147 107
25x 214 225 143 83 166
III. Memory Implementation When implemented in hardware, shifting bits is a simple and efficient operation. Using a processor and for a shift register larger than the registers of the processor, shifting bits is an iterative procedure which is very inefficient. When the units to be shifted are bytes or words, shifting becomes simpler because there is no carry between bytes. However, the shifting process is still iterative and inefficient. In the exemplary embodiment, the linear feedback shift register is implemented with a circular buffer or a sliding window. The diagrams showing the contents of circular buffer 24a at time n and at time n+1 are shown in FIGS. 3A and 3B, respectively. For circular buffer 24a, each element of the shift register is stored in a corresponding location in memory. A single index, or pointer 30, maintains the memory location of the most recent element stored in memory, which is S.sub.k-1 in FIG. 3A. At time n+1, the new element S.sub.k is computed and stored over the oldest element S.sub.0 in memory, as shown in FIG. 3B. Thus, instead of shifting all elements in memory, pointer 30 is moved to the memory location of the new element S.sub.k. When pointer 30 reaches the end of circular buffer 24a, it is reset to the beginning (as shown in FIGS. 3A and 3B). Thus, circular buffer 24a acts as if it is a circle and not a straight line. Circular buffer 24a can be shifted from left-to-right, or right-to-left as shown in FIGS. 3A and 3B. Correspondingly, pointer 30 can move left-to-right, or right-to-left as shown in FIGS. 3A and 3B. The choice in the direction of the shift is a matter of implementation style and does not affect the output result. To generate an output element in accordance with a recurrence relation, more than one element is typically required from memory. The memory location associated with each required element can be indicated by a separate pointer which is updated when the register is shifted. Alternatively, the memory location associated with each required element can be computed from pointer 30 as necessary. Since there is a one-to-one mapping of each element to a memory location, a particular element can be obtained by determining the offset of that element from the newest element (in accordance with the recurrence relation), adding that offset to pointer 30, and addressing the memory location indicated by the updated pointer. Because of the circular nature of the memory, the calculation of the updated pointer is determined by an addition modulo k of the offset to pointer 30. Addition modulo k is simple when k is a power of two but is otherwise an inefficient operation on a processor. In the preferred embodiment, the shift register is implemented with sliding window 24b as shown in FIG. 3C. Sliding window 24b is at least twice as long as circular buffer 24a and comprises two circular buffers 32a and 32b arranged adjacent to each other. Each of circular buffers 32a and 32b behaves like circular buffer 24a described above. Circular buffer 32b is an exact replica of circular buffer 32a. Thus, each element of the shift register is stored in two corresponding locations in memory, one each for circular buffers 32a and 32b. Pointer 34 maintains the memory location of the most recent element stored in circular buffer 32a, which is S.sub.k-1 in FIG. 3C. In the exemplary embodiment, pointer 34 starts at the middle of sliding window 24b, moves right-to-left, and resets to the middle again when it reaches the end on the left side. From FIG. 3C, it can be observed that no matter where in circular buffer 32a pointer 34 appears, the previous k-1 elements can be addressed to the right of pointer 34. Thus, to address an element in the shift register in accordance with the recurrence relation, an offset of k-1 or less is added to pointer 34. Addition modulo k is not required since the updated pointer is always to the right of pointer 34 and computational efficiency is obtained. For this implementation, sliding window 24b can be of any length at least twice as long as circular buffer 24a, with any excess bytes being ignored. Furthermore, the update time is constant and short. IV. Exemplary Stream Cipher Based on LFSR Over GF(2.sup.8) The present invention can be best illustrated by an exemplary generator for a stream cipher based on a linear feedback shift register over GF(2.sup.8). The stream cipher described below uses the byte operations described above over the Galois field of order 8 with the representation of .sym. and {character pullout} for operations of addition and multiplication, respectively, over the Galois field. In the exemplary embodiment, table lookup is utilized for the required multiplication with constants C.sub.j. In the exemplary embodiment, a sliding window is used to allow fast updating of the shift register. A block diagram of the exemplary generator is shown in FIG. 4. In the exemplary embodiment, linear feedback shift register 52 is 17 octets (or 136 bits) long which allows shift register 52 to be in 2.sup.136 -1 (or approximately 8.7.times.10.sup.40) states. The state where the entire register is 0 is not a valid state and does not occur from any other state. The time to update register 52 with a particular number of non-zero elements in the recurrence relation is constant irrespective of the length of register 52. Thus, additional length for register 52 (for higher order recurrence relation) can be implemented at a nominal cost of extra bytes in memory. In the exemplary embodiment, linear feedback shift register 52 is updated in accordance with the following recurrence relation: S.sub.n+17 =(100{character pullout}S.sub.n+9).sym.S.sub.n+4.sym.(141{character pullout}S.sub.n), (4) where the operations are defined over GF(2.sup.8), .sym. is the exclusive-OR operation on two bytes represented by Galois adders 58, and {character pullout} is a polynomial modular multiplication represented by Galois multipliers 54 (see FIG. 4). In the exemplary embodiment, the modular multiplications on coefficients 56 are implemented using byte table lookups on pre-computed tables as described above. In the exemplary embodiment, the polynomial modular multiplication table is computed using the irreducible polynomial defined by equation (3). The recurrence relation in equation (4) was chosen to be maximal length, to have few non-zero coefficients, and so that the shift register elements used were distinct from ones used for the non-linear functions below. In the exemplary embodiment, to disguise the linearity of shift register 52 two of the techniques described above are used, namely stuttering and using a non-linear function. Additional non-linearity techniques are utilized and are described below. In the exemplary embodiment, non-linearity is introduced by performing a non-linear operation on multiple elements of shift register 52. In the exemplary embodiment, four of the elements of shift register 52 are combined using a function which is non-linear. An exemplary non-linear function is the following: V.sub.n =(S.sub.n +S.sub.n+5).times.(S.sub.n+2 +S.sub.n+12), (5) where V.sub.n is the non-linear output (or the generator output),+ is the addition truncated modulo 256 represented by arithmetic adders 60, and .times. is the multiplication modulo 257 represented by modular multiplier 62 and described below. In the exemplary embodiment, the four bytes used are S.sub.n, S.sub.n+2, S.sub.n+5 and S.sub.n+12, where S.sub.n is the oldest calculated element in the sequence according to the recurrence relation in equation (4). These elements are selected such that, as the register shifts, no two elements are used in the computation of two of the generator outputs. The pairwise distances between these elements are distinct values. For example, S.sub.n+12 is not combined with S.sub.n+5, S.sub.n+2, nor S.sub.n again as it is shifted through register 52. Simple byte addition, with the result truncated modulo 256, is made non-linear in GF(2.sup.8) by the carry between bits. In the exemplary embodiment, two pairs of elements in the register {(S.sub.n and S.sub.n+5) and (S.sub.n+2 and S.sub.n+12)} are combined using addition modulo 256 to yield two intermediate results. However, addition modulo 256 is not ideal since the least significant bits have no carry input and are still combined linearly. Another non-linear function which can be computed conveniently on a processor is multiplication. However, truncation of a normal multiplication into a single byte may not yield good result because multiplication modulo 256 does not form a group since the results are not well distributed within the field. A multiplicative group of the field of integers modulo the prime number 257 can be used. This group consists of integers in the range of 1 to 256 with the group operation being integer multiplication reduced modulo 257. Note that the value 0 does not appear in the group but the value 256 does. In the exemplary embodiment, the value of 256 can be represented by a byte value of 0. Typically, processors can perform multiplication instructions efficiently but many have no capability to perform, nor to perform efficiently, divide or modulus instructions. Thus, the modulo reduction by 257 can represent a performance bottleneck. However, reduction modulo 257 can be computed using other computational modulo 2.sup.n, which in the case of n=8 are efficient on common processors. It can be shown that for a value X in the range of 1 to 2.sup.16 -1 (where X is the result of a multiplication of two 8th order operands), reduction modulo 257 can be computed as: ##EQU1## where X.sub.257 is the reduction modulo 257 of X and X.sub.256 is the reduction modulo 256 of X. Equation (6) indicates that reduction modulo 257 of a 16-bit number can be obtained by subtracting the 8 most significant bits (X/256) from the 8 least significant bits (X.sub.256). The result of the subtraction is in the range of -255 and 255 and may be negative. If the result is negative, it can be adjusted to the correct range by adding 257. In the alternative embodiment, reduction modulo 257 can be performed with a lookup table comprising 65,536 elements, each 8 bits wide. Multiplication of the two intermediate results is one of many non-linear functions which can be utilized. Other non-linear functions, such as bent functions or permuting byte values before combining them, can also be implemented using lookup tables. The present invention is directed at the use of these various non-linear functions for producing non-linear output. In the exemplary embodiment, stuttering is also utilized to inject additional non-linearity. The non-linear output derived from the state of the linear feedback shift register as described above may be used to reconstruct the state of the shift register. This reconstruction can be made more difficult by not representing some of the states at the output of the generator, and choosing which in an unpredictable manner. In the exemplary embodiment, the non-linear output is used to determine what subsequent bytes of non-linear output appear in the output stream. When the generator is started, the first output byte is used as the stutter control byte. In the exemplary embodiment, each stutter control byte is divided into four pairs of bits, with the least significant pair being used first. When all four pairs have been used, the next non-linear output byte from the generator is used as the next stutter control byte, and so on. Each pair of stutter control bits can take on one of four values. In the exemplary embodiment, the action performed for each pair value is tabulated in Table 3.
TABLE 3
Pair
Value Action of Generator
(0, 0) Register is cycled but no output is produced
(0, 1) Register is cycled and the non-linear output XOR with
the constant (0 1 1 0 1 0 0 1).sub.2 becomes the output of the
generator. Register is cycled again.
(1, 0) Register is cycled twice and the non-linear output
becomes the output of the generator.
(1, 1) Register is cycled and the non-linear output XOR with
the constant (1 1 0 0 0 1 0 1).sub.2 becomes the output of the
generator.
As shown in Table 3, in the exemplary embodiment, when the pair value is (0, 0), the register is cycled once but no output is produced. Cycling of the register denotes the calculation of the next sequence output in accordance with equation (4) and the shifting this new element into the register. The next stutter control pair is then used to determine the action to be taken next. In the exemplary embodiment, when the pair value is (0, 1) the register is cycled and the non-linear output generated in accordance with equation (5). The non-linear output is XORed with the constant (0 1 1 0 1 0 0 1).sub.2 and the result is provided as the generator output. The register is then cycled again. In FIG. 4, the XORed function is performed by XOR gate 66 and the constant is selected by multiplexer (MUX) 64 using the stutter control pair from buffer 70. The output from XOR gate 66 is provided to switch 68 which provides the generator output and the output byte for stutter control in accordance with the value of the stutter control pair. The output byte for stutter control is provided to buffer 70. In the exemplary embodiment, when the pair value is (1, 0) the register is cycled twice and the non-linear output generated in accordance with equation (5) is provided as the generator output. In the exemplary embodiment, when the pair value is (1, 1) the register is cycled and the non-linear output generated in accordance with equation (5). The non-linear output is then XORed with the constant (1 1 0 0 0 1 0 1)2 and the result is provided as the generator output. In the exemplary embodiment, the constants which are used in the above steps are selected such that when a generator output is produced, half of the bits in the output are inverted with respect to the outputs produced by the other stutter control pairs. For stutter control pair (1, 0), the non-linear output can be viewed as being XORed with the constant (0 0 0 0 0 0 0 0).sub.2. Thus, the Hamming distance between any of the three constants is four. The bit inversion further masks the linearity of the generator and frustrates any attempt to reconstruct the state based on the generator output. The present invention supports a multi-tier keying structure. A stream cipher which supports a multi-tier keying structure is especially useful for wireless communication system wherein data are transmitted in frames which may be received in error or out-of-sequence. An exemplary two-tier keying structure is described below. In the exemplary embodiment, one secret key is used to initialize the generator. The secret key is used to cause the generator to take an unpredictable leap in the sequence. In the exemplary embodiment, the secret key has a length of four to k-1 bytes (or 32 to 128 bits for the exemplary recurrence relation of order 17). Secret keys of less than 4 bytes are not preferred because the initial randomization may not be adequate. Secret keys of greater than k-1 bytes can also be utilized but are redundant, and care should be taken so that a value for the key does not cause the register state to be set to all 0, a state which cannot happen with the current limitation. A flow diagram of an exemplary secret key initialization process is shown in FIG. 5. The process starts at block 110. In the exemplary embodiment, at block 112, the state of the shift register is first initialized with the Fibonacci numbers modulo 256. Thus, elements S.sub.0, S.sub.1, S.sub.2, S.sub.3, S.sub.4, S.sub.5, and so on, are initialized with 1, 1, 2, 3, 5, 8, and so on, respectively. Although Fibonacci numbers are used, any set of non-zero numbers which are not linearly related in the Galois field can be used to initialized the register. These numbers should not have exploitable linear relationship which can be used to reconstruct the state of the register. Next, the loop index n is set to zero, at block 114. The secret key initialization process then enters a loop. In the first step within the loop, at block 116, the first unused byte of the key material is added to S.sub.n. Addition of the key material causes the generator to take an unpredictable leap in the sequence. The key is then shifted by one byte, at block 118, such that byte used in block 116 is deleted. The register is then cycled, at block 120. The combination of blocks 116 and 120 effectively performs the following calculation: S.sub.n+17 =(100{character pullout}S.sub.+9).sym.S.sub.n+4.sym.(141{character pullout}(S.sub.n.sym.K)), (7) where K is the first unused byte of the key material. The loop index n is incremented, at block 122. A determination is then made whether all key material have been used, at block 124. If the answer is no, the process returns to block 116. Otherwise, the process continues to block 126. In the exemplary embodiment, the length of the key is added to S.sub.n, at block 126. Addition of the length of the key causes the generator to take an additional leap in the sequence. The process then enters a second loop. In the first step within the second loop, at block 128, the register is cycled. The loop index n is incremented, at block 130, and compared against the order k of the generator, at block 132. If n is not equal to k, the process returns to block 128. Otherwise, if n is equal to k, the process continues to block 134 where the state of the generator is saved. The process then terminates at block 136. In addition to the secret key, a secondary key can also be used in the present invention. The secondary key is not considered secret but is used in an exemplary wireless telephony system to generate a unique cipher for each frame of data. This ensures that erased or out-of-sequence frames do not disrupt the flow of information. In the exemplary embodiment, the stream cipher accepts a per-frame key, called a frame key, in the form of a 4-octet unsigned integer. The per-frame initialization is similar to the secret key initialization above but is performed for each frame of data. If the use of the stream cipher is such that it is unnecessary to utilize per-frame key information, for example for file transfer over a reliable link, the per-frame initialization process can be omitted. A flow diagram of an exemplary per-frame initialization process with the frame key is shown in FIG. 6. The process starts at block 210. In the exemplary embodiment, at block 212, the state of the generator is initialized with the state saved from the secret key initialization process as described above. Next, the loop index n is set to zero, at block 214. The per-frame initialization process then enters a loop. In the first step within the loop, at block 216, the least significant byte of the frame key is added modulo 256 to S.sub.n. The frame key is then shifted by three bits, at block 218, such that the three least significant bits used in block 216 are deleted. The register is then cycled, at block 220. In the exemplary embodiment, the loop index n is incremented at block 222 and compared against 11 at block 224. The value of 11, as used in block 224, corresponds to the 32 bits used as the frame key and the fact that the frame key is shifted three bits at a time. Different selections of the frame key and different numbers of bits shifted at a time can result in different comparison values used in block 224. If n is not equal to 11, the process returns to block 216. Otherwise, if n is equal to 11, the process continues to block 226 and the register is cycled again. The loop index n is incremented, at block 228, and compared against 2k, at block 230. If n is not equal to 2k, the process returns to block 226. Otherwise, if n is equal to 2k, the process terminates at block 232. The present invention has been described for the exemplary Galois finite field having 256 elements. Different finite fields can also be utilized such that the size of the elements matches the byte or word size of the processor used to manipulate the elements and/or the memory used to implement the shift register, or having other advantages. Thus, various finite fields having more than two elements can by utilized and are within the scope of the present invention. The example shown above utilizes a variety of non-linear processes to mask the linearity of the recurrence relation. Other generators can be designed utilizing different non-linear processes, or different combinations of the above described non-linear processes and other non-linear processes. Thus, the use of various non-linear processes to generate non-linear outputs can be contemplated and is within the scope of the present invention. The example shown above utilizes a recurrence relation having an order of 17 and defined by equation (4). Recurrence relations having other orders can also be generated and are within the scope of the present invention. V. A Second Exemplary Stream Cipher Based on LFSR Over GF(2.sup.8) A block diagram of a second exemplary generator is shown in FIG. 7. In the exemplary embodiment, linear feedback shift register 82 is 17 octets long although other lengths for register 82 (for different order recurrence relation) can be implemented and are within the scope of the present invention. A recurrence relation of order 17 is well suited for applications requiring 128-bit key material. In the exemplary embodiment, linear feedback shift register 82 is updated in accordance with the following recurrence relation: S.sub.n+.sub.17 =(141{character pullout}S.sub.n+15).sym.S.sub.n+4.sym.(175{character pullout}S.sub.n), (8) where the operations are defined over GF(2.sup.8), .sym. is the exclusive-OR operation on two bytes represented by Galois adders 88, and {character pullout} is a polynomial modular multiplication represented by Galois multipliers 84 (see FIG. 7). In the exemplary embodiment, the modular multiplications on coefficients 86 are implemented using byte table lookups on pre-computed tables as described above. The recurrence relation in equation (8) was chosen to be maximal length. In the exemplary embodiment, to disguise the linearity of shift register 82, two of the techniques described above are used, namely stuttering and using a non-linear function. Additional non-linearity techniques are utilized and are described below. In the exemplary embodiment, non-linearity is introduced by combining four of the elements of shift register 82 using a function (or output equation) which is non-linear with respect to the linear operation over GF(2.sup.8). In the exemplary embodiment, the four bytes used are S.sub.n, S.sub.n+2, S.sub.n+5 and S.sub.n+12, where S.sub.n is the oldest calculated element in the sequence according to the recurrence relation in equation (8). In the exemplary embodiment, the four bytes are combined in accordance with the following output equation: V.sub.n =S.sub.n +S.sub.n+2 +S.sub.n+5 +S.sub.n+12, (9) where V.sub.n is the non-linear output and + is the addition truncated modulo 256 (with the overflow discarded) represented by arithmetic adders 90. As stated above, simple byte addition, with the result truncated modulo 256, is made non-linear in GF(2.sup.8) by the carry between bits. In theexemplary embodiment, the four bytes are combined using addition modulo 256 to yield the output. However, addition modulo 256 is not ideal since the least significant bits have no carry input and are still combined linearly. In the exemplary embodiment, the subsequent stuttering step provides sufficient disguise of the remaining linearity in equation (9). The use of modulo addition in equation (9) simplifies the computation required to generate an output. In the exemplary embodiment, the bytes used for recurrence relation (8) comprise S.sub.n, S.sub.n+4, and S.sub.n+15 and the bytes used for output equation (9) comprise S.sub.n, S.sub.n+2, S.sub.n+5 and S.sub.n+12. In the exemplary embodiment, these bytes are selected to have distinct pair distances. For recurrence relation equation (8), the three bytes used have pair distances of 4 (the distance between S.sub.n and S.sub.n+4), 11 (the distance between S.sub.n+4 and S.sub.n+15), and 15 (the distance between S.sub.n and S.sub.n+15). Similarly, for output equation (9), the four bytes used have pair distances of 2 (the distance between S.sub.n and S.sub.n+2), 3 (the distance between S.sub.n+2 and S.sub.n+5), 5 (the distance between S.sub.n and S.sub.n+5), 7 (the distance between S.sub.n+5 and S.sub.n+12), 10 (the distance between S.sub.n+2 and S.sub.n+12), and 12 (the distance between S.sub.n and S.sub.n+12). It can be noted that the pair distances in recurrence relation (8) (e.g., 4, 11, and 15) are unique (or distinct) within that first respective group and that the pair distances in output equation (9) (e.g., 2, 3, 5, 7, 10, and 12) are also distinct within that second respective group. Furthermore, it can be noted that the pair distances in recurrence relation (8) are distinct from the pair distances in output equation (9). Distinct pair distances ensure that, as shift register 82 shifts, no particular pair of elements of shift register 82 are used twice in either recurrence relation (8) or the non-linear output equation (9). This property removes linearity in the subsequent output equation (9). In the exemplary embodiment, multiplexer (MUX) 92, XOR gate 94, switch 96, and buffer 98 in FIG. 7 operate in the manner described above for MUX 64, XOR gate 66, switch 68, and buffer 70 in FIG. 4. In the exemplary embodiment, the secret key initialization process as shown in FIG. 5 is performed once and the state of the generator is saved for later use by the subsequent per-frame initialization process. In the alternative embodiment, instead of saving the state of the generator, the secret key initialization process can be performed whenever the state of the generator is needed. The alternative embodiment work particularly well when the secret key is shorter than 17 bytes, or the length of the shift registers. A flow diagram of an alternative exemplary per-frame initialization process with the frame key is shown in FIG. 8. The alternative exemplary per-frame initialization process in FIG. 8 is identical to the per-frame initialization process in FIG. 6, with the exception of block 213. For frame key which is used somewhat like a counter (e.g., the least significant bits change most frequently), the least significant byte of the frame key can be XORed with the most significant byte such that the most significant byte can have more impact in the initialization process. This is represented by block 213 in FIG. 8 which is interposed between blocks 212 and 214 in the flow diagram of FIG. 6. The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. The various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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