Multiplexed noise coded switching system

Abstract

A switching system for performing line to line or group to group switching of communication signals modulated by multiplexed noise codes. The noise codes comprise a subclass or set of multiplexed noise codes consisting of code mate pairs which provide an impulse autocorrelation function when detected and furthermore crosscorrelate to zero at a time when the code mate pairs compress to an impulse providing thereby orthogonal operation, meaning that there is no mutual interference between any of the input/output lines when the signals are translated thereon concurrently. Plural sets of noise code generators and code selectors are coupled to predetermined ones of a plurality of sets of matched filter detectors and code selectors in accordance with a switching algorithm which sets selected code selectors to the same code mate pairs so that a specific signal applied to a predetermined input line and thereafter coupled to modulation means connected to one set of code generators is directed to a predetermined output line that is connected to a matched filter decoder pair matched to the input code.

Claims

I claim:

1. A multiplexed noise coded switching system for making selective interconnection between a plurality of signal input lines and a plurality of signal output lines, comprising in combination:

input circuit means respectively coupled to each of said input lines and wherein each of said input circuit means includes means for generating a respective multiplexed noise code formed with code mate pairs having autocorrelation functions which upon detection compress to an impulse and additionally having crosscorrelation functions equal to zero at a time when said code mate pairs compress to an impulse;

means for modulating a respective input signal with a selected code mate pair,

output circuit means respectively coupled to each of said output lines and wherein each of said output circuit means includes detector means responsive to a selected code mate pair modulating an input signal applied to said input lines for detecting and compressing said code mate pair to an impulse output signal which is applied to the respective output line,

means for commonly connecting all of said input circuit means with all of said output circuit means, and

whereby any input signal modulated by a generated code mate pair will only translate to a selected output line whose detector means are matched to said code mate pair while non-interfering with all other output lines.

2. The switching system as defined by claim 1 wherein each of said input circuit means includes means for generating mutually different multiplexed noise codes.

3. The switching system as defined by claim 2 wherein said noise code generating means comprises first and second noise code generates each generating one code of a code mate pair, and

said modulating means comprises first and second signal modulators respectively coupled to said first and second noise code generators and commonly coupled to the respective input.

4. The switching system as defined by claim 3 wherein said detector means comprises autocorrelation detector means.

5. The switching system as defined by claim 4 wherein said autocorrelation detector means comprises first and second noise code compressor means each matched to a different one of said first and second code generators, and adder means coupled to said first and second code compressor means for linearly adding the compressed output thereof to provide said impulse output signal.

6. The switching system as defined by claim 5 wherein said first and second code compressor means are comprised of matched filters.

7. The switching system as defined by claim 5 and additionally including code selector means coupled to said first and second noise code generators for producing a desired code mate pair, and additionally including code selector means coupled to said first and second noise code compressor means for matching the code of said first code generator to said first code compressor means and the code of said second code generator to said second code compressor means.

8. The switching system as defined by claim 5 wherein said connecting means comprises a first linear adder coupled to all of said first signal modulators, a second linear adder coupled to all of said second signal modulators, a first noise code bus commonly connected between said first linear adder and all of said first code compressor means, and a second noise code bus commonly connected between said second linear adder and all of said second code compressor means.

9. The switching system as defined by claim 5 and additionally including timing means coupled between said input circuit means and said output circuit means for starting all of the generated noise codes and for detecting all of said noise codes concurrently.

10. The switching system as defined by claim 9 wherein said timing means includes a clock signal generator coupled to all said first and second noise code generators and a respective signal output gate coupled to all said adder means coupled to said first and second noise code compressor means and energized in accordance with the operation of said clock signal generator.

11. The switching system as defined by claim 10 and additionally including gate generator means coupled between said clock signal generator and each signal output gate.

12. The switching system as defined by claim 1 wherein said code mate pairs are comprised of multi-bit binary digital codes.

13. A method of selectively switching a plurality of electrical signals between a plurality of signal input lines and a plurality of signal output lines while providing orthogonal operation therebetween, comprising the steps of:

generating a plurality of different multiplexed noise codes comprising code mate pairs having autocorrelation functions which upon detection compress to an impulse and additionally having crosscorrelation functions equal to zero at a time when said code mates compress to an impulse;

modulating each input signal applied to a respective input line with a different code mate pair;

translating the modulated signals to a plurality of code detectors;

selectively matching said code detectors to predetermined different code mate pairs of said different noise codes;

detecting and compressing each different code mate pair to an impulse signal in a code detector matched to a particular code mate pair to provide a respective output signal for each input signal; and

applying each output signal to a respective output line, whereby any input signal modulated by a particular generated code mate pair will only translate to a selected output line whose code detector is matched to that code mate pair while non-interfering with all modulated signals.

14. The method as defined by claim 13 wherein said step of translating comprises translating all modulated signals of one code of said different code mate pairs on a common signal channel and translating all modulated signals of the code of said different code mate pairs on another common signal channel.

15. The method as defined by claim 14 wherein said step of generating said plurality of different code mate pairs comprises generating each code of a code mate pair separately under the control of a code selector.

16. The method as defined by claim 14 wherein said step of detecting each different code mate pair comprises detecting each code of a code mate pair separately and said step of compressing comprises adding the respective detected code mate pairs together.

17. The method as defined by claim 16 where said step of detecting each code of a code mate pair separately is under the control of code selector for selectively matching a specific modulating code mate pair coupled to a predetermined input line to a specific code detector coupled to a predetermined output line.

18. The method as defined by claim 16 wherein said step of separately detecting each code of a code mate pair comprises matched filter detecting and said step of adding the detected code mate pairs together comprises linearly adding the respective detected code mate pairs together.

19. The method as defined by claim 14 wherein said step of generating said plurality of different multiplexed noise codes comprises generating all said different code mate pairs concurrently.

20. The method as defined by claim 19 and wherein said step of detecting and compressing comprises detecting and compressing all said different code mate pairs concurrently.

21. The method as defined by claim 13 wherein said code mate pairs are comprised of multi-bit binary digital codes.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application is related to another application filed in the name of the present inventor, and comprises U.S. Ser. No. 407,409 (CERCOM D-2058), entitled, "Orthogonal Code Division Multiple Access Communication System", filed on Aug. 12, 1982. This application is referenced inasmuch as the same type of noise codes are employed in both inventions.

FIELD OF THE INVENTION

This invention relates generally to signal switching systems and more particularly to a switching system which performs line to line or group to group switching for signals modulated by multiplexed noise codes.

BACKGROUND OF THE INVENTION

Communications systems utilizing noise coded signals are well known and are particularly desirable because they exhibit immunity against self interference and jamming. In particular, one class of noise codes are known wherein pairs of coded signals termed "code mates" have autocorrelation functions so that when they are detected and the resultant detected outputs are linearly added, there is provided an impulse autocorrelation function meaning that there is an impulse output at a given time and a zero output at all other times. Such codes and systems utilizing such codes are typically shown and described in U.S. Pat. No. 3,461,451, entitled, "Code Generator To Produce Permutations Of Code Mates", which issued to F. S. Gutleber, the present inventor, on Aug. 12, 1969; U.S. Pat. No. 3,519,746, entitled, "Means And Method To Obtain An Impulse Autocorrelation Function", which issued to F. S. Gutleber on July 7, 1970; and U.S. Pat. No. 3,634,765, entitled, "System To Provide An Impulse Autocorrelation Function . . . ", which issued to F. S. Gutleber on Jan. 11, 1972. The teachings of these patents are meant to be incorporated herein by reference, since they provide a basis for the subject invention which will be described subsequently.

Prior art approaches to switching systems for performing line to line or group to group switching between multiple users have resorted to the use of frequency filters, time gates or space division switching. Such apparatus as a result has been found to be relatively complex, bulky and vulnerable to noise interference, cross talk, unauthorized interception and jamming.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide an improvement in secure communications switching systems.

Another object of the present invention is to provide an improved switching system capable of automatically accommodating digital and/or analog signals.

Still another object of the invention is to provide an improved switching system for secure communications systems that automatically accommodate both digital and analog signals and which operates with no interference between multiple users while completely eliminating the unauthorized interception of messages therebetween.

Accordingly, these and other objects are achieved by means of a switching system utilizing multiplexed noise codes which compress to a lobeless impulse upon detection and which additionally have a characteristic whereby different codes of a selected subset crosscorrelate to zero at a time when they exhibit an autocorrelation impulse function. The system includes a plurality of input lines coupled to respective noise code mate generators and a plurality of output lines respectively coupled to noise code pulse compressors. The code generators and the pulse compressors operate in accordance with a switching algorithm that sets an input line code generator and an output line pulse compressor to the same code mate pair which automatically directs or translates the specific signal applied to an input line to a selected output line that is matched to the input code.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram illustrative of the preferred embodiment of the invention; and

FIG. 2 is a functional block diagram further illustrative of the embodiment shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings and more particularly to FIG. 1, shown thereat in block diagrammatic form is a multiplexed noise coded switching system in accordance with the subject invention which is comprised of a plurality of input circuits 10.sub.1, 10.sub.2 . . . 10.sub.n and a corresponding number of output circuits 12.sub.1, 12.sub.2 . . . 12.sub.n. The input units commonly couple to a pair of linear adders 14 and 16 used for signal multiplxing and which respectively connect to a pair of multiplexed noise code busses 18 and 20 commonly coupled to the output circuits 12.sub.1, 12.sub.2 . . . 12.sub.n. Interconnection between the adders 14 and 16 and the noise code busses 18 and 20 is further made by a pair of signal lines 22 and 24. Each of the n input circuits 10.sub.1 . . . 10.sub.n include a respective input line 26.sub.1, 26.sub.2 . . . 26.sub.n which is adapted to receive an input signal S.sub.1, S.sub.2 . . . S.sub.n. In a like manner, each of the output circuits 12.sub.1, 12.sub.2 . . . 12.sub.n include a respective output line 28.sub.1, 28.sub.2 . . . 28.sub.n which are adapted to separately output the signals S'.sub.1, S'.sub.2 . . . S'.sub.n.

Selective signal coupling between one or more input circuits 10.sub.1 . . . 10.sub.n and one or more output circuits 12.sub.1 . . . 12.sub.n is achieved by utilizing multiplexed noise codes of a particular type, to be described, to modulate a particular input signal (S) of the signals S.sub.1 . . . S.sub.n which is then coupled to at least one output circuit having a detector or decoder which is matched to the noise code of the particular input circuit. The noise codes are of the well known general type of noise codes shown and described in the aforementioned U.S. Pat. Nos. 3,461,451; 3,519,746; and 3,634,765 and which consist of code mate pairs that possess an impulse autocorrelation function upon detection. The present invention, however, utilizes a specific subclass or set of these noise codes which have code mate pairs which exhibit a crosscorrelation function equal to zero at a time when the code mate pairs compress to an impulse. While spurious lobes may exist whose rms value has an amplitude that is down by at least the square root of the code sequence length, i.e. the time--bandwidth product, the absence of any correlation value in the same compressed time interval for all codes of this latter type enables the system as shown in FIG. 1 to operate orthogonally, i.e. without any interference between any of the input/output lines, while using different noise codes for the input/output circuits 10.sub.1 . . . 10.sub.n and 12.sub.1 . . . 12.sub.n.

Accordingly, each of the input circuits 10.sub.1, 10.sub.2 . . . 10.sub.n respectively include a noise code selector 30.sub.1, 30.sub.2 . . . 30.sub.n which are adapted to selectively control each of the desired noise code outputs of code mate pair generators 32.sub.1, 32.sub.2 and 32.sub.n and 34.sub.1, 34.sub.2 . . . 34.sub.n so that each input circuit is adapted to generate mutually different code mate pairs. As shown, code generators 32.sub.1 and 34.sub.1 are adapted to generate code mate pairs a.sub.1 and b.sub.1 whereas code generators 32.sub.2 and 34.sub.2 are adapted to generate code mate pairs a.sub.2 and b.sub.2, respectively. Each of the input circuits 10.sub.1, 10.sub.2 . . . 10.sub.n additionally include a pair of modulators 36.sub.1 and 38.sub.1, 36.sub.2 and 38.sub.2 . . . 36.sub.n and 38.sub.n. It can be seen, for example, that code generators 32.sub.1 and 34.sub.1 are coupled to modulators 36.sub.1 and 38.sub.1, respectively, and operate such that code mate a.sub.1 modulates the input signal S.sub.1 in modulator 36.sub.1 which is coupled to the linear adder 14 while code mate b.sub.1 modulates the input signal S.sub.1 via modulator 38.sub.1 whose output is coupled to the linear adder 16.

The input signal S.sub.1 modulated by the generated code mate pair a.sub.1 and b.sub.1 will transfer only to a selected output line 28.sub.1, 28.sub.2 . . . 28.sub.n coupled to output circuits 12.sub.1, 12.sub.2 . . . 12.sub.n whose noise code detectors are matched so that they are responsive to codes a.sub.1 and b.sub.1. Accordingly, the output circuits 12.sub.1, 12.sub.2 . . . 12.sub.n include respective code selectors 40.sub.1, 40.sub.2 . . . 40.sub.n which are coupled to decoders in the form of matched filters 42.sub.1, 44.sub.1, 42.sub.2 and 44.sub.2 . . . 42.sub.n and 44.sub.n. Additionally as shown, the various matched filters for code mates a.sub.1, b.sub.1, a.sub.2, b.sub.2 . . . a.sub.n and b.sub.n couple to respective linear adders 46.sub.1, 46.sub.2 and 46.sub.n wherein resultant compressed impulse signal outputs S'.sub.1, S'.sub.2 . . . S'.sub.n appear in a well known manner on lines 28.sub.1, 28.sub.2 . . . 28.sub.n.

Referring now to FIG. 2, the ith input and output circuits 10.sub.i and 12.sub.i are shown respectively coupled to the linear adders 14 and 16 and the busses 18 and 20 which additionally translate all codes a and b of different code mate pairs generated in the system shown in FIG. 1. What is additionally shown in FIG. 2 is a switch controller 48 coupled to the code selectors 30.sub.i and 40.sub.i for matching the codes a.sub.i and b.sub.i generated and detected by code generators 32.sub.i and 34.sub.i and the matched filters 42.sub.i and 44.sub.i. Also a clock 50 is shown coupled to the a.sub.i and b.sub.i code mate pair generators 32.sub.i and 34.sub.i. Its purpose is to start the generated codes a.sub.i and b.sub.i as well as all other codes at the same time. The clock 50 additionally is coupled to a gate generator 52 which is adapted to trigger a gate 54.sub.i at a time the detected code mate pairs a.sub.i and b.sub.i compress to an impulse output signal S.sub.i upon being added linearly by the linear adder 46.sub.i.

The code mate pairs a.sub.i and b.sub.i are of the general type disclosed in the aforementioned U.S. Pat. Nos. 3,461,451; 3,519,746; 3,634,765 but comprise a subclass thereof having an additional characteristic which permits different code mate pairs to be selectively switched concurrently between input and output lines 26.sub.1 . . . 26.sub.n and 28.sub.1 . . . 28.sub.n simultaneously without mutual interference therebetween. In order to fully understand the operation of the subject invention, it becomes necessary to describe the specific type or subclass of code mate pairs utilized.

As noted above, multiplexed noise codes are codes formed with mate pairs that compress to an impulse autocorrelation function upon detection. The autocorrelation function of two codes forming a mate pair must be of equal magnitude and opposite sense for all values of time outside of the main lobe. Expressed mathematically, for two code mate pairs a and b,

.phi..sub.a.sbsb.i (.GAMMA.)=-.phi..sub.b.sbsb.i (.GAMMA.) for all .GAMMA..noteq.0

where

.phi..sub.a.sbsb.i (.GAMMA.) is the autocorrelation function of code a.sub.i,

.phi..sub.b.sbsb.i (.GAMMA.) is the autocorrelation function of code b.sub.i, and

.GAMMA..sub.0 is the location of the main lobe.

When the two codes a.sub.i and b.sub.i meet this requirement, then the simple linear sum .phi..sub.Ti (.GAMMA.) of their orthogonally multiplexed outputs from matched filters 42.sub.i and 44.sub.i coupled to busses 18 and 20 result in compressing the composite code structure into a single impulse at time .GAMMA.=0.

As an illustration and for clarification, consider the use of the following mate code pair in the switching system as a result of the operation of code selector 30.sub.i of FIG. 2. For code a.sub.i =1000 and code b.sub.i =1011, the code selector 40.sub.i would compress these codes by autocorrelation as follows.

The output .phi..sub.a.sbsb.i (.GAMMA.) of the filter 42.sub.i, matched to code a.sub.i by providing an inversion sequence of 0001 where 0=0.degree. and 1=180.degree. phase reversal, is generated graphically below as,

    ______________________________________
    bit time slot
                1      2      3    4    5    6    7
    ______________________________________
                 0      1    0    0    0
    Inv.         0           1    0    0    0
    Seq.         0                1    0    0    0
                 1                     0    1    1    1
    .0..sub.a.sbsb.i (.GAMMA.) =
                1      .      0    0.sup.4
                                        0    .    1
    ______________________________________
     where 0 = + polarity bit
     1 = - polarity bit

    ______________________________________
    bit time slot
                1      2      3    4    5    6    7
    ______________________________________
                 1      0    1    0    0
    Inv.         1           0    1    0    0
    Seq.         0                1    0    1    1
                 1                     0    1    0    0
    .0..sub.b.sbsb.i (.GAMMA.) =
                0      .      1    0.sup.4
                                        1    .    0
    ______________________________________

    ______________________________________
    bit time slot
              1       2     3     4   5     6   7
    ______________________________________
    .0..sub.a.sbsb.i (.tau.)
              1       .     0     0.sup.4
                                      0     .   1
    .0..sub.b.sbsb.i (.tau.)
              0       .     1     0.sup.4
                                      1     .   0
    .0..sub.i (.tau.)
              .       .     .     0.sup.8
                                      .     .   .
     ##STR1##
    ______________________________________

                  TABLE 1
    ______________________________________
    Code Mate
    Pair No.      Code a subset
                             Code b subset
    ______________________________________
    1             1 0 0 0    1 0 1 1
    2             0 0 1 0    1 1 1 0
    3             0 1 0 0    0 1 1 1
    4             0 0 0 1    1 1 0 1
    5             1 0 0 0    0 1 0 0
    6             0 0 1 0    0 0 0 1
    7             0 1 0 0    1 0 0 0
    8             0 0 0 1    0 0 1 0
    ______________________________________


              TABLE 2
    ______________________________________
    Code Mate
    Pair No.      Code a subset
                             Code b subset
    ______________________________________
    1             1 0 1 0 0 0 1 1
                             1 0 0 1 0 0 0 0
    2             1 0 0 0 0 1 0 0
                             1 0 0 0 1 0 1 1
    3             0 1 0 0 1 0 0 0
                             1 0 1 1 1 0 0 0
    4             0 0 0 1 0 0 1 0
                             0 0 0 1 1 1 0 1
    5             1 1 0 1 0 0 0 1
                             1 1 0 1 1 1 1 0
    6             1 1 1 1 0 1 1 0
                             0 0 1 1 1 0 1 0
    7             0 1 0 0 0 1 1 1
                             0 1 0 0 1 0 0 0
    8             0 1 1 1 0 1 0 0
                             1 0 0 0 0 1 0 0
    9             0 1 1 1 1 0 1 1
                             1 0 0 0 1 0 1 1
    10            1 1 1 0 1 1 0 1
                             0 0 0 1 1 1 0 1
    11            0 0 1 0 1 1 1 0
                             1 1 0 1 1 1 1 0
    12            1 0 1 1 1 0 0 0
                             0 1 0 0 1 0 0 0
    13            0 0 1 0 0 0 0 1
                             0 0 1 0 1 1 1 0
    14            1 1 1 0 0 0 1 0
                             1 1 1 0 1 1 0 1
    15            0 0 1 1 0 1 0 1
                             1 1 1 1 1 0 0 1
    16            1 0 0 1 1 1 1 1
                             1 0 1 0 1 1 0 0
    ______________________________________

    ______________________________________
    a.sub.1           1     0         0   0
    a.sub.2
           X          0     0         1   0
    .SIGMA. = - + - + = = .0..sub.a.sbsb.2 a.sub.1 (0)
    ______________________________________

    ______________________________________
    b.sub.1           1     0         1   1
    b.sub.2
           X          1     1         1   0
    .SIGMA. = + - + - = 0 = .0..sub.b.sbsb.2 b.sub.1 (0)
    ______________________________________

    ______________________________________
    .0..sub.21 (0) =
                .0..sub.a.sbsb.2 a.sub.1 (0) + .0..sub.b.sbsb.2 b.sub.1 (0)
    =           0 + 0 = 0
    where
    .0..sub.a.sbsb.2 a.sub.1 (0) =
                crosscorrelation function value between
                codes a.sub.2 and a.sub.1 at .tau. = 0
    .0..sub.b.sbsb.2 b.sub.1 (0) =
                crosscorrelation function value between
                codes b.sub.1 and b.sub.2 at .tau. = 0
    .0..sub.2.sbsb.1 (0) =
                total crosscorrelation function value
                between multiplexed code pairs 2 and 1
                at .tau. = 0
    ______________________________________

    ______________________________________
    input circuit #2
                    0     0         1   0
    input circuit #3
                    0     1         0   0
    input circuit #4
                    0     0         0   1
    input circuit #5
                    1     0         0   0
    input circuit #6
                    0     0         1   0
    input circuit #7
                    0     1         0   0
    input circuit #8
                    0     0         0   1
    .SIGMA..sub.a = .sup. 0.sup.5
                          .sup. 0.sup.3
                                    .sup. 0.sup.3
                                        .sup. 0 .sup.3
    ______________________________________

    ______________________________________
    input circuit #2
                    1     1         1   0
    input circuit #3
                    0     1         1   1
    input circuit #4
                    1     1         0   1
    input circuit #5
                    0     1         0   0
    input circuit #6
                    0     0         0   1
    input circuit #7
                    1     0         0   0
    input circuit #8
                    0     0         1   0
    .SIGMA..sub.b = 0     1         0   0
    ______________________________________

    ______________________________________
    bit time slot
                1      2      3    4    5    6    7
    ______________________________________
                 0      0.sup.5
                             0.sup.3
                                  0.sup.3
                                       0.sup.3
    Inv.         0           0.sup.5
                                  0.sup.3
                                       0.sup.3
                                            0.sup.3
    Seq.         0                0.sup.5
                                       0.sup.3
                                            0.sup.3
                                                 0.sup.3
                 1                     1.sup.5
                                            1.sup.3
                                                 1.sup.3
                                                      1.sup.3
    .0..sub.a.sbsb.1 (.GAMMA.) =
                0.sup.5
                       0.sup.8
                              0.sup.11
                                   0.sup.4
                                        0.sup.3
                                             .    1.sup.3
    ______________________________________

    ______________________________________
    bit time slot
                1      2      3    4    5    6    7
    ______________________________________
                 1      1    0    1    1
    Inv.         1           1    0    1    1
    Seq.         0                0    1    0    0
                 1                     1    0    1    1
    .0..sub.b.sbsb.1 (.GAMMA.) =
                1      .      0    1.sup.4
                                        0    .    1
    ______________________________________

    ______________________________________
    bit time slot
               1      2      3    4    5    6    7
    ______________________________________
    .0..sub.a.sbsb.1 (.tau.)
               0.sup.5
                      0.sup.8
                             0.sup.11
                                  0.sup.4
                                       0.sup.3
                                            .    1.sup.3
    .0..sub.b.sbsb.1 (.tau.)
               1      .      0    1.sup.4
                                       0    .    1
    .0..sub.T.sbsb.1 (.tau.) =
               0.sup.4
                      0.sup.8
                             0.sup.12
                                  .tau.= 0
                                       0.sup.4
                                            .    1.sup.4
     ##STR2##
    ______________________________________

    ______________________________________
    .SIGMA..sub.a  0.sup.5
                         0.sup.3    0.sup.3
                                        0.sup.3
    input circuit #1
                   1.sup.
                         0.sup.     0.sup.
                                        0.sup.
    .SIGMA..sub.T.sbsb.a =
                   0.sup.4
                         0.sup.4    0.sup.4
                                        0.sup.4
    ______________________________________

    ______________________________________
    .SIGMA..sub.b  0     1          0   0
    input circuit #1
                   1     0          1   1
    .SIGMA..sub.T.sbsb.b =
                   .     .          .   .
    ______________________________________

    ______________________________________
    bit time slot
                1      2      3    4    5    6    7
    ______________________________________
                 0      0.sup.4
                             0.sup.4
                                  0.sup.4
                                       0.sup.4
    Inv.         0           0.sup.4
                                  0.sup.4
                                       0.sup.4
                                            0.sup.4
    Seq.         0                0.sup.4
                                       0.sup.4
                                            0.sup.4
                                                 0.sup.4
                 1                     1.sup.4
                                            1.sup.4
                                                 1.sup.4
                                                      1.sup.4
    .0..sub.a.sbsb.1 (.GAMMA.) =
                0.sup.4
                       0.sup.8
                              0.sup.12
                                   0.sup.8
                                        0.sup.4
                                             .    1.sup.4
                        ##STR3##
    ______________________________________

    ______________________________________
    .0..sub.T.sbsb.1 (.tau.) =
              0.sup.4 0.sup.8
                            0.sup.12
                                  0.sup.8
                                      0.sup.4
                                            .   1.sup.4
     ##STR4##
    ______________________________________

    ______________________________________
    input circuit #5
              1     1       0   1     0   0     0   1
    input circuit #7
              0     1       0   0     0   1     1   1
    .SIGMA..sub.a.sbsb.4 =
              .     .sup. 1.sup.2
                            .sup. 0.sup.2
                                .     .sup. 0.sup.2
                                          .     .   .sup. 1.sup.2
    ______________________________________

    ______________________________________
    input circuit #5
              1     1       0   1     1   1     1   0
    input circuit #7
              0     1       0   0     1   0     0   0
    .SIGMA..sub.b.sbsb.4 =
              .     .sup. 1.sup.2
                            .sup. 0.sup.2
                                .     .sup. 1.sup.2
                                          .     .   .sup. 0.sup.2
    ______________________________________

    __________________________________________________________________________
    bit time
    slot   1 2 3 4 5 6 7 8 9 10
                               11 12 13 14
    __________________________________________________________________________
         0 1.sup.2
             0.sup.2
               . 0.sup.2
                   . . 1.sup.2
         1   0.sup.2
               1.sup.2
                 . 1.sup.2
                     . . 0.sup.2
    Inv. 0     1.sup.2
                 0.sup.2
                   . 0.sup.2
                       . . 1.sup.2
    Seq. 0       1.sup.2
                   0.sup.2
                     . 0.sup.2
                         . . 1.sup.2
         1         0.sup.2
                     1.sup.2
                       . 1.sup.2
                           . . 0.sup.2
         0           1.sup.2
                       0.sup.2
                         . 0.sup.2
                             . .  1.sup.2
         0             1.sup.2
                         0.sup.2
                           . 0.sup.2
                               .  .  1.sup.2
         0               1.sup.2
                           0.sup.2
                             . 0.sup.2
                                  .  .  1.sup.2
    .0..sub.a.sbsb.4 (.GAMMA.) =
           1.sup.2
             0.sup.4
               1.sup.4
                 0.sup.2
                   0.sup.2
                     1.sup.2
                       . . 0.sup.2
                             . 0.sup.4
                                  1.sup.2
                                     1.sup.2
                                        1.sup.2
    __________________________________________________________________________

    __________________________________________________________________________
    bit time
    slot   1 2 3 4 5 6 7 8 9 10
                               11 12 13 14
    __________________________________________________________________________
         1 0.sup.2
             1.sup.2
               . 0.sup.2
                   . . 1.sup.2
         0   1.sup.2
               0.sup.2
                 . 1.sup.2
                     . . 0.sup.2
    Inv. 1     0.sup.2
                 1.sup.2
                   . 0.sup.2
                       . . 1.sup.2
    Seq. 1       0.sup.2
                   1.sup.2
                     . 0.sup.2
                         . . 1.sup.2
         1         0.sup.2
                     1.sup.2
                       . 0.sup.2
                           . . 1.sup.2
         0           1.sup.2
                       0.sup.2
                         . 1.sup.2
                             . .  0.sup.2
         0             1.sup.2
                         0.sup.2
                           . 1.sup.2
                               .  .  0.sup.2
         0               1.sup.2
                           0.sup.2
                             . 1.sup.2
                                  .  .  0.sup.2
    .0..sub.b.sbsb.4 (.GAMMA.) =
           0.sup.2
             1.sup.4
               0.sup.4
                 0.sup.2
                   1.sup.2
                     1.sup.2
                       . 0.sup.4
                           1.sup.2
                             1.sup.4
                               1.sup.4
                                  0.sup.2
                                     0.sup.2
                                        0.sup.2
    __________________________________________________________________________

    ______________________________________
    .0..sub.a4 (.tau.)
            1.sup.2
                  0.sup.4
                        1.sup.4
                            0.sup.2
                                0.sup.2
                                    1.sup.2
                                        .   .   0.sup.2 .
                                                     0.sup.4
                                                          1.sup.2 1.sup.2
    .0..sub.b4 (.tau.)
            0.sup.2
                  1.sup.4
                        0.sup.4
                            0.sup.2
                                1.sup.2
                                    1.sup.2
                                        .   0.sup.4
                                                1.sup.2 1.sup.4
                                                     1.sup.4
                                                          0.sup.2 0.sup.2
    .0..sub.T4 (]) =
            .     .     .   0.sup.4
                                .   1.sup.4
                                        .   0.sup.4
                                                .1.sup.4
                                                     ..   ..
     ##STR5##
    ______________________________________

    ______________________________________
    APPENDIX A
    ______________________________________
    1     0     0     0         1   0   1   1
    0     1     0     0         1   1   1   0
    -     -     +     +   .sym. +   -   +   -    = 0 = .0..sub.31 (0)
    1     0     0     0         1   0   1   1
    0     0     0     1         1   1   0   1
    -     +     +     -   .sym. +   -   -   +    = 0 = .0..sub.41 (0)
    1     0     0     0         1   0   1   1
    1     0     0     0         0   1   0   0
    +     +     +     +   .sym. -   -   -   -    = 0 = .0..sub.51 (0)
    1     0     0     0         1   0   1   1
    0     0     1     0         0   0   0   1
    -     +     -     +   .sym. -   +   -   +    =  0 = .0..sub.61 (0)
    1     0     0     0         1   0   1   1
    0     1     0     0         1   0   0   0
    -     -     +     +   .sym. +   +   -   -    = 0 = .0..sub.71 (0)
    1     0     0     0         1   0   1   1
    0     0     0     1         0   0   1   0
    -     +     +     -   .sym. -   +   +   -    = 0 = .0..sub.81 (0)
    0     0     1     0         1   1   1   0
    0     1     0     0         0   1   1   1
    +     -     -     +   .sym. -   +   +   -    = 0 = .0..sub.32 (0)
    0     0     1     0         1   1   1   0
    0     0     0     1         1   1   0   1
    +     +     -     -   .sym. +   +   -   -    = 0 = .0..sub.42  (0)
    0     0     1     0         1   1   1   0
    1     0     0     0         0   1   0   0
    -     +     -     +   .sym. -   +   -   +    = 0 = .0..sub.52 (0)
    0     0     1     0         1   1   1   0
    0     0     1     0         0   0   0   1
    +     +     +     +   .sym. -   -   -   -    = 0 = .0..sub.62 (0)
    0     0     1     0         1   1   1   0
    0     1     0     0         1   0   0   0
    +     -     -     +   .sym. +   -   -   +    = 0 = .0..sub.72 (0)
    0     0     1     0         1   1   1   0
    0     0     0     1         0   0   1   0
    +     +     -     -   .sym. -   -   +   +    = 0 = .0..sub.82 (0)
    0     1     0     0         0   1   1   1
    0     0     0     1         1   1   0   1
    +     -     +     -   .sym. -   +   -   +    = 0 = .0..sub.43 (0)
    0     1     0     0         0   1   1   1
    1     0     0     0         0   1   0   0
    -     -     +     +   .sym. +   +   -   -    = 0 = .0..sub.53 (0)
    0     1     0     0         0   1   1   1
    0     0     1     0         0   0   0   1
    +     -     -     +   .sym. +   -   -   +    = 0 = .0..sub.63 (0)
    0     1     0     0         0   1   1   1
    0     1     0     0         1   0   0   0
    +     +     +     +   .sym. -   -   -   -    = 0 = .0..sub.73 (0)
    0     1     0     0         0   1   1   1
    0     0     0     1         0   0   1   0
    +     -     +     -   .sym. +   -   +   -    = 0 = .0..sub.83 (0)
    0     0     0     1         1   1   0   1
    1     0     0     0         0   1   0   0
    -     +     +     -   .sym. -   +   +   -    = 0 = .0..sub.54 (0)
    0     0     0     1         1   1   0   1
    0     0     1     0         0   0   0   1
    +     +     -     -   .sym. -   -   +   +    = 0 = .0..sub.64 (0)
    0     0     0     1         1   1   0   1
    0     1     0     0         1   0   0   0
    +     -     +     -   .sym. +   -   +   -    = 0 = .0..sub.74 (0)
    0     0     0     1         1   1   0   1
    0     0     0     1         0   0   1   0
    +     +     +     +   .sym. -   -   -   -    = 0 = .0..sub.84 (0)
    1     0     0     0         0   1   0   0
    0     0     1     0         0   0   0   1
    -     +     -     +   .sym. +   -   +   -    = 0 = .0..sub.65 (0)
    1     0     0     0         0   1   0   0
    0     1     0     0         1   0   0   0
    -     -     +     +   .sym. -   -   +   +    = 0 = .0..sub.75 (0)
    1     0     0     0         0   1   0   0
    0     0     0     1         0   0   1   0
    -     +     +     -   .sym. +   -   -   +    = 0 = .0..sub.85 (0)
    0     0     1     0         0   0   0   1
    0     1     0     0         1   0   0   0
    +     -     -     +   .sym. -   +   +   -    = 0 = .0..sub.76 (0)
    0     0     1     0         0   0   0   1
    0     0     0     1         0   0   1   0
    +     +     -     -   .sym. +   +   -   -    = 0 = .0..sub.86 (0)
    0     1     0     0         1   0   0   0
    0     0     0     1         0   0   1   0
    +     -     +     -   .sym. -   +   -   +    = 0 = .0..sub.87 (0)

• Inventors
  Gutleber, Frank S.;
• Assignee
  The United States of America as represented by the Secretary of the Army (Washington, DC)
• Published
  Oct-2-1984
• Current US Classes:
  341/50
  370/208
  370/351
  370/479
  380/46
• Application #
  402476
• International Classes
  H03K 013/02
• Field of Search
  370/18-22 370/53 370/104 370/116 370/54 370/69.1 370/77 370/85 375/25 375/1 375/38 375/96 375/102-104 340/348 340/349 340/346 340/347 455/306 364/604 364/725 364/728 364/819 364/826
• Examiner
  Griffin; Robert L.
• Agent
  Lane; Anthony T., Kanars; Sheldon, Murray; Jeremiah G.
• US Patent References:
  4149030
  4293953
  4425562