Information signal transmission system5852663Abstract The information signal transmission system of the present invention is so designed as to convert the analog information signal into digital information data and to transmit these digital data after enciphering a part of the digital data. It can therefore maintain the secrecy of the transmitted information signal and can employ a low-speed enciphering process, thereby reducing the magnitude of hardware and reducing its cost. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 1
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+ side - side
Digitized representa- representa-
value tive value tive value
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0 0 0
1 1.about.4
1 -219 -219
2 5.about.10
5 -218.about.-215
-215
3 11.about.20
11 -214.about.-209
-209
4 21.about.35
21 -208.about.-199
-199
5 36.about.55
36 -198.about.-184
-184
6 56.about.79
56 -183.about.-164
-164
7 80.about.109
80 -163.about.-140
-140
8 110.about.139
110 -139.about.-110
-110
9 140.about.163
140 -109.about.-80
-80
10 164.about.183
164 -79.about.-56
-56
11 184.about.198
184 -55.about.-36
-36
12 199.about.208
199 -35.about.-21
-21
13 209.about.214
209 -20.about.-11
-11
14 215.about.218
215 -10.about.-5
-5
15 219 219 -4.about.-1
-1
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The digitizing characteristics shown in Table 1 are an example of the table for determining the positive or negative sign for predicted error data in a range from -219 to 219, utilizing the decoded values of already digitized data, thereby selecting a representative value, and is capable of achieving digitization with digitized levels corresponding to 5 bits, by assigning a digitized level of 4 bits to each of two digitizing steps in the positive and negative sides. Also Table 1 is so designed that two digitizing steps of the positive and negative sides, corresponding to a same digitized value, always have a level difference corresponding to the limited dynamic range (for example "220") of the decoded data, and is also designed as an undershoot type in which the representative value is taken at the lower end of each digitizing step. Consequently the results of decoding with the positive and negative representative values always have a level difference of "220", and only one of said results is contained in the dynamic range from "0" to "219". This fact enables to discriminate the sign of the difference value as will be explained later. In case of an image signal, the difference values in the vicinity of "0" are particularly important, and, there is employed a symmetrical structure with respect to the center at the positive and negative sides, in order to enable superposition of the non-linear characteristics. The sign determining decoding circuit 106 decodes the data released from said sign multiplex digitizing circuit 104, utilizing the predicted data released from the prediction coefficient multiplying circuit 103, and sends the decoded data to a delay circuit 107. Then, after a delay for a predetermined period (for example a sampling period) therein, the decoded data are subjected to the multiplication of a prediction coefficient in the multiplying circuit 103, and are supplied, as the predicted data, to said subtracting circuit 102 and said sign determining decoding circuit 106. In the following there will be explained the function of the sign determining decoding circuit 106 shown in FIG. 4, with reference to FIG. 5. Referring to FIG. 5, the 4-bit data from the sign multiplex digitizing circuit 104 shown in FIG. 4 are entered into a terminal 201, and supplied to a plus-side representative value setting circuit 202 and a minus-side representative value setting circuit 203. The positive and negative representative values released from said setting circuits 202, 203 are respectively added, in adding circuits 205, 206, to the predicted data supplied from the prediction coefficient multiplying circuit 103, shown in FIG. 4, through a terminal 204, and supplied as positive and negative decoded data to a selecting circuit 207. Since the outputs from the plus-side representative value setting circuit 202 and the minus-side representative value setting circuit 203 always have a mutual level difference of "220", either one of the-positive and negative decoded data supplied to the selecting circuit 207 is always outside the limited dynamic range from "16" to "235" within the 8-bit range ("0"-"255"). Thus correct decoded data can be obtained from the sign multiplexed input data, by selecting either one of the positive and negative decoded data, present in said dynamic range. For this purpose, the level of the decoded data obtained from the adding circuit 205 of the plus side is compared in a comparator 209 with a threshold value "236", and the selecting circuit 207 is controlled by the output of said comparator 209 to select either one of the positive and negative decoded data, for release through a terminal 208. In the following the sign determining operation in the present embodiment will be explained by specific examples. Let us assume a case in which the predicted data are "100" and the input data are "150". Since the prediction error is "+50" in this case, the sign multiplex digitizing circuit 104 generates "5" as the 4-bit digitized data according to Table 1. The sign determining decoding circuit 106 generates plus-side decoded data "136" and minus-side decoded data "-84", and the former is selected as the decoded data because it is within the appropriate dynamic range from "16" to "235". Also in case the input data are "50" and the prediction error is "-50", the sign multiplex digitizing circuit 104 generates "11". In this case the plus-side decoded data are "284" while the minus-side decoded data are "64", and the latter is selected in said dynamic range. In the following there will be explained, with reference to FIG. 6, the decoder 10 for decoding the data compressed by the compressor 2 and transmitted through the transmission channel 6 shown in FIG. 3. Referring to FIG. 6, the data transmitted through said channel 6 are entered, by every 4 bits, into an input terminal 301, and supplied to a plus-side representative value setting circuit 302 and a minusside representative value setting circuit 303. The positive and negative representative values respectively released from said setting circuits 302, 303 are added, respectively in adding circuits 304, 305, to the predicted data supplied from a prediction coefficient multiplying circuit 309, and supplied as positive and negative decoded data to a selecting circuit 306. Since the outputs from said setting circuits 302, 303 always have a mutual level difference of "220" because of the digitizing characteristics shown in Table 1, either one of the positive and negative decoded data supplied to said selecting circuit 306 is always outside the limited dynamic range "16"-"235". Thus correct decoded data, corresponding to the input data, can be obtained by selecting the one within said dynamic range. For this purpose the decoded data released from the plus-side adding circuit 304 is compared in a comparator 310 with a threshold value "236", and the selecting circuit 306 is controlled by the output of said comparator 310 to select either of the positive and negative decoded data, for release as 8-bit decoded data from an output terminal 307. Said decoded data are subjected to a delay of a sampling period in a delay circuit 308, and are then supplied to the prediction coefficient multiplying circuit 309, which calculates the predicted data by multiplying the decoded data, delayed by a sampling period, with the prediction coefficient, and sends said decoded data to the adding circuits 304, 305 for the decoding of the succeeding 4-bit input data. The decoding of the transmitted data is conducted by the above-explained structure. As will be apparent from Table 1, the transmitted 4-bit data are a code giving the representative value of the difference of the image data. Thus the decoding of the original image data is entirely impossible if even a bit, among said 4-bit data, is unknown. Thus the present embodiment is designed to maintain the secrecy of image transmission, by enciphering only one bit of said compressed 4-bit data for example by DES method. In the present embodiment, the enciphering is conducted only on the MSB of the transmitted data in compressed transmission of image data by the DPCM process, but it is also possible to encipher one of other bits than the MSB of the transmitted data. Also instead of enciphering on all the transmitted data corresponding to all the sample values of the image signal as explained in the present embodiment, the enciphering may be conducted on a bit or plural bits of transmitted data of every several sample points. Also the data compression method is not limited to DPCM, and, if the data are transmitted without compression, the enciphering may be applied only to the MSB of such transmitted data. Also the present embodiment has been limited to the transmission of an image signal, but the present invention is likewise applicable to other information signals, such as an acoustic signal. As explained in the foregoing, the enciphering of only a part of the information to be transmitted allows to maintain the secrecy in the transmission of information signal and to use a low-speed process in the enciphering, thereby reducing the magnitude of the hardware and also reducing the cost thereof. In the following there will be explained a second embodiment of the present invention. FIG. 7 is a block diagram of an information signal transmission system constituting a second embodiment of the present invention. The system shown in FIG. 7 is so designed to at first encipher and transmit 8-bit initial value data corresponding to a sample as an initial value, and then to transmit, in succession, 4-bit data corresponding to N samples (N being a positive integer), compressed according to said initial value data. At first an explanation will be given on the transmitting side. Referring to FIG. 7, there are shown an A/D converter 401 for converting an analog video signal into a digital video signal of 8 bits per sample; a compressor 402 for compressing the 8-bit digital video signal into 4-bit data; and an enciphering unit 403 for enciphering only initial value data to be explained later, based on 64-bit cipher key data confidentially determined in advance between the transmitter and the receiver. There are also shown a switch 404 for selecting either the initial value data (terminal b) enciphered according to a transmission format shown in FIG. 8 or the compressed data (terminal a); and a parallel-serial converter 405 for receiving said enciphered initial value data, compressed data and synchronization data (SYNC in FIG. 7) in parallel manner and serially releasing these data, for transmission to the receiving side through a transmission channel 406. Said channel 406 can be a recording system such as a tape or a disk, or a communication or broadcasting system such as a satellite, an optical fiber or a cable. In the receiving side, there are provided a serial-parallel converter 407 for converting the received data into parallel data; a switch 408 for separating the enciphered initial value data (terminal b) and the compressed data (terminal a) by detecting the synchronization data SYNC according to the transmission data format shown in FIG. 8; a decoder 409 for deciphering the enciphered initial value data; a decoder 410 for expanding the 4-bit compressed data to an 8-bit digital video signal according to the initial value data deciphered by the decipher unit 409; and a D/A converter 411 for converting the 8-bit digital video signal into an analog video signal. FIG. 9 is a block diagram showing an example of the compression 402 shown in FIG. 7, wherein same components as those in the compressor 2 in the first embodiment (FIG. 4) are represented by same numbers, and will not be explained further. Referring to FIG. 9, the input data limited to a predetermined dynamic range by the limiter 108 are supplied, through the output terminal 110, to the enciphering unit 403 shown in FIG. 7, and also to the terminal b of the switch 109. The terminal a of said switch 109 receives the predicted data released from the prediction coefficient multiplying circuit 103. The circuit shown in FIG. 9 constitutes a DPCM circuit for compressing a digital video signal of 8 bits corresponding to each sample, into 4-bit data. In the compression and transmission of information data by the DPCM process, an error generated in a part of data on the transmission channel propagates to the subsequently transmitted data, whereby the restoration of the original data at the receiving side becomes impossible. Consequently, in the use of the DPCM process, the uncompressed original data are transmitted as initial value data at a predetermined interval, thereby minimizing the propagation of the data error. In the compressor shown in FIG. 9, the switch 109 is connected to the terminal b for a sample period in every one or several scanning periods, but is connected to the terminal a in other periods, whereby the subtractor 103 is given the data from the limiter 108 instead of the predicted data from the prediction coefficient multiplying circuit 103 in every one or several scanning line periods to repeat the initial setting of the compressor. Also the switch 404 shown in FIG. 7 is shifted between the terminals a and b in linkage with said switch 109 in FIG. 9, whereby the 8-bit data released from the limiter 108 during the initial setting of the compressor are enciphered as initial value data in the enciphering unit 403 and released through said switch 404, while the compressed data are released through said switch 404 in other periods. FIG. 10 is a block diagram showing an example of the decoder 410 shown in FIG. 7, corresponding to the compressor shown in FIG. 9. In FIG. 10, same components as those in the decoder 10 in the first embodiment (cf. FIG. 6) are represented by same numbers, and will not be explained further. Referring to FIG. 10, the initial value data deciphered in the deciphering unit 409 in FIG. 7 according to the cipher key data are supplied, through an input terminal 311, to the terminal b of the switch 312. The terminal a of said switch 312 receives the predicted data released from the prediction coefficient multiplying circuit 309. Said switch 312 is shifted in linkage with the switch 408 shown in FIG. 7, wherein, while the switch 408 is connected to the terminal b, the adders 304, 305 are given the initial value data deciphered in the deciphering unit 409 according to the cipher key data, instead of the predicted data released from the prediction coefficient multiplying circuit 309, thereby achieving the initial setting of the decoder, whereas in other periods the compressed data supplied in the unit of 4 bits are expanded to 8-bit data in the decoder thus initialized by the initial value data. As explained in the foregoing, in the compressed transmission of video signal by the DPCM process which digitizes the difference between the values of mutually close sample points on the image frame, the restoration of the values of sample points succeeding to the initial sample point becomes utterly impossible if the initial value data corresponding to said initial sample point are unknown. In case the information signal to be transmitted is a video signal, it is necessary to transmit the initial value data in every one or several scanning-line periods as explained above, and the secrecy of image transmission can be maintained by enciphering said initial value data only, by means of the cipher key data. In the following there will be explained a third embodiment of the present invention. Said third embodiment employs block encoded transmission for the compressed transmission of image signal, and enciphers the initial value data only, among the data transmitted by said block encoded transmission method, by means of cipher key data. Said block encoded transmission method consists of dividing all the sample points constituting an image frame into sample block groups, each composed of plural sample points, transmitting a pair of data relating to the maximum and minimum values of all the sample data in each sample block as the initial value data, and also transmitting the compressed data digitized based on said paired sample data. FIG. 11 is a block diagram of a compressor 402, constituting the third embodiment and employed in the information signal transmission system shown in FIG. 7. A terminal 601 receives an n-bit digital image signal, obtained by sampling with a predetermined frequency and digitizing, in the A/D converter 401 in FIG. 7, a raster-scan analog image signal such as a television signal. Said digital image signal with 2.sup.n levels is supplied to a sample block cutout circuit 602. FIG. 12 illustrates the division of all the sample data into sample blocks. Said circuit 602 forms a block of l.times.m sample points, namely l sample points in the horizontal (H) direction and m sample points in the vertical (V) direction as shown in FIG. 12. The data output is conducted for each sample block thus formed. FIG. 13 illustrates a sample block, containing sample data D.sub.1'1 .about.D.sub.m,l. The digital image data from the sample block cutout circuit 602 are supplied to a maximum value detecting circuit 603, a minimum value detecting circuit 604, and a timing adjustment circuit 605. Thus, among all the sample data D.sub.1,1 .about.D.sub.m, l in each sample block, the maximum value D.sub.max and the minimum value D.sub.min are respectively detected by the maximum value detecting circuit 603 and the minimum value detecting circuit 604. On the other hand, the timing adjustment circuit 605 delays all the sample data by a time required for the detections of D.sub.max and D.sub.min in said detecting circuits 603, 604, and sends all the sample data of each sample block to a division value converting circuit 606, in a predetermined order, for example D.sub.1,1, D.sub.2,1, D.sub.3,1, . . . , D.sub.m,1, D.sub.1,2, . . . D.sub.m,2, . . . , D.sub.1,(l-1) . . . , D.sub.m,(l-1) D.sub.1,l, . . . , D.sub.m,l. In this manner all the sample data (D.sub.1,1 .about.D.sub.m,l) in each sample block and the maximum value D.sub.max and the minimum value D.sub.min thereof are supplied to the division value converting circuit 606, and division data (.DELTA..sub.1,1 .about..DELTA..sub.l,m) of k bits can be obtained by comparison of said sample data with digitizing levels obtained by dividing the interval between D.sub.max and D.sub.min into 2.sup.k levels, wherein k is an integer smaller than n. This digitizing operation is illustrated in FIG. 14A. As shown in FIG. 14A, .DELTA..sub.i,j is obtained as k-bit binary data. The k-bit division data .DELTA..sub.i,j and D.sub.max, D.sub.min of n bits thus obtained are converted into serial data respectively by parallel-serial converters 607, 607a, 607b, and D.sub.max, D.sub.min are supplied through a data selector 608 and an output terminal 609 to the enciphering unit 403 shown in FIG. 7, while the division data .DELTA..sub.i,j are supplied, through an output terminal 610, to the terminal a of the switch 404. The enciphering unit 403 enciphers the supplied D.sub.max, D.sub.min according to the cipher key data and supplies the enciphered data to the terminal b of said switch 404, which is suitably shifted to provide serial data as shown in FIG. 15, which shows the transmitted data format corresponding to a sample block. The data from said switch 404 is subjected to the addition of synchronization data SYNC in the parallel-serial converter 405, and are released to the transmission channel 406. The addition of the synchronization data in the parallel-serial converter 405 may be conducted in every sample block, or in every plural sample blocks- The timing of operations of the above-explained circuits is controlled by a timing signal supplied from an unrepresented timing controller. FIG. 16 is a block diagram showing an example of the decoder 410 shown in FIG. 7, corresponding to the compressor shown in FIG. 11. From the data transmitted through the channel 406, the synchronization data are separated by the serial-parallel converter 407 and supplied to an unrepresented timing controller, which determines the timing of functions of various circuits in the receiving-side, based on said synchronization data. The data supplied from said serial-parallel converter 407 are separated by the switch 408, into n-bit data D.sub.max, D.sub.min, and division data .DELTA..sub.i,j obtained by k-bit digitization of the sample data between D.sub.max and D.sub.min. The D.sub.max and D.sub.min are deciphered in the deciphering unit 409 according to the cipher key data and supplied through an input terminal 611 to the serial-parallel converter 625, while the division data .DELTA..sub.i,j are supplied through an input terminal 612 to a serial-parallel converter 625a. The maximum value data D.sub.max and the minimum value data D.sub.min of each sample block, converted into parallel data by the serial-parallel converter 625, are respectively latched by latch circuits 626, 627, and supplied therefrom to a division value inverse conversion circuit 628. On the other hand, the division data .DELTA..sub.i,j relating to the sample data in each sample block are supplied, in the predetermined sequence explained above, to the serial-parallel converter 625a, and then to the division value inverse conversion circuit 628. FIG. 14B illustrates the restoration of the representative values D'.sub.i,j of the original sample data from the data .DELTA..sub.i,j, D.sub.max and D.sub.min. As shown in FIG. 14B, the representative value is for example selected at the middle of each digitizing level, obtained by 2k divisions of the interval between D.sub.max and D.sub.min. The n-bit representative value data (D'.sub.1,1 .about.D'.sub.m,l) obtained from said inverse conversion circuit 628 are supplied, in the above-mentioned sequence in each sample block, to a scan converter 629, which converts said data into a sequence corresponding to the raster scanning, and sends thus obtained decoded sample data to the D/A converter 411 through an output terminal 630. As explained in the foregoing, in the compressed transmission of a video signal with the block encoding process, the restoration of sample points in a sample block becomes utterly impossible if the maximum value data and/or the minimum value data, constituting the initial value data, are not shown. Thus the secrecy of image transmission can be maintained by enciphering said initial value data only, according to cipher key data. As explained in the foregoing embodiments, in the encoded data transmission, the enciphering of only the initial value data not only maintains the secrecy of the information signals but also allows to employ a low-speed enciphering process, thereby reducing the magnitude of hardware and reducing the cost thereof.
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