Walsh function signal scrambler4052565Abstract A digital speech scrambler system allowing for the transmission of scrambled speech over a narrow bandwidth by sequency limiting the analog speech in a low-pass sequency filter and thereafter multiplying the sequency limited speech with periodically cycling sets of Walsh functions at the transmitter. At the receiver, the Walsh scrambled speech is unscrambled by multiplying it with the same Walsh functions previously used to scramble the speech. The unscrambling Walsh functions are synchronized to the received scrambled signal so that, at the receiver multiplier, the unscrambling Walsh signal is the same as and in phase with the Walsh function which multiplied the speech signal at the transmitter multiplier. Synchronization may be accomplished by time division multiplexing sync signals with the Walsh scrambled speech. The addition of the sync signals in this manner further masks the transmitted speech and thus helps to prevent unauthorized deciphering of the transmitted speech. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
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wal(0,.THETA.)
++++++++++++++++ wal(0,.THETA.)
wal(1,.THETA.)
++++++++-------- sal(1,.THETA.)
wal(2,.THETA.)
++++--------++++ cal(1,.THETA.)
wal(3,.THETA.)
++++----++++---- sal(2,.THETA.)
wal(4,.THETA.)
++----++++----++ cal(2,.THETA.)
wal(5,.THETA.)
++----++--++++-- sal(3,.THETA.)
wal(6,.THETA.)
++--++----++--++ cal(3,.THETA.)
wal(7,.THETA.)
++--++--++--++-- sal(4,.THETA.)
wal(8,.THETA.)
+--++--++--++--+ cal(4,.THETA.)
wal(9,.THETA.)
+--++--+-++--++- sal(5,.THETA.)
wal(10,.THETA.)
+--+ -++--++-+--+ sal(5,.THETA.)
wal(11,.THETA.)
+--+-++-+--+-++- sal(6,.THETA.)
wal(12,.THETA.)
+-+--+-++-+--+-+ cal(6,.THETA.)
wal(13,.THETA.)
+-+--+-+-+-++-+- sal(7,.THETA.)
wal(14,.THETA.)
+-+-+-+--+-+-+-+ cal(7,.THETA.). -wal(15,.THETA.) +-+-+-+-+-+
-+-+- sal(8,.THETA.)
##STR1## .THETA. axis
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It should be noted that there exists a sal and cal function for each Walsh index, except j=0. Wal(0,.theta.) assumes a constant value over the interval and is analogous to d.c. Just as any deterministic signal can be expressed in a Fourier series or transform involving weighted sums of sines and cosines of harmonics of a basic frequency, so can a signal be expressed in weighted sums of sal and cal functions of a basic sequency. Thus, as sine-cosine functions can be used to represent signals, so can Walsh functions. An interesting phenomenon of Walsh functions is seen in the multiplication process. As is well known, the product of two sine waves of different frequencies is the sum of two sine waves, one at the frequency sum and the other at the frequency difference. However, the product of two Walsh functions of different indices is a single Walsh function having an index equal to the modulo 2 sum of the original indices. If the two indices of the two Walsh functions to be multiplied are written as binary numbers, then the binary number of the index of the resulting product is formed by taking the modulo 2 sum of the binary numbers. Therefore, the product of a signal having a sequency spectrum with a sequency carrier results in the spectrum being shifted by the carrier sequency - a single sideband process. If the carrier sequency is inside the sequency spectrum, the sequency spectrum of the product is scrambled all about. As an example, take an information signal v(t) represented by a finite sum of Walsh functions; whereby: ##EQU2## If v(t) is multiplied by a Walsh function carrier, wal(3,.theta.), the result is: +C.sub.1 wal(2,.theta.) + C.sub.2 wal(1,.theta.) + C.sub.3 wal(0,.theta.) +C.sub.4 wal(7,.theta.) + C.sub.5 wal(6,.theta.) + C.sub.6 wal(5,.theta.) +C.sub.7 wal(4,.theta.) From this can be seen that the multiplication resulted in the coefficients retaining their initial values but they now weight different Walsh functions. Thus, the multiplication does not produce additional terms but only scrambles the sequencies with the given coefficients. Another interesting feature of Walsh function multiplication is that multiplying the product with the Walsh function carrier, wal(3,.theta.), restores the original signal elements. From this property of Walsh functions we developed a novel information signal scrambling apparatus. The information signal may be speech, music, video, or any other type of information bearing signal which will be assumed as speech since it is with respect to speech signals that it is contemplated the invention will be most useful. Incoming speech signals are processed by a Walsh function speech scrambler of the invention and then applied to a conventional transmission medium such as telephone wires, microwave transmission systems, or any other wired or wireless conventional channel. The specific transmission channel between transmitters and receivers used to carry the Walsh scrambled speech is conventional and does not, of itself, form a portion of the invention being described herein. In the ensuing discussion the Walsh function speech scrambler will be described with respect to a communications system using separate transmitters and receivers at each station. However, the circuitry described may be adapted to transceiver equipment. FIG. 1 is a block diagram of the Walsh function speech scrambler and descrambler of the present invention. Speech scrambling is accomplished at the transmitter in the following manner. Time variable, analog speech signals are applied to a low-pass sequency filter 2 wherein the analog speech signal is converted into a sequency limited pulse amplitude modulated (PAM) signal. As will be described in greater detail, the low-pass sequency filter is necessarily constructed as an integrate-and-dump circuit in which the integrator, continuously receiving the incoming speech signal v(t), is sampled just prior to the dump operation. The sample is then stored in a suitable memory, such as a capacitor, for a time interval T', where T' is the shortest time the highest selected index Walsh function retains a fixed polarity. The next sample is taken at time T'. Thus, sequency limiting is controlled by selecting the time interval T'. For speech scrambling systems, T' may be selected as 125 microsec. Such sampling is analogous to sampling a 4kHz band limited signal at the 8 kHz Nyquist rate when operating in the frequency domain. As the sequency filter 2 operates on the incoming speech signal, a Walsh function generator 4 synchronously generates a Walsh scrambling signal which is combined with the sequency limited PAM speech signal in Walsh multiplier 8. Since the Walsh scrambling signal is a time varying signal having a value of either +1 or -1, the multiplier 8 may take the form of a sign changer which multiplies the sequency filtered speech by .+-.1 as the Walsh function generator 4 dictates. The output of the multiplier 8 is Walsh scrambled speech. In the simplest embodiment of the invention, the sequency limited PAM speech signal is multiplied by a single Walsh function which, as previously explained, has the effect of scrambling the sequencies of a Walsh series with their coefficients. Added security is obtained when the Walsh function used to scramble the PAM speech signal is varied periodically in some predetermined manner known to the descrambler apparatus at the receiver. To accomplish periodic variation of the scrambling Walsh function there is provided a scrambling code sequencer 6. Sequencer 6 operates to generate digital code words each designating a different Walsh function. When a particular Walsh function is to be generated by the function generator 4, its digital code word is produced by the sequencer 6 and applied as the input to function generator 4. As will be described more fully, hereinbelow, descrambling is accomplished at a receiver by multiplying the received Walsh scrambled signal with the Walsh function used to form the scrambled signal. The descrambling Walsh function which is generated at the receiver must, of course, be in phase with the Walsh function modulating the sequency limited information signal. Thus, it is necessary to provide the system with a means for providing the receiver with information sufficient for it to generate the proper Walsh function in proper phase with the received scrambled signal whereby unscrambling can result. Various synchronization techniques which may be used to transmit the phasing information to the receiver are known. For example, synchronization information may be carried on a separate channel, in which case the synchronization information may take the form of user generated codes which in this case may be an additional Walsh function. Another approach is to transmit pilot signals along with the scrambled speech. Alternatively, a sync burst can be transmitted at the beginning of the transmission to properly phase the scrambling code sequencer and Walsh function generator at the receiver, after which the receiver would free run for the duration of the transmission. For more reliable synchronization, a sync signal can be transmitted along with the scrambled speech. It has been determined that it is particularly advantageous if the synchronization information is modulated on sync pulses interleaved in a time division manner between scrambled information samples. Thus, in a preferred embodiment of the invention sync signals are generated by a synch code generator 12 keyed to the scrambling code sequencer 6. The sync code generator is responsive to the digital code words from sequencer 6 to generate these sync signals. The sync signals are combined with the Walsh scrambled voice signal in a sync multiplexer 10. The output from the sync multiplexer 10 is applied to any conventional channel 16 to be transmitted to a receiver 20. The sync signals are recovered at the receiver and used to control an unscrambling code sequencer 30 which in turn dictates the Walsh function and its phase produced by a Walsh function generator 28. Considering the receiver 20 illustrated in FIG. 1, the scrambled speech with its sync signals, when such signals are transmitted, is removed from the channel in a conventional manner. The scrambled signal is applied to the amplitude recovery circuit 24 where the PAM form of the signal is restored by synchronously averaging and sampling. A sample timing circuit 22, which can be a phase locked loop, generates timing pulses for sample timing which are applied to the amplitude recovery circuit 24, Walsh function generator 28, and the sync recovery circuit 31. The output from circuit 24 is applied to the sync demultiplexer 26 which functions to remove sync signals from the scrambled speech. The recovered Walsh scrambled speech, without the sync signals, is applied to Walsh function multiplier 34. A second input to the multiplier 34 is the unscrambling Walsh function generated by the Walsh function generator 28. The Walsh function generator 28 is controlled by an unscrambling code sequencer 30 which causes generator 28 to generate the proper unscrambling Walsh function, in proper phase. The unscrambling code sequencer 30 is controlled by a sync recovery circuit 31, responsive to the sync signals carried by the received scrambled signal. As previously indicated, sync information is preferably transmitted by modulating sync pulses, time division multiplexed between scrambled information samples. The sync pulses may be amplitude modulated to form sync code words to which the sync recovery circuit 31 is responsive. Each code word represents a different Walsh function. Each interval of speech modulated by a particular Walsh function, termed herein a frame interval, includes a sync code word modulated on the sync pulses appearing in that interval. This code word identifies the modulating Walsh function. The sync recovery circuit 31 stores the sync code words identifying each of the possible scrambling Walsh functions and compares each of these with the incoming signals. When a match is detected, the proper unscrambling Walsh function is identified. The sync recovery circuit may comprise a correlator, a sync code word memory and confidence counter. These circuits and their operation are, per se, conventional and do not of themselves form a portion of the invention. The correlator functions to compare the received sync code words with each of the receiver stored sync code words during each frame interval. When a match is detected, a code word designator identifying the proper Walsh function to be generated by Walsh function generator 28 is loaded into a sequence shift register 44 forming a part of unscrambling code sequencer 30. Register 44 is shown in FIG. 4 and described in greater detail hereinafter. The sync confidence counter determines the relative validity of incoming sync information from the correlator. It maintains a state of zero confidence until two properly spaced correlations have been made, since in a start-up situation the probability of any correlation being valid is the same as for any other one. Thus, the confidence counter jumps to a state of TWO when there is a correlation at the proper interval from one received in the start-up situation. Valid correlations from that point on increment the counter and invalid correlations (no pulse from the correlator when anticipated) decrement the counter. In the zero-confidence state every correlation is assumed correct and is loaded into the sequence shift register 44. In a higher state, the load input to the sequence shift register 44 would be inhibited. With the proper Walsh function being generated in proper phase by the function generator 28 and applied to multiplier 34, the sequency limited speech is recovered at the output of multiplier 34. To convert the sequency limited speech back into its time varying analog form it is applied to low pass frequency filter 36. As previously indicated, transmission privacy is increased if several scrambling Walsh functions are used. A high degree of privacy is realized with thirty-one different Walsh functions. The thirty-one different functions are the first thirty-one, that is wal(1,.theta.) through wal(31,.theta.). This being the case, the following implementation of the present invention is given with reference to a scrambler having a Walsh function generator capable of generating wal(1,.theta.) through wal(31,.theta.). The details of the scrambling and descrambling circuitry, omitting sync, will now be explained with reference to FIGS. 1 and 2. Incoming voice signals are applied to the low-pass sequency filter 2 which is comprised of operational amplifier OP.sub.1, functioning as an integrate and dump circuit. The integrated speech is applied through emitter-follower transistor T.sub.1 to a transistor switch T.sub.2 which is preferably an MOSFET switch. Sample pulses are applied to the gate of transistor T.sub.2 rendering it conductive for approximately 1 microsec. to transfer the integrated speech sample stored on capacitor C.sub.1 of amplifier OP.sub.1 to capacitor C.sub.s. Each sample pulse is followed by a dump pulse of approximately 1 microsec. duration rendering transistor T.sub.0 conductive thus discharging capacitor C.sub.1. Transistor T.sub.0, like transistor T.sub.2 and the other switching transistors to be described, is preferably an MOSFET. Timing of the sample and dump pulses to transistors T.sub.2 and T.sub.0 respectively is controlled by the 8kHz system clock 35, and single-shots 32 and 33. A clock pulse to the input of single-shot 32 causes a 1 microsec. pulse output rendering transistor T.sub.2 conductive for substantially the length of the single-shot 32 output pulse. The trailing edge of the output from single-shot 32 triggers a single-shot 33 rendering T.sub.0 conductive after transistor T.sub.2 becomes non-conductive. Thus, once every 125 microsec., the average value of the speech signal over the preceding 125 microsec. is stored on capacitor C.sub.s and dumped from integrating capacitor C.sub.1. In this manner there is developed a sequency limited pulse amplitude modulated (PAM) signal representing the incoming analog speech. The PAM signal is then applied to the Walsh function multiplier 8, comprised of operational amplifier OP.sub.2 and transistor T.sub.3, through isolation amplifier A.sub.1 and blocking capacitor C.sub.2. The multiplier operates as a sign changer in the following manner. The gate of transistor T.sub.3 is coupled to the output of Walsh function generator 4 to receive a Walsh function from generator 4 having a value of either .+-.1 at any point in time. When the Walsh function is at a +1 value of logic high, transistor T.sub.3 is conductive and the sequency limited speech is passed through amplifier OP.sub.2 with its polarity unaffected. However, when the scrambling Walsh function is at -1 or a logic low, transistor T.sub.3 is non-conductive causing the sequency limited speech to be applied to the inverting terminal of amplifier OP.sub.2. The resulting output from the amplifier OP.sub.2 is a Walsh scrambled signal which is the product of wal(M,.theta.) and the sequency limited speech. FIG. 3 is a graphical representation of the multiplier operation with wal(12,.theta.) as the scrambling Walsh function. The Walsh scrambled speech is then applied to a conventional transmission channel for transmission to a receiver. At the receiver, the Walsh scrambled speech is separated from the channel and applied through amplifier A.sub.2 to sequency limited speech recovery circuitry in this preferred embodiment an integrating amplifier OP.sub.3. Integrating amplifier OP.sub.3 functions to recover the amplitude level of each received scrambled sequency limited signal sample by determining the average value during the symbol duration. The average value is sampled by transistor T.sub.5 which is rendered conductive for a sampling interval once every 125 microseconds. An alternate method is to apply the output of amplifier A.sub.2 directly to transistor T.sub.5 and trigger transistor T.sub.5 conductive near the middle of the signal interval to capture the peak value of the received signal for that interval. The sampling pulse to gate S of transistor T.sub.5 and the dump pulse to the gate D of transistor T.sub.4 are generated by a phase locked loop which locks the receiver clock to the received scrambled signal and which forms sample timing circuit 22. The integrating amplifier OP.sub.3, transistor T.sub.7, sampling transistor T.sub.5 and storage capacitor C.sub. s ' form the amplitude recovery circuitry 24 of FIG. 1. The recovered scrambled sequency limited signal is applied to sign changing amplifier OP.sub.4 and transistor T.sub.6 which together form the multiplier 34 of FIG. 1. The gate of transistor T.sub.6 is connected to Walsh function generator 28 generating the unscrambling Walsh signal wal(M,.theta.). Remembering that the scrambled sequency limited signal is the product of wal(M,.theta.) and the sequency limited speech, and that the multiplication of that product with wal(M,.theta.) recovers the sequency limited speech, the output of amplifier OP.sub.4 is the sequency limited speech. To recover the continuous time varying analog speech v(t) the output from amplifier OP.sub.4 is passed through a 200-3500 Hz band-pass filter. In place of the band-pass filter, a low-pass filter with cut-off at 3500 Hz coulld be used. The Walsh function generator 4 or 28 and scrambling code sequencer 6 or 30 will now be described in detail with reference to FIG. 4. The Walsh function generator and code sequencer at the transmitter and receiver are identical. The scramblng code sequencer may take the form of a pseudorandom sequence generator with five parallel outputs driving the Walsh function generator 4 or 38. The five bit code word is necessary to identify any one of the thirty-one available Walsh functions. The sequencer circuitry can take any one of several forms. The underlying principal must, however, be followed; namely, the storing of Walsh function generation codes (each representing a different Walsh function) and calling them from memory in sequence. In one embodiment, the sequencer 6 or 30 comprises N memories 39, each including a register 40 or other five bit storage means and gates 42, one gate associated with each stage of register 40. The sequencer further includes an M bit circulating ONE sequence shift register 44. The output from each stage of register 44 is connected, in a user selected manner, to one of the memories 39 and more specifically to the enabling input of each set of gates of the memory. In operation, the gates 42 of the memory 39 coupled to the stage of register 44 storing the logic high are enabled allowing the Walsh function code stored in register 40 to pass to the Walsh function generator 4 through OR gates 45. If M is selected as eight and N as five, three of the memories 39 receive two OR-ed inputs from register 44. The scrambling code generator at the transmitter and receiver are coded identically. With M eight and N five there is an eight step sequence of five Walsh functions (three are repeated). This arrangement allows for more than 130 billion different control setting permutations, permitting over nine billion different sequences. The scrambling code sequencer 6 may also take the form of a sequence shift register 41 in combination with a diode matrix as shown in FIG. 5. The circulating "0" in the M-bit register sequences through the N 5-bit words stored on the diodes in a user-selected order. When the "0" appears on a horizontal row (A, B, C, D, etc.), the intact diodes on that row pull down the logic connected to the outputs a.sub.1 to a.sub.5, which in this case is the Walsh function generator 4. This implementation is for TTL, although it is readily adaptable to other logics. Programming sequence codes into the memory is accomplished by burning out unwanted diodes. For example, to encode row A with 10010, Diodes A1 and A4 would be burned out, leaving a.sub.1 and a.sub.4 high when row A is strobed by the "0" in the M-bit register. The Walsh function generator 4, 28 is shown in FIG. 4 as comprising an arrangement of NAND gates 46-50 and exclusive NOR gates 51-54. The inputs a.sub.1 through a.sub.5 of NAND gates 46-50 are connected, respectively, to the outputs a.sub.1 -a.sub.5 of the OR gates 45 in the scrambling code sequencer 6. The second input to each of the NAND gates 46-50 is connected to a counter 80 triggered by the 8 kHz system clock. Inputs a.sub.1 -a.sub.5 specify a particular Walsh function in the form of five bit codes stored in the registers 40. Generator 4 operates on the principle of exclusive-NOR addition of the bits of the sequence control code applied to inputs a.sub.1 -a.sub.5 of gates 46-50. Timing is accomplished by the use of binary counter 80 clocked by the system 8 kHz clock. The Walsh functon generator operates in the following manner. An 8 kHz square wave clock is applied to the 5-bit binary counter 80 which has 5 output ports. The output of the first port (2.sup.1) is the 8 kHz clock divided by 2 to produce the complement of the 31-st Walsh function, wal(31,.theta.). The output of the second port (2.sup.2) is the 8 kHz clock divided by 4 to produce the complement of the 15-th Walsh function, wal(15,.theta.); etc. The counter is phased such that when the output of the fifth port (2.sup.5), wal(1,.theta.), goes low, all other output ports transition from high to low at the same instant. When these outputs are inverted by flip-flops 84,86, and NAND gates 46-50, the Walsh functions 1, 3, 7, 15 and 31 are produced all properly phase aligned. The flip-flops 84 and 86 provide wal(1,.theta.) and wal(31,.theta.) for control purposes. The Walsh function at the output of flip-flop 90, wal(M,.theta.), is determined by the logic level inputs on a.sub.1, a.sub.2, a.sub.3, a.sub.4, and a.sub.5 from the scrambling code sequencer 30 or 6. Assume that Walsh function designator (a.sub.1, a.sub.2, a.sub.3, a.sub.4, a.sub.5) is logically written (10110). This is the Gray code for the desired Walsh function written with the least significant digit first, progressing to most significant digit last. More specifically,, the code 10110 is the Gray code for the decimal number 9 which is represented by the binary equialent 01001 written in the normal notation with the more significant digits to the left. With a.sub.1, a.sub.3, and a.sub.4 set to logic ONE, the outputs of NAND gates 46, 48, and 49 are wal(1,.theta.) wal(7,.theta.) and wal(15,.theta.), respectively, while the outputs of gates 47 and 50 are at logic ONE. The exclusive-NOR gates 51-54 are equivalent to algebraic multipliers when a logic ONE is equivalent for +1 and the logic ZERO is equivalent to -1 as it is here. Therefore, the output of exclusive-NOR gate 51 is the product of wal(0,.theta.) and wal(7,.theta.) which is wal(7,.theta.). Exclusive-NOR gate 52 output is the product of wal(15,.theta.) and wal(0,.theta.) which is wal(15,.theta.). Exclusive-NOR 53 output is the product of wal(15,.theta.) and wal(7,.theta.) which is wal(8,.theta.); that is, the bit-by-bit modulo 2 sum of the binary number notation for 7 and 15 (00111 + 01111) is 8 (01000). Exclusive-NOR gate 54 output is the product of wal(1,.theta.) and wal(8,.theta.) which is wal(9,.theta.); that is, the bit-by-bit modulo 2 sum of the binary number notation for 1 and 8 (00001 + 01000) which is 9 (01001). The flip-flop 90 merely provides a retiming for the output of the exclusive-NOR 54 to remove the propagation delay ripples through the gates and to synchronously retime the output selected Walsh function. As previously mentioned, when synchronization information is to be transmitted with the scrambled speech, it has been found advantageous to transmit such information by time division multiplexing (TDM) short duration sync pulses with the scrambled speech samples. Such sync pulses may be multiplexed with the scrambled speech between every sixteen scrambled signal samples resulting in a 6% increase in the transmission symbol rate. An important advantage is realized with the TDM method of transmitting synchronization information. The inclusion of the sync pulses in this manner has the effect of further masking the speech signal for added privacy. Time division multiplexing sync pulses provides greater masking than mere addition of these pulses to the scrambled signal in that the multiplexing process provides time distortion. Of course, both a sync pulse and a separate masking signal may be time division multiplexed with the Walsh scrambled speech. However, it is particularly convenient if the sync and masking signals are one and the same. FIGS. 6 and 7 illustrate the multiplexing technique. The Walsh scrambled signal which is of PAM structure is applied to sync multiplexer 10 along with sync pulses generated by the sync code generator 12. The multiplexer 10 operates to squeeze seventeen amplitude sample pulses into the time previously occupied by sixteen pulses, with the seventeenth pulse being the sync pulse. To accomplish this, the multiplexer 10 operates to sample the incoming scrambled speech in PAM form at a rate 17/16 times as fast as the original timing rate. The multiplexer is thus clocked at the rate of 8.5 kHz. FIG. 8 illustrates one embodiment of the sync multiplexer 10. Each scrambling code word designator from sequencer 6 may designate a sixteen bit sync code word generated by sync code word generator 12. Counter 57 is clocked by the 8.5 kHz clock to a count of sixteen. The sixteenth cound causes the generation of an inhibit sample pulse which inhibits the scrambled speech from passing through the sample and hold circuit 55 during the seventeenth sampling interval while causing switch 56 to assume the position shown in FIG. 8 allowing one bit of the sync code word to enter the scrambled speech bit stream during the seventeenth bit interval. The amplitude of the sync pulse from generator 12 designates it as a logic 1 or logic 0. A sixteen bit sync code word would then be included among 256 data bits with 272 bits being transmitted over an interval previously containing 256 bits. At the receiver, the modulated sync pulses are applied to the sync recovery circuit 31 and to demultiplexer 26 which may be as shown in FIG. 9 and operates to sample the received PAM structured scrambled speech 16/17 as fast as the high sampling rate of 8.5 kHz, namely 8 kHz. The 8 kHz sampling of the scrambled speech time division multiplexed with the sync pulses causes the sync pulses to fall between the sample windows and consequently be removed entirely. The demultiplexing technique is illustrated in FIG. 7. FIG. 9 illustrates an embodiment of a sync multiplexer combined with a demultiplexer. When switch 81 is set to the transmit line, switches 89 and 63 are closed permitting the scrambled speech to enter the sample and hold circuit 83, while AND gates 87, 85 and 60 are enabled. Under these conditions, the 8.5 kHz clock triggers the single-shot 62 through OR gate 64 to produce 1 microsec. sampling windows, while counter 66 counts to sixteen. The trailing-edge of the sixteenth pulse from the 8.5 kHz clock causes counter 66 to produce a sync enable pulse on line 67 closing switch 68 to block the scrambled speech from the channel during the interval of the sync enable pulse. In addition, the sync enable pulse sets flip-flop 70, disabling AND gate 87, while a bit from the sync code generator 12 passes through AND gate 60 to the channel. As shown in the sync multiplex-demultiplex timing diagram of FIG. 10, the next leading edge of the 8.5 kHz clock resets flip-flop 70 to remove the inhibit pulse. When operating as a demultiplexer, switch 81 is switched to the receive line to enable AND gate 72, while closing switches 74 and 76. Under these conditions, single-shot 62 is triggered at the 8.0 kHz rate through OR gate 62 thereby removing every seventeenth bit from the received signal. When the two clocks are properly synchronized, the seventeenth bit is the sync pulse. What has been described is a unique signal scrambler which makes use of digital technology while producing a narrow-band scrambled information signal which can be transmitted over conventional radio and telephone channels. Added masking of the already scrambled information signal may be accomplished by time division multiplxing sync signals between scrambled information bits.
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