Synchronous universal binary scrambler4187392Abstract 1. A synchronous binary cryptographic system responsive to an input synchronous telegraph signal comprising means for generating timing pulses of substantially fixed, predetermined frequency, means for generating a synchronous binary cryptographic key in synchronism with timing pulses applied thereto by said means for generating timing pulses, switch means actuated by a predetermined input signal sequence for applying the timing pulses to said means for generating the binary cryptographic key, said cryptographic key generating means being continuously responsive to said timing pulses during operation of the system and means for combining said input signal with the cryptographic key. Claims I claim: Description The present invention relates generally to cryptographic telegraphy systems and more particularly to a synchronous, full-duplex transmitting and receiving cryptographic terminal-equipment capable of universal application to binary signals of constant rate.
______________________________________
PULSE FREQUENCY DIVISION PROCESSES FOR
AVAILABLE TIME-DIVISION MULTIPLEX SYSTEMS
OPER-
ATING
SPEEDS 60 WPM 75 WPM 100 WPM
MUX
CLOCK- systems
RATES Teletype 54 KC 54 KC 46-22/23 KC
Rixon 54-9/16 KC 54-9/16 KC
47-41/92 KC
Pulse at terminal 301
RING NOS. 1 2 3 4 1 2 3 4 1 2 3 4
No. Channels
(EFFECTIVE STAGES)
______________________________________
16 9 5 - - 9 4 - - 6 4 - -
12 6 5 2 - 6 4 2 - 4 4 2 -
8 9 5 2 - 9 4 2 - 6 4 2 -
4 9 5 4 - 9 4 4 - 6 4 4 -
3 6 5 4 2 6 4 4 2 4 4 4 2
2 9 5 4 2 9 4 4 2 6 4 4 2
(1) 9 5 4 4 9 4 4 4 6 4 4 4
______________________________________
HIGH-SPEED SINGLE-CHANNEL SYSTEMS
CLOCK- RING NOS.
BIT-RATE
SYSTEM RATES 1 2 3 4
______________________________________
4800/Sec
DDDS 48 KC 5 - - -
2400/Sec
DDDS 48 KC 5 2 - - (Effective
Stages)
2226/Sec
NTDS 44.52 KC 5 4 - -
1360/Sec
NTDS 54.4 KC 5 4 - -
1300/Sec
SAGE 52 KC 5 4 - -
1200/Sec
DDDS 48 KC 5 4 - -
1100/Sec
SAGE 55 KC 5 5 - -
1000/Sec
Facsimile 48 KC 8 3 - -
750/Sec
SAGE 48 KC 8 4 - -
600/Sec
DDDS 48 KC 8 5 - -
______________________________________
The automatic phase-corrector unit 300 is well known and does not require detailed disclosure herein. As shown in FIG. 3, clock pulses are coupled to phase-corrector 300 via input terminal 301 and normally pass through undisturbed to the first stage driving unit 381. The incoming signal from the line or the associated local transmitting unit is coupled to phase-corrector 300 via input terminal 302: the internally generated square-wave reference signal from flip-flop 370 is also coupled to automatic phase corrector unit 300. The 300 unit senses the space-to-mark transitions of the incoming signal which are better defined and more stable than the mark-to-space transitions and compares them with the leading edge of the square wave reference signal from flip-flop 370. To avoid jitter the 300 unit is so designed and so biased that there is a narrow zone of no correction amounting to about 5% of a bit-length (i.e. baud-length) at the leading edge of the square-wave reference signal. If the space to mark signal transition is separated from the leading edge of the flip-flop square wave, phase corrector 301 automatically changes the timing pulse phase to coincide with that of the input signal in a well known manner. After initial synchronization, the space/mark transition should "ride" within this neutral zone, hour-after-hour. When the transition falls outside this neutral zone a correction is made. If within the MARK half of the reference square wave the scrambler has drifted "ahead" of the incoming binary signal, and the scrambler must be retarded; therefore a one-shot multivibrator whose period is one and one half clock pulse intervals is triggered, and serves to inhibit the next clock pulse. If within the SPACE half of the reference square wave, the scrambler has drifted "behind" the incoming binary signal the scrambler must be advanced; therefore a one-shot multivibrator whose period is one-half clock pulse intervals is triggered, and injects an extra "clock" pulse half way between the normal clock pulses from the clock 102. To combat jamming and bad multipath conditions, the automatic phase corrector 300 can be bypassed by a manual switch (not shown) which excludes corrector 300 from the circuit and couples clock pulse terminal 301 directly to 381. During initial synchronization there is always the possibility that the receiving scrambler will "phase-in" one-bit behind or one-bit ahead of the transmitting scrambler. There is also the remote possibility that the receiving scrambler may not correctly receive the transmitted "start pattern" until the second or third repetition thereby starting 1, 2 or more pattern lengths behind the transmitter. To overcome such out of phase relationship, a manual corrector system comprising cores 354 and 355 is provided which advances or retards the receiving key-generator, by adding or deleting one timing pulse at a time. The voltage readout of magnetic flip-flop stage 352 is coupled to a driving amplifier 386 which drives the timing windings of manual corrector cores 353, 354 and 355 at the output bit-rate at terminal 399 but 180 degrees out of phase with the normal timing pulses. Cores 354 and 355 are normally not loaded are therefore readout ZEROS in response to the pulses from amplifier 386. Core 354 is loaded by operation of the manual advance loading circuit 357, when the operator believes the local clock pulse source is behind the received signal. The next drive pulse from driver 386 reads out a voltage pulse from core 354 which is coupled to the timing pulse terminal 399 via an isolating diode and amplifier 387. This serves to inject an extra timing pulse half-way between two normal timing-pulses because of the out of phase relationship of the pulses from amplifier 386 and advances the associated key-generator 114 by 1 bit. Core 353 is a buffer stage which is loaded (in series with 351) by current readout from core 352. Core 355 is loaded by operation of the manual retard loading circuit 358, which is activated when the operator believes the local clock pulse source is ahead of the received signal. The next drive pulse from driver 386 reads out a current pulse from core 355 through the inhibit winding of core 356 and reads out a current pulse from buffer stage 353 through the input winding of core 356, but the core 355 readout through the inhibit winding blocks the loading of core 356. Core 356 normally reads out alternate ONE's (in phase with the output signal) and ZERO's (out of phase with the output signal) voltage pulses to timing pulse terminal 399, via an isolating diode and amplifier 387 in response to the signal from amplifier 385, which is twice the frequency of the signal applied to the input winding from buffer core 353. When a load is inhibited, core 356 reads out three ZERO's in a row in response to the signal applied to its timing winding, thereby dropping one timing pulse and retarding the associated key-generator by 1 bit. In FIGS. 4 and 5 of the drawings, unless otherwise indicated, each circle is indicative of a magnetic core binary logical element and the leads coupled thereto are connected to respective core windings. Driving pulse signals are fed to the cores by the lead connected to the bottom of each core. An input pulse on the lead connected to the lefthand side of each core will normally result in an output pulse on the lead connected to the righthand side at the next time a driving pulse is applied to the core. PUlses applied to the upper input terminal of each core, as shown on the drawings, serve to block or inhibit the generation of an output pulse on the righthand output lead, even when a pulse is generated on the lefthand input lead. Thus, it should be apparent that the leads emanating from the bottom, left, top and right of each circle may be considered as connected to the timing, input, inhibit, and output windings, respectively, of a particular core. It will be understood, therefore, that each core and its associated circuitry serves as an inhibit or "not" binary logical circuit. A logical "or" circuit which produces an output signal of "one" polarity when any or all of the input signals applied thereto are of the "one" polarity is formed by feeding the output signals of two or more binary core circuits through separate diodes and connecting the diodes together at a single terminal. In Boolean algebra terminology it is the general practice to designate an "or" operation by the symbol +. A binary "and" circuit is formed by cascading the output signals of two magnetic core circuits, i.e. applying the output signal of a first core to the inhibit terminals of a second core and applying a first signal to the inhibit winding of the first core and a second signal to the standard input winding of the second core. In Boolean algebra terminology the "and" operation signifies that all of the input signals applied to a particular stage must be equal to "one" in order to obtain a "one" output signal. The "and" function is normally represented by the multiplication of two variables. FIGS. 4 and 5 of the drawings, a schematic representation of the key generators 114 and 124, comprises a shift register 11 having nine magnetic cores 17 20. Each of these cores is simultaneously supplied with driving or timing pulses from amplifier 387. The driving pulses cuase the stored signal state in each stage to be transferred to the succeeding stage to which it is connected. Each stage of the shift register comprises a standard bistable magnetic core, an associated temporary storage capacitor and suitable pulse shaping and delaying networks between it and the next stage. Since this shift register construction is well known in the art it is not deemed necessary to explicitly disclose the circuitry employed. Prior to the operation of the device, spring biased switch 23 is manually brought into contact with terminal 24. Thus the B+ source coupled to terminal 24 by way of terminal 25 and switch 23 applies a prolonged advance pulse to all of the cores of the system. This pulse switches all of the cores to the "zero" state and holds them in this condition while the associated temporary storage capacitors are discharged through the input windings of the next core. This erases any "ones" previously stored in the cores in a manner well known to those skilled in the art. In this disclosure negative saturation of the magnetic cores is to be interpreted as a zero binary signal. Four feedback shift registers 11, 27, 28 and 29 having 11, 13, 17 and 19 stages, respectively, the numbers 11, 13, 17 and 19 being different co-prime numbers, are employed to produce signals having recurrance durations of 2.sup.N -1 bits; where N is the number of stages in each register. Preloading of cores 311, 321, 331, 341, 351 and selectively of core 911 as well as certain selected stages in each shift register 11, 27, 28 and 29 is achieved when spring bias switch 23 is released from terminal 24 and is swept past loading terminal 26 to operating terminal 31. This causes the magnetic cores selected by the load selector switches 32, 33, 34 and 35, associated respectively with shift registers 11, 27, 28 and 29, to change state from "zero" to "one", thereby preloading certain binary information therein. The number of load selector switches utilized depends upon the number of stages in each of the shift registers, i.e. shift register 11 having nine magnetic cores requires nine different switches, while shift registers 27, 28 and 29 having 11, 15 and 17 cores, respectively, require load selector switches having capacities equal to the number of stages contained therein. While load selector switches 32 have been shown as being of the toggle switch variety, it is to be understood that it may be more desirable to employ multi-position rotary switches for ease of operation and for compactness of size. By actuating any desired load switches it is to be understood that the number of preloaded stages in any of the respective shift registers may be varied in accordance with any particular binary coded information. After switch 23 returns to its normal position wherein switch 23 alights on terminal 30, timing pulse amplifier 387 is coupled into the circuit and simultaneously supplies timing pulses to each of the magnetic cores employed in the complete circuit. It is to be understood that suitable amplifiers may be needed to drive strings of six or eight of the magnetic stages in series at one time. The type and number of amplifiers utilized is within the skill of the art and may be determined by ordinary design techniques. As timing pulses are supplied to each shift register stage, the binary signal stored therein is transferred from one core to the next core. Thus, if it is assumed that cores 12, 13 and 14 store the quantities "one", "zero", "one", respectively, prior to the occurrence of a drive pulse, these cores will shift their pulses to the next cores so that cores 13, 14 and 15 will be stored with the values one, zero, and one, subsequent to the next clock pulse. Selected stages of each shift register 11, 27, 28 or 29 are connected to a respective feed back mixer circuit 36, 37, 38 or 39. Two or four register stages are connected to the feed back mixer logical circuit, depending upon the desired capacity of the machine. In order to effectively utilize each stage of all of the shift registers, it is necessary to connect the last stage of each shift register to the feedback mixer circuit to which it is associated. Connections between the shift register and the feed back mixers may be accomplished by conventional removable plug board connectors. These interconnections may be periodically changed so as to change the preprogramed output signal of the unit. The logical circuitry associated with each of the feed back mixers is such that a binary output signal having a particular polarity, e.g., "one", will be produced when all but one of the input signals to the feed back mixer circuit are the same. In other words, if all of the signals supplied to mixer 36 are of the same state, either "zero" or "one", a "zero" output pulse will be obtained from that feed back mixer. Likewise if a pair of signals supplied to mixer 36 are identical and another pair are oppositely identical, a "zero" signal will be obtained from mixer 36. With four signals supplied to mixer 36, a "one" signal will be obtained at its output terminal only when three of the signals applied thereto are identical and the other signal is of opposite polarity. If "one" signals coupled to plug board terminals 41, 42, 43 and 44 are indicated by X, Y, Z and N, respectively, and "zero" signals applied to these terminals are respectively indicated as X, Y, Z and N, (X is usually read "not X" or the complement of X), the Boolean function obtained from feedback mixer 36 on lead 45 may be given by the function NXYZ+ NXYZ+ NXYZ+ NXYZ+ NXYZ+ NXYZ+ NXYZ+ NXYZ. The truth table #2 for the signal appearing on lead 45 is given in the table appearing at the end of the specification when four input signals are fed to the feed back mixers. If only two leads are connected between shift register 11 and feed back mixer 36 so that two input signals, N and X, are supplied thereto, the Boolean function of the signal appearing on lead 45 is NX+ NX. Truth table #3 for two input signals applied to feed back mixer 36 appears at the end of the specification. The actual construction of each feed back mixer 36-39 is identical and it is deemed necessary to describe only one of these circuits. Feed back mixer 36 comprises six magnetic cores 47, 49, 56, 57, 58 and 59 of the type previously described. In the particular disclosed embodiment, plugboard terminals 41, 42 and 43 are respectively connected to the output windings of magnetic cores 12, 15 and 17 of shift register 11. It is to be understood, however, that terminals 41, 42 and 43 may be connected to any of the stages in shift register 11 and that the particular arrangement shown is for purposes of illustration only. The signal appearing at terminal 41 is simultaneously applied to the input winding 46 of core 47 and to the inhibit winding 48 of core 49. Similarly, the signal appearing at terminal 42 is simultaneously applied to inhibit winding 51 of core 47 and to input winding 52 or core 49. The output windings 53 and 54 of cores 47 and 49, respectively, are coupled to terminal 55 by means of isolating rectifiers connected to each of the output windings. The connection of windings 53 and 54 to terminal 55 serves as an "or" gate. For purposes of explanation, a pair of examples will be given to illustrate the manner in which the logical elements employed in this circuit function. It will be assumed that core 12 is storing a "one" and that core 15 is storing a "zero" at the time a timing pulse is produced by amplifier 245. At such a time, a positive pulse is supplied to inut winding 46 of core 47 by means of terminal 41 while no pulse is applied to inhibit winding 51 from terminal 42. The application of these pulses to core 47 causes it to switch to a positive state of magnetization and (at the next timing pulse) produce a positive voltage at output winding 53 that is supplied to terminal 55. In core 49, the application of a positive pulse to winding 48 inhibits the core from changing its state and no pulse is subsequently produced at its output winding 54. Thus, if core 12 is storing a "one" and core 15 is storing a "zero", a "one" output will appear at terminal 55 when the next timing pulse is generated and a "one" will also be produced if the state of cores 12 and 15 are reversed due to the symmetry of the logical circuitry associated with cores 47 and 49. If both cores 12 and 15 are "the .cent.zero" state when a timing pulse is applied thereto a "zero" will appear at terminal 55. This may be explained as follows: when timing pulses are applied to cores 12 and 15 no output signals will be derived therefrom and cores 47 and 49 will remain at rest. If both cores 12 and 15 have "ones" stored therein at the time a timing pulse is applied thereto, a "zero" will also be fed to terminal 55 because these pulses will inhibit the loading of both cores 47 and 49 preventing any positive output signals to be generated thereby. The circuit comprising cores 47 and 49 is commonly referred to as a binary half adder. The output signal from the stage associated with core 17 of shift register 11 is simultaneously applied to the input winding of core 56 and the inhibit winding of core 57. The input winding of core 57 and the inhibit winding of core 56 are simultaneously supplied with pulses indicative of the state of the last stage 20 of shift register 11 by lead 44. The output windings of half adder cores 56 and 57 are combined together to form an "or" circuit at terminal 61. Half adder cores 58 and 59 have applied thereto the combined signals from the other cores 47, 49, 56 and 57 of feed back mixer circuit 36. The signal appearing at terminal 55 indicative of the Boolean function XY+ XY is applied to the input winding of core 58 and the inhibit winding of core 59. In a similar fashion the signal appearing at terminal 62 indicative of the Boolean function NZ+ NZ is supplied to the inhibit winding of core 58 and the input winding of core 59. The output winding of core 59 is coupled through an isolating rectifier and lead 45 to the first core 12 associated with shift register 11. In this manner four output signals from shift register 11 are combined in feed back mixer 36 to provide a single input for the stage of the shift register associated with core 12. Recirculation of the information contained in shift register 11 is thus established providing a feed back shift register that enables the repetition or recurrence rate of the signals stored in shift register 11 to be 2.sup.N -1 bits, where N is the total number of stages employed in the shift register. In this particular shift register, having nine cores, there are actually 11 stages because feed back mixer 36 inserts a two bit delay in the signals applied thereto. Thus, for the first two timing pulses generated by amplifier 245 no input signal is fed to the input winding of core 12 from feedback mixer 36 because of the inherent delay associated with the cores in transferring information into and out of them, unless the cores of mixer 36 are also initially loaded through selector switches (not shown) in a manner similar to that disclosed in connection with register 11. The feed back mixer circuitry associated with each of the other shift registers 27, 28 and 29 is identical to that employed for shift register 11. However, it may be desirable to utilize only two input signals to some of these feed back mixers rather than all four, depending on the desired capacity of the machine. Shift registers 27, 28 and 29, respectively, contain 11, 15 and 17 magnetic cores therein and may be considered as 13, 17 and 19 state shift registers, respectively, because of the feed back mixers associated therewith. Output signals from the last stage of each shift register 11, 27, 28 and 29 are combined in another logical Boolean algebra circuit, output mixer 65 containing cores 66, 67, 68, 69 and 72. Output signals from the penultimate stages of shift registers 11 and 28, e.g. core 19 of register 11, are respectively connected to the inhibit windings of cores 66 and 67. Core 70, commonly referred to as a "ones generator" supplies the input windings of cores 66 and 67 with power pulses each time a timing pulse is produced by amplifier 245. In this manner, both cores 66 and 67 serve as inverting circuits for the next to the last stages of shift registers 11 and 28, respectively. Thus, if a "zero" is stored in core 19 at the time a timing pulse is produced core 66 will not inhibit the passage of a pulse from "ones generator" 70 through core 66. If, however, a "one" is stored in core 19, a "zero" will be produced at the output winding of core 66 because the signal applied to its inhibit winding blocks its loading and the generation of a subsequent output signal. Core 67 similarly responds to the next to the last stage of shift register 28. The inhibit winding of core 68 is supplied with the output signal of core 66 while the input winding of core 68 is fed with a signal indicative of the state of the last stage of shift register 27. In this manner, a signal is obtained at the output winding of core 68 indicative of the Boolean function AB; where A is the state of the last stage 20 of shift register 11 and B is the state of the last stage of shift register 27 at the time as when signal A is produced. It should thus be apparent that the signal from the next to the last stage of shift register 11 is supplied to core 66 rather than that from the last stage because of the inherent one bit delay produced by the core. Stated differently, when core 68 is receiving a signal on its inhibit and input windings these signals are indicative of the state of the last stages of both shift registers 11 and 27 at the same time. In a similar manner, cores 67 and 69 are respectively supplied with input signals from the penultimate stage of shift register 28 and the last stage of shift register 29; the inhibit winding of core 69 being supplied with the output signal from core 67 and the input winding of core 69 being coupled to the last stage of shift register 29. Thus, the signal supplied to terminal 71 from output winding 69 is indicative of the Boolean function CD where C and D are the signals stored in the last stage of shift registers 28 and 29 at the same time. Core 72 serves as a complimentary generator and produces an output pulse having "one" polarity that is coupled to output terminal 73 only when the last stage of each shift register 11, 27, 28 and 29 is in a "zero" state. This is accomplished by connecting the input winding of core 72 to the output winding of core 70 and by connecting the inhibit winding of core 72 to the last stage of each shift register by means of isolating diodes. Thus, if the last stage of any of the shift registers is in the "one" state, a pulse will be supplied to the inhibit winding and no output will be fed to terminal 73 from core 72. In Boolean terms, core 72 produces an output signal in accordance with the function A+B+C+D, where A, B, C and D are as previously defined. It is thus seen that output mixer 65 produces a Boolean Boolean at terminal 73 that will assumes a "one" state when all of the input signals applied thereto are either similar, i.e. all or none are zeros, or will produce a "one" output signal when certain pairs of the input signals applied to the mixer circuit are in the "one" state. The signal at terminal 73 will be in the "zero" state, in response to one half of the combinations of signals fed thereto and it will be in the opposite "one" state in response to the other half of the combinations of signals fed to it. Specifically, the output signal at terminal 73 will be in accordance with the Boolan function AB+CD+A+B+C+D. The truth table #4 for this function appears at the end of the specification. The signal at terminal 73 will not repeat its cycle for 10.sup.18 bits generated by amplifier 245 and will have zero information biasing for the complete cycle. In utilizing a keying rate of approximately 100 words per minute no recurrence of signals produced at terminal 73 should occur for 10.sup.9 years, i.e. one thousand million years. FIG. 6 is a schematic diagram of the comparator 117 or 127, which is a safety device that can be applied to this or other forms of binary scramblers. Cores 441 and 442 are delay stages for the clear text input signal to synchronize the clear and cipher text signals applied to the half-adder mixer circuit comprising cores 443 and 444. The clear text signal is applied to the input and inhibit windings of cores 443 and 444, respectively from terminal 824 via lead 137 or 138 and cores 441 and 442. The line or cipher text signal from mixer 116 or 126 is coupled via lead 139 or 140 to variable register 448, the inhibit winding of core 443 and the input winding of core 444. Variable resistor 448 permits balancing the two currents so that half-adder containing core 443 and 444 will function reliably. The current read-out terminals of these cores are coupled through isolating diodes to the inhibit winding of complement generator core 446 and the input winding of delay core 447. The series connected timing windings of cores 441-447 are supplied with timing pulses from timing pulse terminal 399, to provide energization of the buffer and mixer cores. Core 445 is a conventional "ones" generator and supplies current to the input winding of core 446 through an isolating diode upon each occurrence of a timing pulse. The current read-out terminals of cores 446 and 447 are grounded through external resistors to give proper impedance to the "current" circuits. Core 446, having its inhibit winding connected to the half adder output terminal inverts the half adder output signal and core 447 having its input winding in series with the inhibit winding of core 446 inserts the same delay introduced by core 446. Thus, the output voltages of cores 446 and 447 occur simultaneously and are complementary. The output signal of core 446 is supplied simultaneously to the shift windings of the cores in quatinary counter 410 through amplifier 417. Successive pulses from core 446 indicative of successive similarities between the pulses at terminals 497 and 498, shifts the signal stored in the cores of counter 410 from one core to another. After four successive similarities in the signals at terminals 498 and 497, an output pulse is generated by core 414. This output pulse reloads core 411, since it is fed back to its input winding, and shifts the signal stored in counter 420 from one stage to the next. Similarly, when four successive pulses are supplied to amplifier 427, due to sixteen successive similarities at terminals 497 and 498, an output pulse is obtained from core 424. This pulse is supplied back to the input winding of core 421 and to the drive windings of the cores in quatinary counter 430 through amplifier 437. Four consecutive output pulses from core 424, i.e. 64 successive similarities at terminals 497 and 498 causes an output pulse to be generated by core 434 of counter 430. This pulse is supplied back to the input winding of core 431, thereby reloading the core, and to the S input terminal of flip-flop 470. Flip-flop 470 is accordingly switched to actuate visual and aural alarms 480 and to turn-on keyer 118 or 128. Thereby a steady marking signal is supplied to the transmit channel 4 or to the receive terminal equipment 3. Malfunction is highly improbable because the chances of sixty four consecutive "zeros" from the key generator is extremely remote (1 in 10.sup.13 words). Every time that the signals at terminals 497 and 498 are different, prior to the occurrence of sixty three consecutive similarities thereof, a trigger pulse is supplied from the voltage output terminal of core 447 to one-shots 450 and 460. "Clear" one-shot 450 generates a 20 microsecond output pulse which is coupled to the driving circuits of the 3 quarternary counters 410, 420, and 430, thus clearing the cores of their previous loads. "Load" one-shot 460 is coupled to the inhibit windings of cores 411, 421 and 431 in series fashion but in reverse polarity; its 40 microsecond output pulse persists beyond the clearing pulse and thus reloads the first stage of each of the 3 quarternary counters 410, 420 and 430. Initial erasing and loading of the cores is accomplished by the connection of clear terminal 24, FIG. 4, through terminal 464 to the drive windings of the cores in counters 410, 420 and 430 and the connection from load terminal 26 to the inhibit windings of cores 411, 421, and 431. The pulses from terminals 464 and 466 actuate the cores in substantially the same manner as those produced by one-shots 450 and 460. With this comparator, there is a possibility of false alarm because sixty three similar consecutive pulses at terminals 498 and 497 results in core 434 being loaded. If there is a difference between the next two pulses, and output pulse is obtained from core 434 because of the signal applied to the drive winding thereof from pulse shaper 450. The possibility of this occurring is extremely remote, 1 in 2.sup.48 bauds or 1 in 10.sup.13 words. The comparator is preferably constructed in the form of a plug-in module or modules. Normally 1 comparator per scrambler should be supplied, and it should be inserted in the Transmit Chassis 110. For twin-transmit operation of the scrambler two comparators should be supplied, but the extra comparator can be taken from the associated twin-receive scrambler at the other end of the circuit. In case of need a transmit chassis can operate without the comparator, as a calculated risk, and still present no more hazard of transmitting inadvertent clear text than is found in presently available cryptographic equipments. FIG. 8 is a schematic diagram of the ciphering mixer 116 or 126, which comprises a 6-core magnetic unit 810, two transistor emitter-followers 817 and 818 and a transistor flip-flop 820. The mixer combines the key generator signal with the unciphered signal of the local transmitter in a binary half adder to produce the ciphered mark and space transmitted signals or it combines the received cipher signal with the key generator signal to produce the unciphered mark and space signals fed to the local receiving system. The former function is accomplished by mixer 116 and the latter by mixer 126. The mixer intelligence input signal on lead 133 or 134 is supplied via terminal 822 and current limiting resistor 809 to the input winding of sampling 801 which supplies current pulses of the correct shape and synchronism to the input winding of core 802 and inhibit winding of core 803. The intelligence signal output voltage of core 801 is also applied through emitter follower 817 to comparator 117 or 127 via terminal 824; emitter follower stage 817 being employed to prevent loading of the output winding of core 801 by the comparator. The sampling-gate 801 is a conventional 4-winding, one-core-per-bit magnetic shift-register unit identical with other 4-winding cores employed in this equipment. The inhibit winding of core 801 is permanently biased to negative magnetic saturation from the positive regulated voltage bus, with the inhibiting current limited and controlled by variable resistor 812. Resistor 812 is adjusted so the core 801 will switch slowly from positive to negative saturation and slowly back to positive saturation again, following the "loop" or "line" signals at terminal 822, without generating appreciable voltage in its output winding. The "shift" or "drive" winding of core 801 is connected in a series-string with the drive windings of cores 802, 803, 804, 805 and 806, and all cores are driven from a single driving-amplifier 811, drive current being limited by resistor 819. Timing pulses are fed to the drive windings through terminal 821 from timing unit 112 or 122 at the middle of each baud or bit of the input signal at terminal 822. The driving pulses sense and read-out the signals stored in sampling gate 801 so sharp pulses indicative of core state are obtained when they are applied. The current output terminal of sampling gate 801 is coupled to the input winding of core 802 and inhibit winding of core 803 which comprise the binary half-adder that combines the intelligence and key generator signals. The voltage output terminal of sampling gate 801 is coupled to comparator input terminal 497 via emitter-follower 819 and terminal 824, thereby supplying the clear-text signal input to the comparator 117 or 127. The key generator signal is applied to the series connected inhibit and input windings of cores 802 and 803 respectively, while the output intelligence current signal from core 801 is applied to the series connected input and inhibit windings of cores 802 and 803, respectively. The current readouts from cores 802 and 803 are fed through blocking diodes 807 and 808. respectively, combined to generate the mixer half adder output signal and supplied to the series connected inhibit and input windings of inverting core 805 and delay core 806, respectively. The input winding of inverting core 805 is supplied with a current pulse by ones generator 804 upon the occurrence of each timing pulse. Since the half adder output current is applied to the inhibit winding and the ones generator output current is applied to the input winding of core 805, the voltage output of core 805 is the complement of the mixer output signal. The output voltages of cores 805 and 806 are applied to the reset and set terminals, respectively, of flip-flop 820, core 806 being employed to provide synchronization for the out of phase signals applied to the flip-flop. Resistors 815 and 816 connected in the output circuits of cores 804 and 805, respectively, are employed to provide proper loading of the core output current. The transistor flip-flop 820 is of conventional set/reset design. Terminals "A" and "B" are the output terminals, one of which is ON (conducting) and the other OFF (cut-off or non-conducting), but the "A" terminal is the only output terminal that is used. Terminals "R" and "S" are the input terminals, one of which is energized by a positive pulse when required. An input pulse to the "R" terminal causes the "A" output terminal to be cut-off and the "B" output terminal to conduct while the converse is true for an input pulse to the "S" terminal. The flip-flops are designed to respond to positive control pulses only, but if desired the elements may be responsive to negative pulses, in which case other pulse polarities must be reversed for compatibility and proper operation. As previously explained, the "S" input terminal is coupled to the voltage output terminal of delay core 806, producing a voltage and current at output terminal 825 when a "ONE" has been read out of core 806. The "R" input terminal is coupled to the voltage output terminal of complement generator 805, producing no voltage and no-current at output terminal 825 when a "ONE" has been read out of core 805. The mark and space rectangular pulses generated by flip-flop 820 normally supply just enough current to control the electronickeyer 118 or 119. Clock (102) FIG. 7 is a block diagram of the clock 102 of FIG. 2. The clock is divided into 5 functional parts, preferably in the form of plug-in modules, as follows:
______________________________________
Basic frequency converter 701
NTDS frequency converter 702
SAGE/Rixon frequency converter
703
Pulse shaping network connected
704
to timing and phasing unit 112
in transmitter chassis 110,
Pulse shaping network connected
705
to timing and phasing unit 122
in receiver chassis 120.
______________________________________
The normal functions of the scrambler can be performed without using the 702 and 703 modules and the description will be given accordingly. A 1 megacycle sine wave is received from stable oscillator 101 through lead 130 (FIG. 2) and input terminal 706, and is coupled via patch cord 707 and jack 708 to a decade boot-strap frequency divider consisting of divide-by-10 stage 710, multiply-by-3 stage 711 and multiply-by-3 stage 712. Sine wave outputs of 100 kc, 300 kc and 900 kc are generated by the respective stages. The 300 kc output from stage 711 is coupled to a second decade boot-strap consisting of divide-by-10 stage 713 and multiply-b-9 stage 714, which generate sine wave outputs of 30 kc and 270 kc respectively. The 270 kc and 30 kc outputs are coupled to a heterodyne mixer 715 which generates the difference-frequency of 240 kc. This output frequency is coupled to a quintile boot-strap consisting of a divide-by-5 stage 716 and a multiply-by-4 stage 717, which generate output frequencies of 48 kc and 192 kc respectively. The 48 kc output is connected to terminal 733, which is preferably a double-jack. The 48 kc clock-rate is the basis of the timing pulses for Department of Defense Digital Data Systems (4800, 2400, 1200 and 600 bits/second) and for 1000 bauds per second facsimile. The 270 kc output from stage 714 is also coupled to another boot-strap consisting of divide-by-23 stage 718, multiply-by-4 stage 719, and multiply-by-6 stage 720. The 46-22/23 kc output from stage 719 is connected to double-jack 731 and is the timing basis for 100 wpm operation of Teletype multiplex equipments. The 270 kc output from stage 714 is also connected to jack 721 and may be coupled (as shown) via patch cord 724 to a quintile boot-strap consisting of divide-by-5 stage 725 and multiply-by-4 stage 726. With 270 kc input, the output frequency from stage 725 is 54 kc. The output of stage 725 is connected to double-jack 732 nd is thence coupled via patch cords 736 and 737 to the two conventional pulse shaping networks 704 and 705 which generate clock pulses of required shape, amplitude and duration, at exactly the same rate as the sine wave timing signal applied thereto. Clock pulses generated within network 704 are conducted via output terminal 738 and lead 131 (FIG. 2) to transmit timing and phasing unit 112. In like manner 705 clock pulses are conducted via terminal 739 and lead 132 (FIG. 2) to receive unit 122. The 54 kc clock pulses are the timing basis for 60 wpm and 75 wpm operation of Teletype multiplexes, and may be used for other purposes. Output clock pulses to the 112 and 122 units are normally at the same rate, but do not have to be if it is desired to transmit and receive signals of different frequencies simultaneously. For use with the Navy Tactical Data System, the NTDS module 702 (upper right hand portion of FIG. 7) must be added to the clock 102. 270 kc output from stage 714 and 100 kc output from stage 710 are combined in heterodyne mixer 740, and the output sum-frequency of 370 kc coupled to heterodyne mixers 741 and 750. The 900 kc output of stage 712 is also coupled to mixer 741 and the difference-frequency of 530 kc is coupled to vigintile boot-strap consisting of divide-by-20 stage 742, multiply-by-3 stage 743 and multiply-by-7 stage 744. The 556.5 kc output from stage 744 is coupled to a quintile boot-strap consisting of divide-by-5 stage 745 and multiply-by-4 stage 746. The 445.2 kc output from stage 746 is coupled to a decade boot-strap consisting of divide-by-10 stage 747 and multiply-by-9 stage 748. The 44.52 kc output from stage 747 is connected to jack 735, and is the timing basis for the 2226 bps which is one of the two simultaneous bit rates required by the NTDS. For NTDS operation, network 705 is unplugged from terminal 732 and patched to terminal 735, but network 704 is connected to terminal 732 and the scrambler operated in twin-transmit or twin-receive mode. The 30 kc output from stage 713 is coupled to heterodyne mixer 750 to which the 370 kc output of mixer 740 is also coupled. The difference-frequency of 340 kc is coupled to a quintile boot-strap consisting of divide-by-5 stage 751 and multiply-by-4 stage 752. The 272 kc output from stage 752 is connected to jack 722 and thence coupled via patch cord 724 to the quintile boot-strap 725/726 previously described. The 272 kc input is reduced to a 54.4 kc output (from stage 725) which is coupled to network 704 via patch cord 736. This 54.4 kc is the timing basis for 1360 bps, which is the other of the two simultaneous bit rates required by the NTDS. For use with either the SAGE system or Rixon multiplex equipments, the SAGE/Rixon module, 703 (lower right hand portion of FIG. 7) must be added to the clock 102, and the NTDS module 702 may be removed. The 1 mc stable input signal is directly coupled from the input terminal 705 to a heterodyne mixer 760 and to a duodecimal boot-strap consisting of divide-by-12 stage 761 nd multiply-by-11 stage 762. The 916-2/3 kc output from stage 762 is coupled to a decade boot-strap consisting of a divide-by-10 stage 765, multiply-by-3 stage 766 and multiply-by-3 stage 767. The 275 kc output from stage 766 is connected to jack 723 and is thence coupled via patch cord 724 to the previously described decade boot-strap 725/726. The output clock rate of 275/5 or 55 kc is the timing basis for the 1100 bps required by SAGE. The 192 kc output from stage 717 is coupled to a frequency-doubler 769 whose output is coupled to a heterodyne mixer 770. The 240 kc output from stage 715 is also coupled to heterodyne mixer 770. The output sum-frequency of 624 kc from mixer 770 is connected to a duodecimal boot-strap 771/722. The output frequency of 624/12 or 52 kc from stage 771 is connected to jack 734 and thence coupled, via patch cord 336 or 337, to network 704 or 705. This 52 kc clock rate is the timing basis for the 1300 bps required by SAGE. The 750 bps bit rate required by SAGE can be derived from the 54 kc clock rate and is the same bit rate that is required for 16-channel Teletype multiplex operating at 75 wpm. It can also be derived from the previously mentioned 48 kc clock rate. For the Rixon multiplex, the 83-1/3 kc output from stage 761 is coupled to an octal boot-strap 763/764. The 10-5/12 kc output from stage 763 is coupled to the previously mentioned heterodyne mixer 760 to which the 1 mc input signal frequency is coupled. A sharply tuned high-pass or band-pass filter accepts the sum-frequency of 97/96 mc or 1.010,416-2/3 mc and rejects the 1 mc "carrier" and the difference-frequency of 95/96 mc. The output of mixer 760 is connected to jack 709 and thence after suitable replugging of patch cord 707, to decade boot-strap 710/711/712. From here on the operation is exactly as described for the basic module 701, except all the frequencies are raised by exactly 1 part in 96. The 45-22/23 kc output at jack 731 becomes 47-41/92 kc and the 54 kc output at jack 732 becomes 54-9/16 kc. To summarize, the clock 102 described herein generates clock pulses at the following 9 required rates:
Table 6
______________________________________
Clock-Rate
System Remarks
______________________________________
44.52 KC NTDS 2226 bps (bauds per
sec.)
46-22/23 KC
Teletype multiplex
100 wpm
47-41/92 KC
Rixon multiplex 100 wpm
48 KC Dept. of Defense
600, 1200, 2400, 4800
Digital Data System
1000 bps.
SAGE and Facsimile
750 bps.
52 KC SAGE 1300 bps
54 KC Teletype multiplex
60 and 75 wpm
54.4 KC NTDS 1360 bps
54-9/16 KC
Rixon multiplex 60 and 75 wpm
55 KC SAGE 1100 bps
______________________________________
It is possible, of course, by the components and patch cords herein provided, to generate other clock-rates that are not presently required nor desired, but which may be utilized in the future. It is also possible by means of the techniques disclosed herein to add other components which will generate new clock-rates, not presently required, from a standard 1 mc stable oscillator. To be compatible with the automatic phase-correcting unit 300 disclosed in connection with FIG. 3, the average clock-rate is about 10.times.4800 bits/second or about 50 kc and the range of clock-rates should not exceed about .+-.10%. These requirements have been met in this invention. The oscillator 101 that actuates clock 102 is a standard off-the-shelf 1 megacycle stable oscillator, preferably fully-transistorized in the interests of compactness and compatibility with the other components of the scrambler. One megacycle is selected since it corresponds with the frequency standard by the National Bureau of Standards so that calibration is easily performed. Oscillator 101 should be of 10.sup.-6 stability in order not to degrade the over all stability of the systems with which used. Because the transmitting scrambler "tracks" the transmitting MUX, no useful purpose is served by having stability of the scrambler oscillator better than the multiplexer oscillator. When the synchronous circuit is subjected to severe jamming or bad multipath "jitter" it is often desirable to disable the receiving phase-corrector 300 and "ride" on the receiving oscillator. In such cases the stability of the receiving scrambler oscillator should be equal to the stability of the transmitting MUX oscillator. In the case of systems like the Rixon multiplexer which have oscillators one or two magnitudes of stability better than the oscillator built into the scrambler, it may be desirable to use a 1 mc externl oscillator of superior stability. FIG. 9 is a schematic diagram of the starting unit 103 of FIG. 2. In order to follow the operation of the starting unit the rest of the system must be understood: hence its deferment until the last. The starting unit comprises sync pattern generator containing cores 901 and 902, start pattern generator containing cores 903-906, start signal sensing unit including cores 911-916 and control switches 931-939 or 930. The 12 cores 901-906 and 911-916 are driven as 2 parallel strings of 6 cores each by the timing pulses applied to terminal 941 from timing and phasing unit 112. The drivers 909 and 919 for the core timing windings are coupled to the pole of 3-position switch 939. For transmitting, the XMT contact of switch 939 is connected via terminal 941 and lead 135 to the timing output terminal 399 of the timing and phasing unit 112 in the transmit chassis 110. During operation of the apparatus, after starting and synchronizing is accomplished, switch 939 is set at the center or off position to cut-out starting unit 103. Terminal 941 is also connected to switch 937 and thence via terminal 943 and lead 135 to supply the clear text input signal to the XMT ciphering mixer 116 and comparator 117. At starting only, switch 937 is opened thus disabling comparator 117 and all elements of the ciphering mixer 116 except flip-flop 820. During the start process, flip-flop 820 is energized by the start pattern signals applied to it from cores 903 and 905 via terminals 923 and 924, and switches 931 and 932. The current start pattern signal generated by cores 903-906 is supplied from the output winding of core 906 to the input winding of start pattern signal sensor core 911 via armature 951 of switch 932. Terminals 925 and 926, responsive to the output signals of mixers 116 and 126, respectively, are connected to switches 934 and 935, are set to the grounded contacts during starting to effect mixer loading. Switch 936 is set to the XMT contact, so that the voltage output terminal of core 916 is coupled to the input terminal of the "transit" electronic switch 113 via terminal 927 and lead 151 to close the switch when the start signal is generated by cores 903-906 and sensed by cores 911-916. After the Receiving Station reports ready or is presumed ready by passage of sufficient time interval, power is turned on the equipment and three-pole, three-position switch 932 is moved from its center or off position where the armatures alight on terminals 952, 953 and 954 to the "Sync" contacts where the armatures alight on terminals 954, 955 and 956, thus coupling the input R and S terminals of flip-flop 820 to the voltage readout terminals of magnetic flip-flop cores 901 and 902 respectively, and grounding the current readout terminal of core 906 to prevent saturation. The output winding of core 901 is coupled to the input winding of core 902 and the output winding of core 902 is coupled back to the input winding of core 901, thus switching a preloaded "ONE" from one core to the other. The effect is to transmit a Space-Mark-Space-Mark-Space-Mark-pattern through the transmit channel 4 in response to timing signals from timing and phasing unit 112. For receiving, the armature of 3-position switch 939 is set to the RCV contact, coupling the timing circuit of the starting unit 103 to the output (timing) terminal 399 of the timing and phasing unit 122 in the receive chassis 120, via terminal 942 and lead 136. Terminal 942 is also connected to switch 938, left in its closed condition to couple the timing pulses to the RCV ciphering mixer 126. Three-pole three position switch 932 is set to its center or off position, where the armatures engage terminals 952, 953 and 954 thus de-coupling the voltage outputs of cores 901, 902, 903 and 905 from the flip-flops 820 in the ciphering mixers 116 and 126. Three-position switch 933 is set to its RCV contact; switch 934 is set to its grounded contact; switch 935 is set to its RCV contact; the foregoing couples the input winding of core 911, via terminal 926 and lead 144 to the current output terminal of core 806 of the receive ciphering mixer 126 so the remotely generated start pattern signal is applied to the local start sensing unit containing cores 911-916. Switch 936 is set to the RCV contact, coupling the voltage output terminal of core 916 indicative of reception of the start pattern signal via terminal 928 and lead 152, to the XMT electronic switch 123 of the receive chassis 120; switch 123 being activated to supply key generator 124 with timing pulses. Operation of the transmitter and receiver is initiated by turning power on, resetting electronic switches 113 and 123 so key generators 114 and 124 are not supplied with timing pulses from timing and phasing units 112 and 122, opening manual switches 115 and 125 to prevent actuation of mixers 116 and 126 by key generators 114 and 124 so the transmitted and received signals pass through the mixers unaltered, setting up, clearing and loading of key generators 114 and 124 by switch 23, thus establishing the transmitting and receiving terminals ready for automatic synchronization and starting. When the transmitting operator receives a go ahead signal over the other duplex channel, or is otherwise satisfied that the receiving unit is in proper synchronism, he actuates switch 932 so the armatures engage the start contacts 957, 958 and 959, thereby coupling core 903 voltage output via terminal 923 to the R input terminal of transmit flip-flop 820, core 905 voltage output via terminal 924 to the S input terminal of transmit flip-flop 820, and core 906 current output to the XMT contact of switch 933 and thence to the input winding of core 911. Cores 903, 904 and 905 are connected as a 3-stage ring or recirculating-loop commutator, with core 906 operating simultaneously with 905 as a buffer stage. The preloaded "ONE" in core 903 is shifted to 904 with the first timing pulse, then is shifted to cores 905 and 906 with the second timing pulse, and back to core 903 with the third timing pulse, with operation repeated in response to additional timing pulses applied to cores 903-906. The successive current read-outs from core 906 in response to the timing signal into core 911 represent -ZERO-ZERO-ONE-ZERO-ZERO-ONE and repeat or SPACE-SPACE-MARK-SPACE-SPACE-MARK etc. The voltage read-outs from cores 903 and 905 into flip-flop 820, and the corresponding signals transmitted over the transmit channel 4 to the receiving scrambler represent -SPACE-SPACE-MARK-SPACE-SPACE-MARK, and repeat. In the associated receiving unit 120, the above start-signal pattern is received, integrated and sampled in the receiving mixer 126, and passes through the mixer into the input winding of core 911 of the start-signal sensing unit 911-916 (inclusive) unaltered in polarity (because the key generator is disconnected by manual switch 125) but delayed by 2 binary digits to compensate for the 2 binary-digit delay of the subsequent enciphered signals within the transmitting mixer 116. There is no delay in the transmitting unit, the start signal pattern going directly from the current read out terminal of core 906 via switch 933 to the input winding of core 911. The start-signal sensing unit (cores 911-916) is so connected that a voltage pulse is read out of core 916 (and into the electronic switch 113 or 123 to which it is coupled) only when it senses the 5-bit signal ZERO-ZERO-ONE-ZERO-ZERO or SPACE-SPACE-MARK-SPACE-SPACE. In this way, the synchronizing signal (MARK-SPACE-MARK-SPACE-MARK-SPACE) cannot be mistaken for the start signal unless there are garbles in 2 or 3 of five consecutive bits of the signal. The current output circuits of cores 911, 912, 914 and 915, after passing through the input winding of the following stage or a compensating resistor are coupled, via isolating diodes, to the inhibit winding of core 916. The current output circuit of core 913, is supplied in series to the input winding of core 914, a compensating diode and to the input winding of core 916. A ONE (or MARK) in the 1st, 2nd, 4th, or 5th bits of the input signal will inhibit the loading of core 916. A ZERO (or SPACE) in the 3rd bit of the input signal will give a ZERO read out from core 913 and therefore fail to load core 916. Of the 32 possible combinations of a 5-bit binary signal only one (SPACE-SPACE-MARK-SPACE-SPACE), the prescribed start-signal, will be accepted by the start signal sensing unit 911-916 and thus trigger the associated electronic switch 113 or 123. For operational simplicity and "fool-proofness" the 9 control switches 931-939 are incorporated in a single multi-position, multi-pole, rotary selector switch (930), but the elements are more easily described and clearly illustrated as separate components. By appropriate switch settings the (normal) transmit chassis 110 can be used for receiving the synchronizing and starting signals, and the (normal) receive chassis 120 can be used for transmitting them, thus providing for the twin-receive and twin-transmit modes of operation. The transmit key-generator 114 is started at the very first "appearance" of the start signal, but the manual switch 115 is still open and the unenciphered start pattern is repeated so long as switch 932 is on the start contact. The receive key-generator 124 is normally started at the very first transmission of the start signal, but due to poor circuit conditions may not be sensed until the 2nd or possibly 3rd or 4th repetition. In case of delayed start, the manual corrector system described under FIG. 3, must be used. After momentarily resting on start contact, switch 932 is set to its "OFF" position, thereby decoupling both the sync pattern generator 901-902 and the start pattern generator 903-906. Switch 939 is also set to its OFF position, thereby disabling the start sensing unit as well as the two pattern generators. The manual switches 115 and 125 are now closed, thereby supplying the key signal of generators 114 and 124 to mixers 116 and 126, respectively. The remote and local system are now operating in synchronism and correct phase. The associated transmit and receive multiplexes (or other communications terminal equipments) can be connected and the system as a whole is in operation. TRUTH TABLES
Table 2
______________________________________
4-Tap Feed-back Mixer
N X Y Z Out N X Y Z Out
______________________________________
0 0 0 0 0 1 0 0 0 1
0 0 0 1 1 1 0 0 1 0
0 0 1 0 1 1 0 1 0 0
0 0 1 1 0 1 0 1 1 1
0 1 0 0 1 1 1 0 0 0
0 1 0 1 0 1 1 0 1 1
0 1 1 0 0 1 1 1 0 1
0 1 1 1 1 1 1 1 1 0
______________________________________
It should now be apparent that there has been herein disclosed a synchronous, universal, binary cryptographic system which may operate in conjunction with all presently available and projected military synchronous binary communications systems at all currently agreed-upon bit rates. Portability is achieved by use of magnetic core circuitry which results in light weight and rugged construction. While I have described and illustrated one specific embodiment of my invention, it will be clear that variations of the details of construction which are specifically illustrated and described may be resorted to without departing from the true spirit and scope of the invention as defined in the appended claims.
|
Same subclass Same class Consider this | ||||||||||