Including digital audio

Multilocation video conference terminal including video switching contention control

4531024

Abstract

In a multilocation video conference system, contention for the video to be transmitted to the locations is resolved by employing so-called talker and graphics contention resolution processes. Both the talker and graphics contention processes may be overridden by manual selection of the video to be viewed at each location. In the talker contention process, the video to be transmitted is not switched until one and only one talker location is detected during a predetermined talker timing interval. In the graphics contention process, all requests for graphics transmission are rejected until one and only one graphics transmission request is detected during a predetermined graphics request timing interval. Once transmission of graphics has been assigned to a location, all other locations in the conference are transmitted the graphics video information until the location displaying graphics releases from the graphics transmission mode or there is a manual override. The location transmitting graphics information is transmitted the video from the last of the other locations selected for talker video transmission.


Claims

What is claimed is:

1. An apparatus for transmitting video signals to a plurality of remote locations, wherein each of the remote locations is or includes at least one conference location and each conference location generates a graphics transmission request message signal when a graphics video signal transmission is desired from the conference location,

means for resolving contention among the remote locations for the video signal to be transmitted from a conference location to other locations including

means for determining one conference location of said plurality of remote locations generating a graphics request message signal with an absence of graphics request message signals from all the other locations during a predetermined graphics timing interval; and

means for transmitting the video signal from said determined one conference location to all the other remote locations.

2. Apparatus as defined in claim 1 wherein said means for resolving contention further includes means for providing each conference location requesting graphics transmission an indication of whether its request is granted or denied.

3. In apparatus for transmitting video signals to a plurality of remote locations, wherein each of the remote locations is or includes at least one conference location and each conference location generates a graphics transmission request message signal when graphics transmission is desired and a talker message signal when a talker is detected at the conference location,

means for selecting one conference location of said plurality of remote locations having a talker with an absence of talkers at the other locations during a predetermined talker timing interval,

means for selecting one conference location of said plurality of remote locations generating a graphics request message signal with an absence of graphics request message signals from all the other locations during a predetermined graphics timing interval, and

means for selecting a video signal from said plurality of remote locations to be transmitted to said remote locations according to a prescribed priority including if a conference location requesting graphics transmission has been selected, a video signal from said selected graphics conference location is transmitted to all locations except said selected graphics conference location and a last previous selected talker conference location video signal other than that from said selected graphics conference location is transmitted to said selected graphics conference location, and if a graphics conference location has not been selected, a video signal from said selected talker conference location is transmitted to all of said remote locations except said selected talker conference location and said last previous selected talker video signal other than said selected talker video signal is transmitted to said selected talker conference location.

4. Apparatus as defined in claim 3 wherein said talker conference location selecting means includes means for inhibiting switching of the video signal being transmitted from said selected talker conference location until another talker conference location generating a talker message signal with an absence of talker message signals from all other locations during a current or subsequent one of said predetermined talker timing intervals is detected.

5. Apparatus as defined in claim 4 wherein said talker timing interval is at least 400 milliseconds.

6. Apparatus as defined in claim 3 wherein said graphics location selecting means includes means for providing each location requesting graphics transmission an indication of whether its graphics transmission request has been granted or denied.

7. Apparatus as defined in claim 6 wherein said graphics conference location selecting means further includes means for denying all requests for graphics transmission until a graphics transmission request message signal from a location is detected with the absence of graphics request message signals from all other locations during said predetermined graphics request timing interval.

8. Apparatus as defined in claim 7 wherein said graphics transmission request timing interval is at least 400 milliseconds.

9. In apparatus for transmitting video signals to a plurality of remote locations, wherein each of said remote locations is or includes at least one conference location and each conference location generates a talker status signal indicative of the talker state at the conference location, a graphics request signal indicative of the graphics transmission request state at the conference location and a video selection signal which can select the video signal from the other conference locations to be transmitted to the conference location,

means responsive to the talker status signals from the plurality of locations for selecting one of said conference locations having a talker with an absence of talkers from all other locations during a predetermined talker timing interval,

said talker conference location selecting means generating signals representative of a current selected talker conference location and at least a last previous selected talker conference location,

means responsive to the graphics request signals from the plurality of locations for selecting one of said conference locations generating a graphics request signal with an absence of graphics request signals from the other locations during a predetermined graphics request timing interval, and

means responsive to outputs from said talker selecting means, from said graphics selecting means and to video selection signals from said conference locations for selecting the video signal to be transmitted to each of said locations from the other locations according to a prescribed priority including, if a video selection signal is received from the conference location, the video signal from a conference location identified by the video selection signal is transmitted to that location, if no video selection signal is received and a conference location requesting graphics transmission has been selected, the video signal from said selected graphics conference location is transmitted to all locations except the said selected graphics conference location and the current selected talker conference location video signal if it is not that from said selected graphics conference location is transmitted to said selected graphics conference location, if the current selected talker conference location is the graphics conference location a last previous selected talker conference location video signal is transmitted to the selected graphics conference location, and if no video selection signal is received and a graphics conference location has not been selected, a video signal from said current selected talker conference location is transmitted to all the locations except said selected talker conference location and the last previous selected talker conference location video signal is transmitted to said selected talker conference location.

10. Apparatus as defined in claim 9 wherein said talker selecting means includes means for inhibiting the start of said talker timing interval until the talker conference location is selected.

11. Apparatus as defined in claim 9 wherein said talker selecting means includes means for starting said talker timing interval only when a conference location having a talker with an absence of talkers from all other locations is detected and means for stopping said talker timing interval when none or more than one conference location having a talker is detected.

12. Apparatus as defined in claim 11 wherein said talker timing interval is approximately 400 milliseconds.

13. Apparatus as defined in claim 11 wherein said graphics request timing interval is approximately 400 milliseconds.

14. Apparatus as defined in claim 11 wherein said remote locations include conference locations and can include other apparatus for transmitting video signals to a plurality of remote locations.

15. Apparatus as defined in claim 14 wherein said video signals are transmitted in digital form.


Description

RELATED APPLICATIONS

U.S. patent applications Ser. No. 545,761 (J. R. Colton et al), Ser. No. 545,461 (J. R. Colton et al), Ser. No. 545,363 (D. Scordo), Ser. No. 545,364 (D. Scordo), and Ser. No. 545,162 (D. Scordo) were filed concurrently herewith.

TECHNICAL FIELD

This invention relates to audio-visual conferencing systems and, more particularly, to a system for controllably connecting a plurality of conference locations together including video switching contention resolution.

BACKGROUND OF THE INVENTION

Heretofore, analog signals were used in multilocation conference arrangements to transmit both video and audio information. Consequently, when the video to be viewed is switched from one conference location to another the entire video picture was present and switched. In more recent conference arrangements, digital signals are employed to transmit the video information which do not usually contain complete picture information. Indeed, the digital signal usually includes only changes in the scene being viewed. Therefore, upon switching the digital signal, there is some disruption in the picture being viewed until the complete picture information is obtained.

None of these prior known arrangements resolve contention among multiple talkers at different conference locations or multiple requests for graphics transmission from different conference locations.

In one known arrangement, the video signal to be transmitted to conference locations is selected to be from a location having the first talker. While in another known arrangement the video is selected from the location having the loudest talker.

Problems arise in these prior arrangements when a number of conferees at different locations are concurrently talking. Indeed, the first talker or the loudest talker may not be the "right" or desired talker. This may lead to unnecessary switches in the video being transmitted before the "right" talker is selected. Such unnecessary switching adds undesirable disruption in the video being viewed. This is especially true in those conference arrangements which use digital signals to transmit the video information.

It is also important that after an interval of concurrent talkers the single retaining talker should be viewing a conference location he or she is responding or otherwise talking to and not some other location. This desired result may not be obtained in the prior known arrangements which have no mechanism for resolving contention among the locations for the video to be viewed.

Similar problems arise in conference arrangements including the transmission of graphics information. In one known conference arrangement, it is possible that during an interval of concurrent graphics transmission from different locations some of the conference locations may be viewing graphics information transmitted from one location while other conference locations may be viewing graphics transmitted from another location. This, of course, can be extremely undesirable. Additionally, multiple switches of the video being transmitted may be required before arriving at the "right" graphics transmission location. Again, in conference arrangements using digital transmission of the video information such unnecessary switching is undesirable because of the resulting disruptions in the video being viewed.

SUMMARY OF THE INVENTION

Contention among conference locations for the video information to be transmitted to the locations is resolved, in accordance with an aspect of the invention, by employing talker and graphics contention resolution processes.

A talker contention process selects, in accordance with an aspect of the invention, the video to be transmitted to the other locations from a location determined to have the one-and-only-one talker during a predetermined talker timing interval. The process inhibits switching the video information being transmitted until a different one-and-only-one talker location is detected during the predetermined talker contention timing interval, or a location starts to display graphics. The video information from the last selected talker location is transmitted to the presently selected one-and-only-one talker location.

A graphics contention process selects, in accordance with an aspect of the invention, the graphics information to be transmitted to the other locations by first rejecting all requests for graphics transmission from the locations until one-and-only-one graphics request is detected during a predetermined graphics timing interval. Once transmission of graphics information is assigned to a location, the other locations in the conference are transmitted the graphics video information until the location displaying the graphics information releases from the graphics tansmission mode. The location transmitting graphics information is transmitted video information from the (current) last of the other locations determined to be the one-and-only-one talker location.

Each conference location can normally select the video information to be transmitted to it. Thus, the talker and graphics contention processes can be manually overridden.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more fully understood from the following detailed description of an illustrative embodiment taken in connection with the appended figures in which:

FIG. 1 shows in simplified block diagram form a system arrangement including a Multilocation Conference Terminal (MLCT) incorporating an embodiment of the invention;

FIG. 2 depicts the VTS signal data format used in the system of FIG. 1;

FIG. 3 illustrates the cross connect frame format used in the system of FIG. 1;

FIG. 4 shows in simplified block diagram form details of microprocessor system 101 employed in the system of FIG. 1;

FIG. 5 depicts in simplified block diagram form details of transmission facility interface 104 used in the system of FIG. 1;

FIG. 6 shows in simplified block diagram form details of cross-connect 102 employed in the system of FIG. 1;

FIG. 7 illustrates in simplified block diagram form details of time multiplexed switch 601 used in cross-connect 102 of FIG. 6;

FIG. 8 shows in simplified block diagram form details of N.times.N switch 602 used in cross-connect 102 of FIG. 6;

FIG. 9 illustrates the cross-connect 102 audio and video time slot assignments utilized in effecting an aspect of the invention;

FIG. 10 shows in simplified block diagram form details of bridge 103 used in the system of FIG. 1;

FIG. 11 depicts in simplified block diagram form details of bridge input circuit (BOC) 1001 used in bridge 103 of FIG. 10;

FIG. 12 illustrates the output frame format of the audio encryption process which is useful in describing aspects of the invention;

FIG. 13 illustrates timing diagrams useful in describing the encryption and decryption process;

FIG. 14 shows in simplified block diagram form details of audio decryptor (DEC) 1002 used in bridge 103 of FIG. 10;

FIG. 15 illustrates a flowchart of the decryptor program routine for the common control operation of decryptor 1002 to controllably decrypt the incoming audio and control information of bridge 103;

FIGS. 16, 17, 18 and 19 when connected as shown form a flow chart of the PADEC sub-routine used in the decryptor routine of FIG. 15;

FIGS. 20 and 21 connected as shown form a flow chart of the CENCHR sub-routine used in the decryptor routine of FIG. 15;

FIG. 22 shows in simplified block diagram form details of audio bridge 1003 employed in bridge 103 of FIG. 10;

FIGS. 23, 24, 25 and 26 when connected as shown form a flow chart of a program routine for controllably operating DSP 2201 in audio bridge 1003 of FIG. 22;

FIGS. 27, 28, 29 and 30 when connected as shown form a flow chart of a program routine for controllably operating DSP 2202 in audio bridge 1003 of FIG. 22;

FIG. 31 is a flow chart of a DSP control (DSPCTL) program task for operating host processor 2203 to interact with digital signal processors (DSPs) 2201 and 2202 in audio bridge 1003 of FIG. 22;

FIG. 32 is a flow chart of a noise guard program (NGRD) sub-routine used in the DSPCTL program task of FIG. 31;

FIG. 33 shows in simplified block diagram form details of audio encryptor (ENC) 1004 employed in bridge 103 of FIG. 10;

FIGS. 34, 35 and 36 when connected as shown form a flow chart of program routine ESCVC to effect common control of the mixed audio information from audio bridge 1003;

FIG. 37 is a flow chart of the PAENC sub-routine used in the ESCVC program routine of FIGS. 34, 35 and 36;

FIG. 38 depicts in simplified block diagram form details of bridge output circuit (BOC) 1005 used in bridge 103 of FIG. 10;

FIG. 39 shows in simplified block diagram form details of control processor (CF) 1006 used in bridge 103 of FIG. 10;

FIG. 40 is a flow chart of program routine XPCTL for operating control processor 1006 of FIG. 39 to control communications to audio decryptor 1002, audio bridge 1003 and audio encryptor 1004;

FIG. 41 is a flow chart of sub-routine PREST used in the XPCTL program routine of FIG. 40;

FIGS. 42, 43, 44 and 45 when connected as shown form a flow chart of the PRNLA sub-routine employed in the XPCTL program routine of FIG. 40;

FIG. 46 is a flow chart of the PRDENT sub-routine employed in the XPCTL program routine of FIG. 40;

FIG. 47 illustrates the relationship among the program tasks that perform the video selection algorithm and the fast update algorithm;

FIGS. 48, 49 and 50 when connected as shown form a flow chart of steps performed in the new talker process (NTP) task by control processor 1006 of FIG. 39;

FIG. 51 is a flow chart of the CONTEND sub-routine used in the NTP program task of FIGS. 48, 49 and 50;

FIG. 52 is a flow chart of the NTSAVE sub-routine used in the NTP progam task of FIGS. 48, 49 and 50;

FIGS. 53, 54, 55 and 56 when connected as shown form a flow chart of the steps performed in the new graphics process (NGP) program task by control processor 1006 of FIG. 39;

FIG. 57 is a flow chat of the GRACK sub-routine used in the NGP program task of FIGS. 53, 54, 55 and 56;

FIGS. 58 and 59 when connected as shown form a flow chart of the steps performed in the video selection (VSEL) program task by control processor 1006 of FIG. 39;

FIGS. 60 and 61 when connected as shown form a flow chart of the steps performed in the fast update generator (FUGEN) program task by control processor 1006 of FIG. 39;

FIGS. 62 and 63 when connected as shown form a flow chart of the steps performed in the fast update monitor (FUMON) program task by control processor 1006 of FIG. 39;

FIGS. 64 and 65 when connected as shown form a flow chart of the steps performed in the video switch (VSWCH) program task by control processor 1006 of FIG. 39; and

FIG. 66 is a flow chart of the SWITCHLK sub-routine used in the VSWCH program task of FIGS. 64 and 65; and

FIGS. 67 and 68 when connected as shown form a flow chart of steps performed in facility administrator (FADMIN) program task by control processor 1006 of FIG. 39.

DETAILED DESCRIPTION

General

The Multilocation Conference Terminal, hereinafter referred to as MLCT, is employed to establish and control a multilocation audiovisual teleconference in a Video Teleconferencing Service, hereinafter referred to as VTS, for conferences involving a plurality of VTS conference rooms. Accordingly, FIG. 1 shows in simplified block diagram form a system arrangement including a pluralty of MLCT's, namely, MLCTs 1 through Y and a plurality of conference rooms, namely, rooms 1 through M, which may be controllably interconnected via the MLCT's and transmission facilities 10. Each of MLCTs 1 through Y includes a plurality of VTS communication ports, associated with data links 106-1 through 106-N, for interconnecting up to N rooms via transmission facilities 10. Transmission facilities 10 include both terrestrial communication channels and/or satellite channels. Additionally, facilities 10 also include arrangements for interconnecting one or more of the conference rooms, i.e., conference locations, to an associated MLCT for establishing a conference. These connections may be established manually or via switching apparatus, for example, a digital cross connect arrangement. When satellite channels are deployed a multiplicity of MLCTs are used to reduce the number of end-to-end satellite hops to a maximum of one. In the satellite mode of operation, the MLCTs form a distributed conferencing control structure.

A number of conference configurations are realizable including one or more MLCTs. For example, a single MLCT may be used to include up to N=6 rooms in a conference over either local or long-haul terrestrial communication facilities. While it is possible to use only one MLCT in an all terrestrial confererence, it is not necessary to do so. Two MLCT's can be connected terrestrially, allowing savings of transmission facilities. In a mixed satellite/terrestrial conference network, distributed conferencing is used with a MLCT being associated with each satellite earth station. Satellite and terrestrial connections remain unchanged during an ungoing conference.

Each of MLCTs 1 through Y provides a time-space-time switching function and includes microprocessor system 101, digital cross connect 102, bridge 103, transmission facility interface 104 and a plurality of data terminal ports 105-1 through 105-T. Data terminals may be connected to data terminal ports 105-1 through 105-T for manually providing teleconference setup information including VTS port assignment and other information needed for the ongoing conference. Where an operations support system or other reservation service computer is available, the data terminal ports are used to connect the MLCT thereto for carrying out the necessary conference setup and maintenance procedures.

As described hereinafter each MLCT provides audio mixing and video switching of encrypted digital VTS signals which are supplied via VTS ports and data links 106-1 through 106-N, respectively, to transmission facilities 10 and, in turn, to associated ones of rooms 1 through M and/or to another MLCT. In this example, each MLCT includes six (6) VTS ports, i.e., N=6.

Each of conference rooms 1 through M includes known audio and video equipment. For example, each room includes video monitors and cameras 120, speakers and microphones 121, audio detectors 122, picture processor 123, rooms controls 124 and room controller 125. Rooms substantially identical to rooms 1 through M are presently commercially available for point-to-point audiovisual conferences. Room controller 124 is arranged to respond to an auxiliary control channel signal in the VTS signal from an associated MLCT for controlling picture processor 123 in accordance with aspects of the invention as will be described below. Picture processor 123 is commercially available from Nippon Electric Corporation and is described in Western Electric Company KS-22456 specification. U.S. Pat. No. 3,601,530 discloses a video conference arrangement using voice-switched cameras in a conference room. Further details of the point-to-point conference room are broadly described in an article by Mr. Bernard A. Wright entitled, "The Design and Provisions of PICTUREPHONE Meeting Service (PMS) Conference Centers for Video Teleconferencing", in the IEEE Communications Magazine, pages 30-36, March 1983. Also see an article by Audrey J. Kames and W. Gordon Heffron entitled, " Human Factors Design of PICTUREPHONE Meeting Service" in GLOBECOM '82 Conference Record, Volume 3, pages 976-981, November 1982 for a broad overview of the commercially available point-to-point video teleconferencing service.

As indicated above, the MLCTs are interconnected via transmission facilities 10 to associated ones of rooms 1-M and/or another one of the MLCTs through VTS ports 501-1 through 501-N (FIG. 5) and data links 106-1 through 106-N, respectively. The VTS signals are transmitted over one or more time division multiplexed channels, for example, T1 lines, depending on the data rate being employed. In this example, the data rates are selectable at 1.544, 3.088 or 6.176 Mb/sec. In a specific embodiment, two T1 lines are used having the 3.088 Mb/sec data rate with each T1 line having an incoming data link and an outgoing data link. The VTS data format is shown in FIG. 2. One of the T1 lines, designated DS-1 No. 1 carries encoded audio and control channels in addition to video data. The other T1 lines, designated DS-1 No. 2 through DS-1 No. 4 carry only video data. The T1 lines do not have standard DS-1 formats except for framing bits Ft.

The format for DS-1 No. 1 is a combination of three groups of information; one associated with the video signal; another with audio; and another with the control data channel. The control group consists of a single C-bit per frame located in word 1 bit 4, as shown in FIG. 2. The C-bit implements an 8 Kb/sec data link between the MLCT and the remote location communicating to it, i.e., either a room or another MLCT. The audio group consists of 16 audio bits, A1 to A16, a D-bit, as well as "1"s in the shown bit positions, all within the first three words of DS-1 No. 1. The A-bits represent two samples per frame of mu-255 coded audio. Bits A1 through A8 are audio bits belonging to a first sample of the audio signal. Bits A9 through A16 are audio bits belonging to the second sample of the audio signal. The audio may be encrypted or transmitted "on the clear". The D-bit is used for synchronization of the audio encryptor 1004 and decryptor 1002 described below.

The first three words of the DS-1 No. 1 contain fixed "1"s in the shown position to maintain the required "1"s density during these words for all possible codes transmitted. The remaining bits in DS-1 No. 1, i.e., FD, X, X, and those of DS-1 No. 2 through DS-1 No. 4 contain video information. The MLCT does not process these remaining bit locations aside from maintaining their relative position throughout its switching function. Indeed, except for the information included in the C-bit position, the VTS data format is essentially identical to that employed in the existing point-to-point teleconferencing service available through American Telephone and Telegraph Company.

MLCT Operation--General

A Multilocation Conference Terminal (e.g., MLCT1, FIG. 1) located in a Video Teleconferencing Service (VTS) is connected via transmission facilities 10 to conference locations, i.e., rooms and other MLCTs dependent on the conference being set up.

The MLCT is always in one of the following modes:

Standby (SBY)

In the standby mode the MLCT is not processing a conference. It is continually performing internal diagnostics to ensure that it is fully operational.

Sender's Choice (SC)

A MLCT in the SC mode is set up to operate a SC conference.

Viewer's Choice (VC)

A MLCT in the VC mode is set up to operate a VC conference.

No MLCT mode changes are allowed while the MLCT is processing a conference. To change modes the MLCT must first be removed from the conference.

The steps to set up the MLCT for a conference are as follows:

1. Enter command(s) into the MLCT through an input terminal connected to one of input ports 105-1 through 105-T to place it in the desired mode for the conference (VC,SC) and to define the MLCT's ID in the conference.

2. Setup transmission connections to the MLCT required for the conference.

3. Enter command(s) into the MLCT to assign the VTS ports as either:

a. connected to a room (specify room ID).

b. a broadcast link (outgoing transmission path to all other MLCTs in the conference) and/or a MLCT link (incoming transmission path from another MLCT, specify that MLCT's ID).

Once these steps are completed the conference is in progress and the MLCT will automatically set up and maintain communication with its serving rooms, i.e., rooms associated to it, and other MLCTs.

If communication over a VTS port connected to a room, e.g., room I, is lost (or is never established in the first place) the MLCT operates the conference without room I. No other room can view room I. The audio transmitted by room I is not muted unless audio decryptor 1002 (FIG. 10) detects a facility failure in the audio signal incoming from room I. The video transmitted to room I is selected by assuming that room is in the automatic video switching (AVX) mode. Thus, room I essentially becomes a spectator. Room I views a new talker room or a new graphics room as described below. The other rooms hear room I if its audio signal is not muted, but they cannot view room I.

If communication over a broadcast link or MLCT link is lost (or is never established in the first place) the MLCT operates a conference for only the rooms that it serves.

Configuration changes to a conference already in progress are realized as follows:

1. If any of the MLCT's room, broadcast, or MLCT links are to be removed, then:

a. Command(s) must be entered into the MLCT that unassign those links.

b. The port connections to be removed are taken down.

2. If any room, broadcast, or MLCT links are to be added to the conference, then:

a. The port connections just assigned are set up.

b. Command(s) must be entered into the MLCT to assign each new port as connected to a room or as a broadcast link and/or MLCT link.

Any number of configuration changes can occur during a conference.

The microprocessor system (MS) 101 (FIG. 1) maintains control of the MLCT. Commands are entered through the links 105-1 through 105-T into the MS 101. The MS 101 interprets these commands and issues signals to set up the other components of the MLCT. The MS 101 is responsible for downloading the proper program code into bridge 103 when any MLCT mode change is performed and for informing the bridge on all the conference attributes (MLCT's ID and link assignments). MS 101 cannot communicate directly with other MLCTs or any room controllers.

Bridge 103 computes the weighted sums of the audio signals, receives the control signals that come over the incoming links from the rooms and other MLCTs, generates the control signals that are transmitted to the rooms and other MLCTs, signals MS 101 to execute video switches, and monitors the links to detect facility failures in the control and audio signals.

MS 101 and bridge 103 interact during a conference to perform two primary functions. Bridge 103 directs MS 101 to perform switching of the video signals. MS 101 and bridge 103 keep each other informed of link failures.

Cross-connect 102 and transmission facility interface 104 provide bridge 103 with audio and control signals, receive conferenced audio and control signals from bridge 103 and perform the switching of the video signals under the control of the MS 101.

The MLCT can be in one of three modes (SBY, SC, or VC) as described above. Bridge 103 can be in one of four states. Three of the bridge states correspond to the MLCT modes (SBY, SC, and VC). Bridge 103 enters the fourth state, called the kernel state, while MS 101 is downloading a new program code. The MLCT's mode and bridge state are set up prior to the start of the conference and do not change while the conference is in progress. By definition the MLCT mode and bridge state during a conference must be the same, either sender's choice or viewer's choice.

When the conference is first initiated, bridge 103 comes up in the stand alone (SA) condition. In the SA condition bridge 103 operates a conference for just its serving rooms.

When the bridge verifies that all of its broadcast links and MLCT links are active, it assumes the distributed (DS) condition. In the DS condition the bridge will operate in the conference with other MLCTs. The conference messages are exchanged with the other MLCTs. If the MLCT is in the DS condition and one of its broadcast or MLCT links becomes inactive, bridge 103 assumes the SA state again.

If the bridge has communication with the other MLCTs it will notify them of its DS/SA condition transitions by transmitting an MLCT status (MSTAT) message specifying the condition (DS,SA) it has assumed.

The MLCT will try to operate the conference as set up by the commands entered through MS 101. At the initialization of the conference the MLCT mode (VC,SC) and MLCT's own ID is specified before any links are assigned. MS 101 will have already downloaded the program code for the required bridge state into bridge 103. Bridge 103 starts up in the SA condition in the mode specified (VC,SC) with all ports unassigned.

1. MS 101 communicates with bridge 103 to assign a port to a room (MS specifies room ID) or assign a port's in-link, i.e., an incoming transmission path, as a MLCT link (MS specifies MLCT ID) and/or assign the port's out-link, i.e., an outgoing transmission path, as a broadcast link.

2. Bridge 103 marks the in and/or out link as assigned, inactive, and muted.

a. If the port is assigned to a room bridge 103 marks that room assigned.

b. If the in link is assigned to an MLCT bridge 103 marks that MLCT assigned.

3. Bridge 103 trys to establish communication over the links. If communication is established the link is marked active.

4. If decryptor 1002 (FIG. 10) detects no facility failure in the audio signal of the assigned incoming link, bridge 103 unmutes the audio signal and marks the in link as unmuted.

Any subsequent command entered through one of the MLCT's administrative links that declares link(s) to be assigned will be accepted only if it does not reassign links that are presently assigned. All of these subsequent commands are executed (if they are accepted) in the same manner as the first command that assigned links in the conference.

Any subsequent command entered through one of the MLCT's administrative links that declares an in link and/or out link to be unassigned will be accepted only if that in link and/or out link is presently assigned. MS 101 communicates with bridge 103 to update the bridge's link assignments. Bridge 103 does the following:

1. Mark the specified links as unassigned. 2. If any links are being marked unassigned were assigned to rooms, mark those rooms as unassigned. 3. If the last MLCT link assigned to another MLCT, MLCT J, is being marked unassigned, then:

a. MLCT J is marked unassigned.

b. All rooms served by MLCT J are marked unassigned.

Any link or room that is marked unassigned is automatically marked inactive and muted.

While the MLCT is involved in a conference (i.e., some links are assigned), no command entered into the MLCT that specifies changing either the MLCT mode or MLCT's own ID will be accepted.

Broadcast links are dedicated to ensure that the MLCT will be able to transmit any of the required combination of video signals to the other MLCTs. At the time of the conference set-up, the MLCT decides how to dedicate each of its broadcast links. The dedication of these broadcast links will not be changed unless the conference set up is changed.

In a Viewer's Choice conference, MLCTs may need more than one broadcast link. The push-to-see (PTS) mode requires that MLCTs be able to transmit any combination of video signals to the rooms. In a Viewer's Choice conference the broadcast links are dedicated according to the following priorities:

1. If the MLCT has enough broadcast links it assigns a broadcast link to each of its serving rooms. In this case all of the other MLCTs always receive video from every room served by this MLCT.

2. If the MLCT has enough broadcast links it assigns a broadcast link to each of the rooms served by another MLCT. In this case the MLCT will always be able to transmit the video required for each of the rooms served by other MLCTs.

3. If the MLCT does not have enough broadcast links to satisfy either of two previous cases, then the MLCT does not have enough broadcast links to operate properly in the conference. In this case the MLCT prints a warning message.

If the MLCT has more than enough broadcast links needed for dedication to the rooms, then it marks the remaining broadcast links as undedicated.

In a Sender's Choice conference each MLCT requires only one broadcast link. This broadcast link is not dedicated.

Returning to MLCT FIG. 1, there is shown MLCT1 including a microprocessor system (MS) 101, digital cross connect 102, bridge 103 and transmission facility interface 104 which are interconnected as shown by a multiplicity of data and control paths in order to perform required multilocation audio video teleconferencing functions.

Microprocessor System (MS)

The MLCT microprocessor system (MS) 101 is shown in simplified block diagram form in FIG. 4. Shown are CPU 401, memory 402, back-up memory 403, peripheral interface 404 and communications interface 405 all interconnected via bus 406. Memory 402 includes program storage in ROM and data storage in RAM. Back-up memory 403 stores data pertaining to conference set-up in a nonvolatile storage such as bubble memory in order to maintain conference set-up information integrity in the event of a short-time power outage to eliminate the re-entry of the information at the data terminals. Microprocessor system 101 communicates via peripheral interface 404 to transmission facility interface 104, cross connect 102 and bridge 103. Peripheral interface 404 communicates to the transmission facility interface 102 to transfer time-slot map information as discussed hereinafter or in other words to allow a connection to a VTS port of the MLCT. Microprocessor system 101 communicates through peripheral interface 404 to cross-connect 102 to map the time multiplexed switches (TMS) for configuring the TMS output data links 603-1 through 603-N (FIG. 6) to contain the information shown in TABLE 3 below and to perform the video switch function by the use of N.times.N switch 602 (FIG. 6) as described below. The bridge 102 communication is also handled by the peripheral interface 404. Information transfer to bridge 103 includes VTS port assignment, conference set-up including the designation of the various connections to the VTS data links and whether conference rooms or MLCTs are connected to them. Communications interface 405 is used to provide a connection to serial data terminal connections 105-1 through 105-T, in one example T=5, which are used to communicate with the conference set-up operator, a reservation system, or a port system to handle the conference reservation from multiple locations and to perform maintenance operations on the system. The microprocessor system 101 functions may be divided into three distinct classes: maintenance, operational (video switches), and conference parameter management. It performs all communication and administrative functions for the MLCT. It has communication access to all major components of the system to perform conference set-up operations, maintenance functions, error recovery, transmission facility performance monitoring, and video switches upon request from bridge 103. Microprocessor system 101 is essentially identical to the arrangement described by A. J. Cirillo, L. F. Horney II and J. D. Moore in an article entitled, "DACS Microprocessor System", NTC'81, IEEE 1981 National Telecommunications Conference, Vol. 1, pages B1.3.1-B1.3.6, November 1981.

Transmission Facility Interface

Details of transmission facility interface 104 are shown in simplified block diagram form in FIG. 5. It includes VTS ports 500-1 through 500-N, each of which includes a plurality of digroup circuits 501-1 through 501-R. As noted above, in this example two T1 lines are used for each of VTS ports 500-1 through 500-N and, therefore, two digroup circuits are used per VTS port. Again, the VTS ports connect transmission facility interface 104 via transmission facilities 10 (FIG. 1) to associate conference rooms and/or to associated MLCTs. Each of digroup circuits 501-1 through 501-R is connected via a corresponding one of the data links 502-1 through 502-R to cross connect 102. Each of digroup circuits 501-1 through 501-R in a VTS port receives data from cross connection 102 on a shared data link, for example, via data link 108-1. Each digroup circuit in transmission facility interface 102 provides a read-write capability to microprocessor system 101 of all error source registers (not shown) and control registers (not shown). The error source registers relate to various internal hardware error detectors as well as to transmission facility related problems such as T1 framing errors, out-of-frame conditions, slips and carrier failure alarms (CFA). In addition to the DS-1 termination function, the digroup circuit implements the "time" portion of the time-space-time switching function of the MLCT. Its receiving section contains a line clock recovery circuit, a framer for recovery of the Ft framing bits, an elastic store, transmission facility error detectors and a time-slot interchanger (RTSI) (all not shown) to transform the T1 frame format to one compatible with that of the cross-connect, i.e., the cross connect data format of FIG. 3. Its transmitting section contains a second time-slot interchanger (TTSI) (not shown) and a DS-1 signal formatter (not shown) to convert the cross-connect data format to the DS-1 format.

The signal format provided by the digroup circuit to the cross-connect 102 is shown in FIG. 3. It consists of a frame of 256 time-slots, labeled time-slot 0 through time-slot 255. It is transported by three rails at a data rate of 8.192 Mb/sec each. Each time-slot contains 12 bits of information: 8 data bits, labeled D1 through D8, three spare bits, and a parity bit that provides odd parity over the 12 bits in the time slot and the eight-bit code representing the time-slot number. The RTSI may be configured to fill any of the 256 time slots with the received 24 words of the incoming T1 line. Similarly, the TTSI may choose any of the 256 time-slots (up to 24) and selectively place them in the outgoing T1 line.

In this example, the digroup circuits 502-1 through 502-R, where R=4, for VTS port 500-1 identify and format the incoming DS-1 signals. Specifically, digroup circuit 502-1 identifies the video control signals, c bit and audio signals in words 1, 2 and 3 and formats them in time slots 0, 1 and 2 in the cross connect frame format of FIG. 3. Similarly, it identifies the video information in words 4 through 24 and formats it into time slots 64 through 84 in the cross connect frame format of FIG. 3. Digroup circuit 502-2 identifies the video information in signal DS1 No. 2 and formats it into time slots 85 through 108 of the cross connect frame format. Digroup circuit 502-3, if used, identifies the video information in signal DS1 No. 3 and formats it into time slots 108 through 132 of the cross connect format. Finally, digroup circuit 502-4, if used, identifies the video information in signal DS1 No. 4 and formats it into time slots 133 through 156 of the cross connect format. For VTS port 500-2 the only difference from VTS port 500-1 is in the formatting of the video control signal, c-bit and audio signals. In this example, this information is formatted into time slots 4, 5 and 6 of the cross connect frame format.

This formatting is shown in FIG. 9 relating to the cross connect 102 frame formats. There is shown that for VTS port 500-3 the video control, c-bit and audio information is in time slots 8, 9 and 10, for VTS port 500-4 in time slots 12, 13 and 14, for VTS ports 500-4 in time slots 16, 17 and 18 and for VTS port 6, i.e., N=6, in time slots 20, 21 and 22. These formatted signals are supplied to cross connect 102.

Such digroup circuits are known in the art, see for example the digroup circuit described by R. P. Abbott and D. C. Koehler in an article entitled, "Digital Access and Cross-Connect System--System Architecture", NTC'81, IEEE 1981 National Telecommunication Conference, Vol. 1, pages B1.2.1-B1.2.7 at page B1.2.2., November 1981.

VTS ports 500 can be assigned in a conference as follows:

1. Both the input and output data links of a VTS port are assigned to a room;

2. The output data link of the VTS port is assigned as a so-called broadcast link, i.e., the outgoing signal is supplied to all other MLCTs in the conference; and

3. The input data link of the VTS port is assigned as a MLCT link, i.e., it receives an outgoing broadcast signal from another MLCT.

Cross Connect

Details of cross-connect 102 are shown in simplified block diagram form in FIG. 6. Cross-connect 102 provides the space switching function of the MLCT time-space-time switching function. Cross-connect 102 includes time-multiplexed switches (TMS) 601-1 through 601-N and N.times.N switch 602. Time multiplexed switches 601-1 through 601-N are assigned on a one-to-one basis to VTS ports 500-1 through 500-N, respectively, in transmission facility interface 104. Data links 107-1 through 107-N are supplied from transmission interface 104 to TMS 601-1 through 601-N, respectively. Also supplied to TMS 601-1 through 601-N are data links 109-1 through 109-N, respectively. Data links 109-1 through 109-N carry processed information from bridge 103 relating to associated VTS ports 500-1 through 500-N, respectively. Each of TMS 601-1 through TMS 601-N selects on a per time slot basis information from its input data links and combines the information to generate at its output data link another 256 time-slot composite signal frame containing the time slot selection that the TMS is programmed to produce. It is important to note that the video information from a conference location is included in several incoming signals and that the TMS combines the information into the one composite signal. This combining of all the video information from a corresponding conference location into one composite signal enables, in accordance with an aspect of the invention, a rapid switch of the video being viewed. Outputs from TMS 601-1 through 601-N are controllably selected by N.times.N switch 602 and supplied via 108-1 through 108-N, respectively, to transmission facility interface 104 for transmission on T1 transmission facilities to transmission facility 10 to be routed to appropriate ones of the conference room and/or other MLCTs, TMS 601-1 through TMS 601-N and N.times.N switch 602 are controlled by microprocessor system 101 to realize a desired video and audio switch to the ports. Through this arrangement anyone of the composite signals from TMS 601-1 through TMS 601-N is selectable via switch 602 for transmission to any one of VTS ports 500.

It is noted that each VTS port receives an audio mix from all the other ports. Thus, the audio that must accompany the video to each port is a different mix. The appropriate audio mix and video are switched to the VTS ports by employing cross-connect 102. Error free, i.e., non-disruptive switching is realized, in accordance with an aspect of the invention, by employing TMS 601-1 through 601-N to each generate a so-called composite audio and video signal. The composite signal includes all the video information from a room associated with the corresponding VTS port and the audio mixes generated by bridge 103 to be transmitted to all of the rooms and partial audio sums to be transmitted to other MLCTs. Cross connect 102 time slot assignments of the signals generated at the outputs of TMS 601-1 through 601-N are shown in FIG. 9. Accordingly, shown in FIG. 9 are the composite signals combined in cross-connect 102 for each of the VTS ports 500-1 through 500-N. Thus, for VTS port 500-1 the audio mix to VTS port 1 is in fixed time slots 32, 33 and 34 as supplied from bridge output circuit 1005, the audio mix to VITS port 500-2 is in fixed time slots 36, 37 and 38, the audio mix to VTS port 500-3 is inserted into fixed time slots 40, 41 and 42, the audio mix to VTS port 500-9 is in fixed time-slots 44, 45 and 46, the audio mix to VTS port 500-5 is in fixed time slots 48, 49 and, 50 and finally, the audio mix to VTS port 500-6 is in time slots 52, 53 and 54. The video from VTS port 500-1 is combined into time slots 64 through 156. The audio from VTS port 500-1 which is in time slots 0, 1 and 2 is supplied to bridge 103 via 110-1 to be appropriately mixed with the audio from the other VTS ports and, then, supplied via 109-1 from bridge 103 to TMS 601-1 in the appropriate fixed time slots in the composite signals associated with VTS port 500-1. The composite signals associated with VTS ports 500-2 through 500-6 are similarly obtained as shown in FIG. 9. Consequently, when the video from anyone of the VTS ports and, hence, the associated conference room is switched via N.times.N switch 602 to anyone of the other conference rooms, the proper audio mix for the specific conference rooms is present and obtained by the MLCT selecting the audio mix in the fixed time slots assigned to the associated conference rooms. The functions of TMS 600 and switch 602 may be realized by employing dual multiplexers of a type described in the article entitled, "Digital Access and Cross-Connect System-System Architecture" noted above.

FIG. 7 shows in simplified block diagram form details of time multiplexed switches 601 of cross-connect 102 (FIG. 6). Accordingly, shown are (R+1).times.1 data selector 701, TMS control memory 702 and time slot counter 703. Selector 701 is controlled by control codes stored in control memory 702. The control codes are written into memory 702 from microprocessor system 101 and include the time slot switching information for the time multiplexed switch for an assigned VTS port. Once the control information is written into control memory 702 no further interaction with microprocessor system 101 is required until a new data link selection is made. Control memory 702 is addressed by time slot counter 703 which generates a sequentially incrementing modulo-256 counter signal synchronized to the time slot occurrences of the cross-connect data format as shown in FIG. 3.

FIG. 8 shows in simplified block diagram form details of N.times.N switch 602 of cross-connect 102 FIG. 6. Switch 602 includes N.times.1 data selectors 801-1 through 801-N which are controlled by control registers 802-1 through 802-N, respectively. Each of outputs 108-1 through 108-N of data selectors 801-1 through 801-N, respectively, is connected to an associated one of VTS ports 500-1 through 500-N (FIG. 5). Outputs 603-1 through 603-N from time multiplexed switches 601-1 through 601-N (FIG. 6), respectively, are supplied to respective inputs of selectors 801-1 through 801-N. Switching commands are supplied from microprocessor system 101 via control lines 605-1 through 605-N to control registers 802-1 through 802-N, respectively. In response to the switching commands each of selectors 801-1 through 801-N selects an appropriate one to its inputs and provides it to its associated VTS port in transmission facility interface 104. Consequently, any one of the composite signals supplied from time multiplexed switches 601 can be selected for transmission to any one of the VTS ports 500. The input selection is controlled to occur at the boundary between the cross-connect data format frame in order to prevent any mixing of information from different inputs within a given frame.

In summary, the operation of cross-connect 102 in realizing nondisruptive audio and rapid video switching, in accordance with an aspect of the invention, is such that the first 3 words of DS-1 No. 1 of all N incoming VTS signals are identified by and formatted into predetermined time slots by digroups circuit 501 and sent via TMS 601-1 through 601-N to bridge 103 for processing the audio and control information and for performing sub-byte bit manipulation of video-related signaling bits located in the first word. All other words containing video information are formatted into a composite video signal and provided to N.times.N switch 602 for the video switching function of the MLCT along with processed audio, control, and video related information are supplied by each of data links 109-1 through 109-N from bridge 103. After any selection is made by N.times.N switch 602, it is up to the particular one of digroup circuits 501 (FIG. 5) to choose the necessary timeslots to form the corresponding outgoing VTS signal.

This implies, as will be seen in the following, that the processed audio and control signals generated in bridge 103 must appear on all data links 603 presented to N.times.N switch 602 in order to affect only video information when the switch state is changed. The time-slot assignment has been chosen, along with other system features, so that after a conference configuration has been decided and set-up, the time-space-time switching configuration is static except for N.times.N switch 602. N.times.N switch 602 is the only switching element whose configuration is dynamic, i.e., during video switches. The other switching elements remain constant until a new conference configuration is required, i.e., addition or deletion of a conference room or MLCT. This type of arrangement allows, in accordance with an aspect of the invention, very efficient and rapid video selection operations. In fact, not using the above method implies remapping one time-slot at a time of all the switching elements to perform a video switch thereby resulting in serious video selection speed degradations.

Table 1 shows the relative time-slot assignment of all information groups as they appear at the output of TMS 601-1 through 601-N. Entries of the form "vnwn" and "vnWn" represents a group of 3 timeslot each. The "Vn" entries represent a group of 21+(24.times.R) time-slots to accommodate the video information from each VTS port. The table is subdivided into two sections each pertaining to where the information is routed. Bridge 103, for example, has access in space and time to all audio and control inputs to the MLCT. Conversely, bridge 103 provides N copies of the processed audio and control information mixed with video portions pertinent to each VTS port. The transmit sections of digroup circuits (DC) 500 in the transmission facility interface 104 (FIG. 4) choose the time-slots under the "VTS Output Contribution" to construct the word pattern in the R outgoing T1 lines. Once this selection is performed, no other interaction is done with the DC TTSI. When a "space" switch is performed by N.times.N switch 602 (FIG. 6) it represents a vertical movement of the "VTS Output Contribution" section of the time-slot assignment table which affects only video information.

                                      TABLE 1
    __________________________________________________________________________
    Cross-Connect Time-Slot Assignment
    Time-Slot Assignment
    VTS Input Contribution Bridge 103 Contribution
    To Bridge 103       VTS Output Contribution
    __________________________________________________________________________
    L 1 v1w1
            --  --  --  v1 v1W1
                               v1W2
                                   V1Wn
                                       v1WN
    I 2 --  v2W2
                --  --  V2 v2W1
                               v2W2
                                   v2Wn
                                       v2WN
    N n --  --  vnwn
                    --  Vn vnW1
                               vnW2
                                   vnWn
                                       vnWN
    K N --  --  --  vNwN
                        VN vNW1
                               vNW2
                                   vNWn
                                       vNWN
    __________________________________________________________________________
     LEGENDA
     vn Video in word 1 of DS1 No. 1 from VTS Input Port n
     Vn Video from VTS Input Port n
     wn Control and Audio from VTS Input Port n
     Wn Control and Bridged Audio to VTS Output Port n
     -- Unassigned TimeSlot Group


BRIDGE

FIG. 10 shows in simplified block diagram form details of MLCT bridge 103. Bridge 103 performs an access formatting function to cross-connect 102, an audio processing function and a conference control function. To this end, bridge 103 includes bridge input circuit (BIC) 1001, audio decryptor (DEC) 1002, audio bridge 1003, audio encryptor (ENC) 1004, bridge output (BOC) circuit 1005 and control processor (CP) 1006 which are interconnected by bus 1007. Details of the components of bridge 103 and their operation are shown in FIGS. 11 through 46 and described below.

Briefly, outputs from time multiplexed switches 601-1 through 601-N (FIG. 6) in cross-connect 102 are supplied via 110-1 through 110-N to bridge input circuit (BIC) 1001. BIC 1001 is arranged under control of processor 1006 to accept the audio time slots associated with the VTS ports. These time slots include words 1, 2 and 3 as shown in the VTS data format of FIG. 3. It separates the video signaling bits FD, X, X from the control bit C and the remaining audio bits for each of VTS ports 500-1 through 500-N. The video signaling bits associated with VTS ports 500-1 through 500-N are supplied via circuit paths 1008-1 through 1008-N, respectively, directly to bridge output circuit (BOC) 1005. This is necessary to keep the current frame video signaling bits with the current frame video information bits. As will be apparent from the discussion below, there is some delay in the audio because of the processing. The audio and control bits associated with each VTS port are supplied to audio decryptor 1002 via 1011. Audio decryptor (DEC) 1002 accesses BIC 1001 via 1012 for this purpose. DEC 1002 under control of processor 1006 separates the control bit C from the remaining audio associated with each VTS port and supplies them via 1009-1 through 1009-N to control processor 1006. DEC 1002 also decrypts, if necessary, the remaining audio for all the VTS ports and supplies it via 1001 to audio bridge 1003. The decryption process is performed using an appropriate decryption key supplied from microprocessor system 101 during the conference setup. The decryption process may be bypassed if the conference is not using encryption of the information. Audio bridge 1003 accesses an output port in DEC 1002 via 1014. Audio bridge 1003 generates the appropriate audio mixes for each VTS port. The audio mix for each of the VTS ports includes the audio from all other ports except itself. For example, the audio mix for VTS port 1 includes only the audio from VTS ports 2 through N. The method with which audio bridge sums the audio varies according to the number of data presently employed in a conference and whether the audio sum is destined to a conference room or to another MLCT. The audio sums are then supplied via 1015 and 1016 to audio encryptor (ENC) 1004. Also supplied to ENC 1004 via 1010-1 through 1010-N are modified control bits associated with each of VTS ports 1 through N, respectively. ENC 1004 encrypts, if necessary, the audio sums in accordance with an encryption key supplied from microprocessor system 101 during setting up of the conference. Again, if no encryption is being used the encryption process in ENC 1004 is bypassed. Additionally, ENC 1004 combines the modified control bits generator by processor 1006 with the appropriate audio sums and supplies them via 1017 and 1018 to bridge output circuit (BOC) 1005. Bridge output circuit 1005 combines the processed audio from ENC 1004 with the video signaling bits from BIC 1001 and formats a cross-connect 102 compatible signal for each VTS port with time-slot assignments consistent with those of Table 3.

Control processor 1006 in addition to control of bridge 103 performs all communications via the auxiliary C bit data channel to the conference rooms and other MLCTs in the conference for realizing necessary communications and video operations within the MLCT. Additionally, processor 1006 switches messages to be transmitted from room to room. Within bridge 103, processor 1006 communicates via parallel bus 1007.

Bridge Input Circuit (BIC)

FIG. 11 shows in simplified block diagram form details of bridge input circuit (BIC) 1001. As indicated above, BIC 1001 separates the video signaling bits FD, X, X from audio information for each VTS port. To this end, the outputs from time multiplexed switches 601-1 through 601-N (FIG. 6) are supplied via 110-1 through 110-N, respectively, to inputs of N.times.1 data selector 1101. Selector 1101 is controlled by control codes stored in control memory 1102 to perform the space selection function of the audio signals from the VTS ports shown in cross-connect 102 time slot assignments in FIG. 9. The control codes are written into memory 1102 from control processor 1006 (FIG. 10) and include the time slot switching information for the supplied data links from the time multiplexed switches 601-1 through 601-N. The output from selector 1101 is supplied to the data input of video latch 1103 and to data memory 1104. Video latch 1103 includes N latch circuits which are assigned on a one-to-one basis to data links 110-1 through 110-N and are used to temporarily store the video signaling bits FD, X, X from those links. To this end, control memory 1102 also includes codes supplied from control processor 1006 (FIG. 10) for enabling the appropriate latch circuits in video latch 1103 to temporarily store the corresponding video signaling bits which are then supplied via 1008-1 through 1008-N to bridge output circuit 1005. Each code word includes 8 bits and is associated with a specific time slot in the cross connect frame format shown in FIG. 3. Two of the bits are spares and two bits are used for parity. The remaining four bits are so-called operational control bits and are defined as follows:

b3: RVCSEN. Receive Video Control Slot. A logical 1 indicates that the respective time slot contains video control bits FD, X, X to be latched in latch 1103 and transmitted to BOC 1005. A logical 0 indicates a normal time slot.

b2: RPA2. Receive Port Address (MSB).

b1: RPA1. Receive Port Address.

b0: RPAO. Receive Port Address (LSB).

Bits b0-b2 form a three bit code indicating the origin of data to be received by bridge 103. Codes 0-5 select the respective VTS ports. Codes 6 or 7 will not select any port and BIC 1001 assumes that the associate time slot is idle. Data memory 1104 is a dual port memory written with the remaining audio and control information from selector 1101. Memory 1104 is accessed by decryptor 1002 via 1012 further to process the stored audio and control information. Data memory 1104 includes a RAM having duplicate sets of memory locations. A first set of the RAM locations is written with incoming data from selector 1101 while the second set of RAM locations is read by decryptor 1002 during a current frame. During a next subsequent frame the first set is read while the second set is written. Both control memory 1102 and data memory 1104 are sequentially addressed by time-slot counter 1105 which includes a modulo-256 binary counter synchronized to the internal frame time-slot boundaries. Once a code pattern is written into control memory 1102 no other interaction is required unless a VTS port and, hence, a conference room is to be added to or deleted from the conference.

Encryption/Decryption Process

Audio decryptor (DEC) 1002, audio bridge 1003 and audio encryptor (ENC) 1004 form, in accordance with an aspect of the invention, a programmable audio mixing arrangement including common control decryption and encryption. Such an arrangement is advantageously utilized in controllably adding rooms to and/or deleting rooms from an ongoing conference.

Private communication is realized by separately encrypting both the audio and video information. The audio information from the rooms must be decrypted in the MLCT to perform the audio mixing in bridge 1003. Then, the mixed audio is encrypted on a common control basis in ENC 1004.

For clarity and simplicity of description the general encryption process shall be discussed first. As described below encryption of the audio is obtained by using the Data Encryption Standard (DES) promulgated by the National Bureau of Standards.

The audio information is encrypted by adding each audio bit modulo-2 to a synchronous stream of cipher bits derived from the DES algorithm. The data input to be encrypted is derived from a 64-bit plain text counter having arbitrary contents which are known to both ENC 1004 and DEC 1002. The encryption process in the DES algorithm uses an appropriate 56 bit secret key in conjunction with the contents of the plain text counter to form the cipher bit stream which the audio is added modulo-2 bit-by-bit thereby forming the encrypted audio (A-bits). The encryption process may be easily bypassed. The audio information is sampled in a conference room by picture processor 123 (FIG. 1) and encoded with standard u-255 companding. Therefore, each 125 mu-sec frame includes two adjacent samples of the audio, as shown in Table 2 below.

Decryptor 1002 employs a common control routine to decrypt a plurality of simultaneously received, randomly phased encrypted audio signals by adding modulo-2 to each received signal a cipher bit stream synchronized with and identical to the one used for encrypting the signal. This is realized by use of the 56 bit encryption key and knowledge of the 64 bit plain text counter contents at the time the cipher stream was generated. The plain text counter state is sent over the encryption decipherment bits (D-bits). Also included in the D-bits are a framing pattern and a parity bit which provides EVEN parity over the unencrypted audio samples. This parity bit is used by decryptor 1002 to verify that decryption has been performed correctly. If the decryption is incorrect because of a data link failure, the decryptor will cause that link's audio to be muted. This insures that the audio performance of the conference is not degraded by the link failure.

FIG. 12 shows all the data associated with audio encryptor 1004 output signal for a VTS link in addition to the audio bits (A-bits) shown in Table 2. The relationship of the A-bits to the mu-255 companding law is shown in Table 2. Note that the A-bits do not represent the complemented values of the mu-255 codes as in a normal DS-1 format.

                  TABLE 2
    ______________________________________
    VTS Data Format: Audio Group
    A-bit      Mu-law    Description
    ______________________________________
    A1     A9      M0        Mantissa Least Significant Bit
    A2     A10     M1
    A3     A11     M2
    A4     A12     M3        Mantissa Most Significant Bit
    A5     A13     L0        Cord Least Significant Bit
    A6     A14     L1
    A7     A15     L2        Cord Most Significant Bit
    A8     A16     S         Sign
    ______________________________________


FIG. 12 shows the D-bit sequence. The D-bits are decipherment control bits which are used for synchronization of the audio encryption and decryption circuitry. The D-bits are an 8 Kb/sec data stream organized into a 128 bit superframe. The D-bits are organized into an odd-numbered group and an even numbered group. The superframe also includes 32 most significant bits (MSB) of the counter contents, namely L1-L32 which are used during the next superframe interval, and 32 check bits, namely, R1-R32. The 32 plain text counter contents bits L1-L32 are subdivided into 8 blocks of 4 bits. Appended to each block of 4 bits is a respective block of 4 error control check bits labeled R1 through R32. The L and R bits implement eight blocks of (8, 4) extended Hamming code words. The even-numbered D-bits contain a fixed sequence of framing bits labeled S1 through S6 and FA0 through FA7 and a set of audio parity bits. The value of the audio parity bits is such that in the frame that they occur, even parity is obtained over the on-the-clear audio sample represented by A9 through A16. This information is shown in TABLE 3 below.

                  TABLE 3
    ______________________________________
    VTS Data Format: Audio Decipherment Group
    ______________________________________
    Odd Numbered D-bits
    n   Counter Contents  Check Bits
    ______________________________________
    0   L1      L2     L3    L4   R1    R2    R3   R4
    1   L5      L6     L7    L8   R5    R6    R7   R8
    2   L9      L10    L11   L12  R9    R10   R11  R12
    3   L13     L14    L15   L16  R13   R14   R15  R16
    4   L17     L18    L19   L20  R17   R18   R19  R20
    5   L21     L22    L23   L24  R21   R22   R23  R24
    6   L25     L26    L27   L28  R25   R26   R27  R28
    7   L29     L30    L31   L32  R29   R30   R31  R32
    R4n+1 = L4n+1 .sym. L4n+2 .sym. L4n+3
    R4n+2 = L4n+2 .sym. L4n+3 .sym. L4n+4
    R4n+3 = L4n+1 .sym. L4n+2 .sym. L4n+4
    R4n+4 = L4n+1 .sym. L4n+3 .sym. L4n+4
    ______________________________________
    Even Numbered D-bits
    n    S1      S2     S3    S4   S5    S6   P    FAn
    ______________________________________
    0    1       0      0     1    1    1     P    0
    1    1       0      0     1    1    1     P    0
    2    1       0      0     1    1    1     P    0
    3    1       0      0     1    1    1     P    0
    4    1       0      0     1    1    1     P    1
    5    1       0      0     1    1    1     P    1
    6    1       0      0     1    1    1     P    1
    7    1       0      0     1    1    1     P    1
    ______________________________________
     The symbol .sym. indicates an "Exclusive OR" function.


For encryption, the 64 bit plain text counter used to obtain the cipher stream is subdivided into two sections, one including L1-L32 representing the most significant bits and another l1-l32 representing the 32 least significant bits (LSB). At the end of a D-bit superframe, the 32 most significant bits presently sent via the D-bits are utilized as a portion of the plain text during the next superframe and, therefore, are stored for that purpose. The L1-L32 section of the plain text counter is incremented by 1 and the resulting plain text counter contents are used for encryption. The l1-l32 bit section is reset to 0, and every 4 DS-1 frames (125 mu sec) the most 5 significant bits 28 through 32 are incremented and used to perform a plain text counter encryption. One encryption is required every 4 DS-1 frames, because in each frame 16 bits of the cipher stream are used to perform the bit-by-bit modulo-2 sum of the audio and cipher stream. This is turned to account, in accordance with an aspect of the invention, in obtaining the common control encryption and decryption processes described below. The decryptor is able to derive the same cipher stream that was used for encryption because it has obtained the most significant 32 bits (L1-L32) in use by the encryptor during the previous D-bit superframe. The process repeats after 32 encryptions or 128 D-bits have been transmitted. A timing diagram of the encryption process is shown in FIG. 13. The plain text counter section containing the most significant 32 bits L1-L32 is initialized to the preset values as shown in FIG. 13. The identifying code is an arbitrary number chosen by the user.

In the decryption process, the plain text data input to the DES module is derived from the received 32 most significant bits L1-L32 used to derive the cipher bit stream during the encryption process. The least significant 32 bit portions of the DES plain text data input, namely, bits l1-l32, comprise a plain text counter identical to that used in the encryption process. A framer function locates the phase of the 128 bit superframe boundaries and extracts the information shown in TABLE 3 above, and supplies the audio parity bit to a parity checker during the frame in which the D-bits occur. The parity check generates a cipher error indication. In turn, the cipher error ORed with an out of D-bit superframe indication generates a mute signal which is used to inhibit any erroneous audio information from impairing the conference.

As in the encryption process, the decryption process may readily be bypassed by generating a cipher stream of all 0's.

Audio Decryptor (DEC)

Details of audio decryptor (DEC) 1002 of FIG. 10 are shown in simplified block diagram form in FIG. 14. DEC 1002 provides, in accordance with an aspect of the invention, a common control arrangement for decrypting a multiplicity of VTS audio channels. Accordingly, shown are microcontroller 1401 and associated program memory 1402, BIC 1001 data input port 1403, BIC 1001 data read control port 1404, scratchpad RAM memory 1405, serial output port 1406, DES data encryption standard module 1407, control channel output port 1408 and control processor bus interface 1409. Microcontroller 1401 is interconnected with units 1403 through 1409 via bus 1410. Additionally, microcontroller 1401 receives a reset signal from interface 1409 and code instructions from program memory 1402 in response to address signals supplied thereto. Program memory 1402 is also connected to interface 1409. In this example, microcontroller 1401 is a Signetics 8.times.305 and DES module 1407 includes a Fairchild 9414-1,-2,-3,-4 DES chip set which implements the National Bureau of Standards (NBS) Data Encryption Standard (DES).

DEC 1002 accesses the control channel audio, and audio decipherment bits (D-bits) stored in BIC 1001 data memory 1104 (FIG. 11) by supplying an appropriate address via BIC data read control port 1404 over 1012 and by reading the contents of BIC data memory 1104 via BIC data input port 1403. DEC 1002 under control of microcontroller 1401 separates the control C-bits from the stored information and stores them in control channel output port 1208 for further processing by control processor 1006. The audio and audio decipherment bits are operated on to generate deciphered audio for all the VTS ports. The deciphered audio is supplied via serial output port 1406 to audio bridge 1003 for further processing. Control processor 1006 accesses DEC 1002 via control processor bus interface 1409. Interface 1409 provides read-write access to microcontroller program memory 1402 for loading the decryptor program into memory 1402, for verifying that the program is stored properly and to halt and restart microprocessor 1401 as appropriate. Once microcontroller 1401 is in the run mode, control processor 1006 communicates to microcontroller 1401 via bus 1410 for communicating fault conditions associated with the audio decryption operators. These fault conditions are used, in accordance with an aspect of the invention, to determine whether a conference room can be added to or deleted from an ongoing conference without disruption of the conference. Additionally, control processor 1006 (FIG. 39) supplies the DES key and the encryption modes, namely, encrypted/clear via interface 1409 to DEC 1002.

Moreover, DEC 1002 realizes common control decryption of the incoming audio signals under program control. Consequently, rooms may be dynamically added to or deleted from and ongoing conference without disrupting it, in accordance with an aspect of the invention.

Operation of audio decryptor (DEC) 1002 is controlled by microcontroller 1401 under control of programs stored in program memory 1402.

FIG. 15 is a flowchart of a program routine stored in program memory 1402 to effect, in accordance with an aspect of the invention, the common control decryption of the simultaneously received, randomly phased incoming VTS audio signals. Accordingly, the program is entered via oval 1501. Thereafter, operational block 1502 causes initialization of system variables to known states. For example, the ENC mode is set to bypass encryption if transmission is in the clear and AMUTST is set to muted until it is determined that the rooms are being decrypted properly, among others.

Conditional branch point 1503 tests to determine the beginning of the DS-1 frame, i.e., DS-1 frame sync, of the VTS signal. If the test result is true, operational block 1504 sets counter J to 1. is detected. Thereafter, operational block 1504 sets counter J to 1.

Operational block 1505 provides time slot address information for port J to BIC data read control port 1404. Operational block 1506 calls the PADEC subroutine to perform audio decryption and to extract the control channel information for port J.

The PADEC subroutine is shown in FIGS. 16, 17, 18 and 19 and described below.

Operational block 1507 causes the audio information for port J to be stored in an associated portion of scratchpad memory 1405.

Operational block 1508 causes the control channel information i.e., bit CJ, to be supplied to control processor 1006 via an associated one of data links 1009-1 through 1009-N.

Operational block 1509 causes the mute status supplied by subroutine PADEC to be stored in an AMUTST location associated with port J in scratchpad memory 1405.

Operation block 1510 sets counter J equal to J+1.

Conditional branch point 1511 tests to determine if J is greater than N. If the test result is false, control is returned to operational block 1507 and steps 1505 through 1511 are iterated until the test result in step 1511 is true, i.e., yes.

Conditional branch point 1512 tests to determine whether the mute status known by the decryptor is the same as the one known by the control processor 1006. If the test result is false, an interrupt is sent to control processor 1006 via operational block 1513. If the test result in step 1512 is true, no interrupt is sent to control processor 1006. Operational block 1514 causes the transferral of audio information from the scratchpad memory 1405 to audio bridge 1003 via data link 1013. Thereafter, control is returned to conditional branch point 1503. If the test result of conditional branch point 1503 is false, operational block 1515 calls subroutine CENCHR which performs a plain text counter encryption if requested and checks for requests from control processor 1006. The CENCHR subroutine is shown in FIGS. 20 and 21 and described below.

FIGS. 16, 17, 18, and 19 connected as shown illustrate a flowchart of the PADEC subroutine employed in operational block 1506 of the decryptor program routine of FIG. 15. It is important to note that the D-bit sequences of the incoming audio signals are randomly aligned. Consequently, the entire decryption process cannot simply be performed N times and different operations must be performed on each VTS audio signal. These operations are achieved, in accordance with an aspect of the invention, by employing the PADEC subroutine. Accordingly, the PADEC subroutine is entered via oval 1601.

Operational block 1602 causes the BIC data input port 1403 (FIG. 14) to read the data from bridge input circuit 1001 associated with the audio, control channel and audio decipherment information. The data is supplied via data link 1011 in accordance with the address supplied to bridge input circuit 1001 via operational block 1505 (FIG. 15).

Operational blocks 1603, 1604 and 1605 cause segregation of the audio data, control channel data and decipherment information, respectively. Operational block 1606 increments a D-bit counter, i.e., a state counter, for VTS channel J. The state counter is a modulo-128 counter, i.e., counts from 0 to 127 and repeats. The D-bit counter is used on a per channel basis to keep track of operations in performing the decryption.

Operational block 1607 implements a 128 way branch based on the state of the least seven significant bits of the D-bit counter.

Operational block 1608 implements a set of operations based on each of the 128 states of the D-bit state counter on a per channel basis as shown in Table 4 below. The information provided in Table 4 is subdivided into 6 columns as shown.

Column "K" is the D-bit number as described by the state of the D-bit counter in memory 1405 (FIG. 14).

Column "D-bit K Processing" describes the operation that should be performed on each of the different D-bits as shown in FIG. 12.

Column "Received Counter Contents Bookkeeping" assembles the counter contents to be utilized as plain text into the DES module 1407 (FIG. 14).

Column "Counter Encryption Request" requests encryption of the plain text counter contents.

Column "Cipher Byte Selection to Decrypt Audio" determines which cipher text block is to be used to perform audio decryption as described below.

Column "Flow Chart Node" directs the operation to one of flowchart nodes S, LR, or P.

In TABLE 4 the following are used:

LRTMP is a temporary register in memory 1405;

NXTPT is a next plain text register in memory 1405;

HAM(LRTMP) is the code correction of L bits as per TABLE 3;

PRSPT is a present plain text register in memory 1405;

ENCRQ is an encryption request flag including cipher text block [CT]1 or [CT]0; and

CTADDR is a cipher text address in memory 1405.

It is noted that during a present four (4) frame block of audio information, e.g., K=1 through 4, encryption of the plain text counter contents and the resulting cipher text generated by DES module 1407 to be stored, for example, in cipher text (CT) block 1, will be used to decrypt the next subsequent 4 frame block, e.g., K=5 through 8, of audio information. This is realizable because the cipher text is 64 bits and the audio sample is only 16 bits. Thus, the cipher text is used with four audio samples. Since only one cipher text word is needed for every four audio samples per channel the DES module is further freed-up for use with the other channels. During the next 4 frame block of audio information encryption of the plain text counter contents and resulting cipher text stored in [CT] block 0 will be used for decrypting the next block of audio information. That is to say, the cipher text blocks alternate for each 4 frame block of audio information. Moreover, since single DES module 1407 (FIG. 14) needs to be used on a per channel basis only once every 4 frames, and since the DES module performs the prescribed operation in a fraction of an audio sample period, it can be used to perform similar operations for the other VTS channels. Additionally, it is noted that DES module 1407 takes less time than one frame interval to perform the encryption operation on the plain text data. Thus, by employing common control techniques, in accordance with an aspect of the invention, the operations shown in TABLE 4 below are concurrently being performed for up to N randomly phased signals from N VTS channels.

                                      TABLE 4
    __________________________________________________________________________
                 Received
                 Counter   Counter
                                 Cipher Byte
                                           Flow
       D-bit K   Contents  Encryption
                                 Selection to
                                           Chart
    K  Processing
                 Bookkeeping
                           Request
                                 Decrypt Audio
                                           Node
    __________________________________________________________________________
    001
       RTMPO=D=L1          ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (1,[Ct]1)
    002
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    003
       LRTMP1=D=L2               CTADDR=*[Ct2]0
                                           LR
    004
       FRAMING=D+1               CTADDR=*[Ct3]0
                                           S
    005
       LRTMP2=D=L3         ENCRQ CTADDR=*[Ct0]1
                                           LR
                           (2,[Ct]0)
    006
       FRAMING=D+1               CTADDR=*[Ct1]1
                                           S
    007
       LRTMP3=D=L4               CTADDR=*[Ct2]1
                                           LR
    008
       FRAMING=D+0               CTADDR=*[Ct3]1
                                           S
    009
       LRTMP4=D=R1         ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (3,[Ct]1)
    010
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    011
       LRTMP5=D=R2               CTADDR=*[Ct2]0
                                           LR
    012
       FRAMING=D+0               CTADDR=*[Ct3]0
                                           S
    013
       LRTMP6=D=R3
                 NXTPT0 =  ENCRQ CTADDR=*[Ct0]1
                                           LR
                 HAM(LRTMP)
                           (4,[Ct]0)
    014
       PARITY=D                  CTADDR=*[Ct1]1
                                           P
    015                          CTADDR=*[Ct2]1
                                           LR
    016
       FRAMING=D+1               CTADDR=*[Ct3]1
                                           S
    017
       LRTMPO=D=L5         ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (5,[Ct]1)
    018
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    019
       LRTMP1=D=L6               CTADDR=*[Ct2]0
                                           LR
    020
       FRAMING=D+1               CTADDR=*[Ct3]0
                                           S
    021
       LRTMP2=D=L7         ENCRQ CTADDR=*[Ct0]1
                                           LR
                           (6,[Ct]0)
    022
       FRAMING=D+1               CTADDR=*[Ct1]1
                                           S
    023
       LRTMP3=D=L8               CTADDR=*[Ct2]1
                                           LR
    024
       FRAMING=D+0               CTADDR=*[Ct3]1
                                           S
    025
       LRTMP4=D=R5         ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (7,[Ct]1)
    026
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    027
       LRTMP5=D=R6               CTADDR=*[Ct2]0
                                           LR
    028
       FRAMING=D+0               CTADDR=*[Ct3]0
                                           S
    029
       LRTMP6=D=R7
                 NXTPT1 =  ENCRQ CTADDR=*[Ct0]1
                                           LR
                 HAM (LRTMP)
                           (8,[Ct]0)
    030
       PARITY=D                  CTADDR=*[Ct1]1
                                           P
    031                          CTADDR=*[Ct2]1
                                           LR
    032
       FRAMING=D+1               CTADDR=*[Ct3]1
                                           S
    033
       LRTMPO=D=L9         ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (9,[Ct]1)
    034
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    035
       LRTMP1=D=L10              CTADDR=*[Ct2]0
                                           LR
    036
       FRAMING=D+1               CTADDR=*[Ct3]0
                                           S
    037
       LRTMP2=D=L11        ENCRQ CTADDR=*[Ct0]1
                                           LR
                           (10,[Ct]0)
    038
       FRAMING=D+1               CTADDR=*[Ct1]1
                                           S
    039
       LRTMP3=D=L12              CTADDR=*[Ct2]1
                                           LR
    040
       FRAMING=D+0               CTADDR=*[Ct3]1
                                           S
    041
       LRTMP4=D=R9         ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (11,[Ct]1)
    042
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    043
       LRTMP5=D=R10              CTADDR=*[Ct2]0
                                           LR
    044
       FRAMING=D+0               CTADDR=*[Ct3]0
                                           S
    045
       LRTMP6=D=R11
                 NXTPT2 =  ENCRQ CTADDR=*[Ct0]1
                                           LR
                 HAM(LRTMP)
                           (12,[Ct]0)
    046
       PARITY=D                  CTADDR=*[Ct1]1
                                           P
    047                          CTADDR=*[Ct2]1
                                           LR
    048
       FRAMING=D+1               CTADDR=*[Ct3]1
                                           S
    049
       LRTMPO=D=L13        ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (13,[Ct]1)
    050
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    051
       LRTMP1=D=L14              CTADDR=*[Ct2]0
                                           LR
    052
       FRAMING=D+1               CTADDR=*[Ct3]0
                                           S
    053
       LRTMP2=D=L15        ENCRQ CTADDR=*[Ct0]1
                                           LR
                           (14,[Ct]0)
    054
       FRAMING=D+1               CTADDR=*[Ct1]1
                                           S
    055
       LRTMP3=D=L16              CTADDR=*[Ct2]1
                                           LR
    056
       FRAMING=D+0               CTADDR=*[Ct3]1
                                           S
    057
       LRTMP4=D=R13        ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (15,[Ct]1)
    058
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    059
       LRTMP5=D=R14              CTADDR=*[Ct2]0
                                           LR
    060
       FRAMING=D+0               CTADDR=*[Ct3]0
                                           S
    061
       LRTMP6=D=R15
                 NXTPT3 =  ENCRQ CTADDR=*[Ct0]1
                                           LR
                 HAM(LRTMP)
                           (16,[Ct]0)
    062
       PARITY=D                  CTADDR=*[Ct1]1
                                           P
    063                          CTADDR=*[Ct1]1
                                           LR
    064
       FRAMING=D+1               CTADDR=*[Ct3]1
                                           S
    065
       LRTMPO=D=L17        ENCRQ CTADDR=*[Ct0]0
                                           LR
                           (17,[Ct]1)
    066
       FRAMING=D+0               CTADDR=*[Ct1]0
                                           S
    067
       LRIMP1=D=L18              CTADDR=*[Ct2]0
                                           LR
    068
       FRAMING=D+1               CTADDR=*[Ct3]0
                                           S
    069
       LRTMP2=D=L19        ENCRQ CTADDR=*[Ct0]1
                                           LR
                           (18,[Ct]0)
    070
       FRAMING=D+1               CTADDR=*[Ct1]1
                                           S
    071
       LRTMP3=D=L20              CTADDR=*[Ct2]1
                                           LR
    072
       FRAMING=D+0               CTADDR=*[Ct3]1
                                           S
    073
       LRTMP4=D=R17        ENCRQ CTADDR=*[Ct0]0
                                           LR


(19,[Ct]1) 074 FRAMING=D+0 CTADDR=*[Ct1]0 S 075 LRTMP5=D=R18 CTADDR=*[Ct2]0 LR 076 FRAMING=D+0 CTADDR=*[Ct3]0 S 077 LRTMP6=D=R19 NXTPT4 = ENCRQ CTADDR= *[Ct0]1 LR HAM(LRTMP) (20,[Ct]0) 078 PARITY=D CTADDR=*[Ct1]1 P 079 CTADDR=*[Ct2]1 LR 080 FRAMING=D+1 CTADDR=*[Ct3]1 S 081 LRTMPO=D=L21 ENCRQ CTADDR=*[Ct0]0 LR (21,[Ct]1) 082 FRAMING=D+0 CTADDR=*[Ct1]0 S 083 LRTMP1=D=L22 CTADDR=*[Ct2]0 LR 084 FRAMING=D+1 CTADDR=*[Ct3]0 S 085 LRTMP2=D=L23 ENCRQ CTADDR=*[Ct0]1 LR (22,[Ct]0) 086 FRAMING=D+1 CTADDR=*[Ct1]1 S 087 LRTMP3=D=L24 CTADDR=*[Ct2]1 LR 088 FRAMING=D+0 CTADDR=*[Ct3]1 S 089 LRTMP4=D=R21 ENCRQ CTADDR=*[Ct0]0 LR (23,[Ct]1) 090 FRAMING=D+0 CTADDR=*[Ct1]0 S 091 LRTMP5=D=R22 CTADDR=*[Ct2]0 LR 092 FRAMING=D+0 CTADDR=*[Ct3]0 S 093 LRTMP6=D=R23 NXTPT5 = ENCRQ CTADDR=*[ Ct0]1 LR HAM(LRTMP) (24,[Ct]0) 094 PARITY=D CTADDR=*[Ct1]1 P 095 CTADDR=*[Ct2]1 LR 096 FRAMING=D+1 CTADDR=*[Ct3]1 S 097 LRTMPO=D=L25 ENCRQ CTADDR=*[Ct0]0 LR (25,[Ct]1) 098 FRAMING=D+0 CTADDR=*[Ct1]0 S 099 LRTMP1=D=L26 CTADDR=*[Ct2]0 LR 100 FRAMING=D+1 CTADDR=*[Ct3]0 S 101 LRTMP2=D=L27 ENCRQ CTADDR=*[Ct0]1 LR (26,[Ct]0) 102 FRAMING=D+1 CTADDR=*[Ct1]1 S 103 LRTMP3=D=L28 CTADDR=*[Ct2]1 LR 104 FRAMING=D+0 CTADDR=*[Ct3]1 S 105 LRTMP4=D=R25 ENCRQ CTADDR=*[Ct0]0 LR (27,[Ct]1) 106 FRAMING=D+0 CTADDR=*[Ct1]0 S 107 LRTMP5=D=R26 CTADDR=*[Ct2]0 LR 108 FRAMING=D+0 CTADDR=*[Ct3]0 S 109 LRTMP6=D=R23 NXTPT6 = ENCRQ CTADDR=*[Ct0] 1 LR HAM(LRTMP) (28,[Ct]0) 110 PARITY=D CTADDR=*[Ct1]1 P 111 CTADDR=*[Ct2]1 LR 112 FRAMING=D+1 CTADDR=*[Ct3]1 S 113 LRTMPO=D=L29 ENCRQ CTADDR=*[Ct0]0 LR (29,[Ct]1) 114 FRAMING=D+0 CTADDR=*[Ct1]0 S 115 LRTMP1=D=L30 CTADDR=*[Ct2]0 LR 116 FRAMING=D+1 CTADDR=*[Ct3]0 S 117 LRTMP2=D=L31 ENCRQ CTADDR=*[Ct0]1 LR (30,[Ct]0) 118 FRAMING=D+1 CTADDR=*[Ct1]1 S 119 LRTMP3=D=L32 CTADDR=*[Ct2]1 LR 120 FRAMING=D+0 CTADDR=*[Ct3]1 S 121 LRTMP4=D=R29 ENCRQ CTADDR=*[Ct0]0 LR (31,[Ct]1) 122 FRAMING=D+0 CTADDR=*[Ct1]0 S 123 LRTMP5=D=R30 CTADDR=*[Ct2]0 LR 124 FRAMING=D+0 CTADDR=*[Ct3]0 S 125 LRTMP6=D=R31 NXTPT6 = ENCRQ CTADDR=*[Ct0]1 LR HAM(LRTMP) (0,[Ct]0) PRSPT=NXTPT 126 PARITY=D CTADDR=*[Ct1]1 P 127 CTADDR=*[Ct2]1 LR 128 FRAMING=D+1 CTADDR=*[Ct3]1 S __________________________________________________________________________


Flow chart node S is entered as described in Table 4. Thereafter, operational block 1609 will choose the proper cipher text as shown in Table 4 to decrypt the audio information in bits A-1 through A-16 by performing an Exclusive OR function of the chosen cipher text portion and the audio sample AJ.

Conditional branch point 1610 tests to determine whether the D-bit counter state is in synchronism with the audio deciphering bits super frame (D-bit super frame). If the test result is true, there is synchronism and control is transferred to conditional branch point 1611. However, if the test result is false, operational block 1612 decrements the D-bit counter to search for D-bit superframe synchronism. Then, operational block 1613 mutes the audio by forcing bits A-1 through A-16 to be logical 0's and also sets the mute flag to a logical 1, thereby indicating that the audio has been muted to control processor 1006. Conditional branch point 1611 tests to determine whether the mute counter is equal to 0. If the test result is true, operational block 1614 sets the mute flag to a logical 0 thereby indicating that the audio is not muted. If the test result in step 1611 is false, the audio bits A-1 through A-16 are set to logical 0's and the mute flag is set to a logical 1, again indicating that the audio is muted. Control is returned to the decryptor program routine (FIG. 15) via oval 1616.

Flow chart node LR is entered as described in Table 4. Thereafter, operational block 1617 will choose the proper cipher text as shown in Table 4 to decrypt the audio information in bits A-1 through A-16 by performing and Exclusive OR function of the chosen cipher text portion and the audio samples AJ.

Conditional branch point 1618 tests to determine if the mute counter is set to 0. If the test result is true, operational block 1619 sets the mute flag to 0 indicating that the audio is not muted. If the test result in step 1618 is false, operational block 1620 sets audio bits A-1 through A-16 to logical 0's and sets the mute flag to a 1, thereby indicating that the audio is muted. Thereafter, control is returned to the decryptor program routine (FIG. 15) via oval 1621.

Flowchart node P is entered as described in Table 4. Thereafter, operational block 1622 decrypts audio bits A-1 through A-16 by performing an Exclusive OR function of the chosen cipher text portion and the audio sample AJ.

Operational block 1623 computes the modulo-2 sum over the decrypted bits A-9 through A-16 and the associated value of the D-bit.

Conditional branch point 1624 tests to determine whether the modulo-2 sum resulted in an error defined as odd parity over audio bits A-9 through A-16. If the test result is false, control is transferred to conditional branch point 1625. However, if the test result is true, operational block 1626 sets the mute counter to 15 to ensure at least 15 error free audio samples, corresponding to when the D-bit is a parity bit (a total of 240 audio samples), are received before the audio is unmuted. Operational block 1627 sets the audio bits A-1 through A-16 to logical 0's and sets the mute flag to 1, thereby indicating that the audio is muted.

Conditional branch point 1625 tests whether the mute counter equals 0. If the test result is true, operational block 1628 sets the mute flag to 0, thereby indicating that the audio is unmuted. If the test result in step 1625 is false, operational block 1629 decrements the mute counter. Thereafter, operational block 1630 sets audio bits A-1 through A=16 to logical 0 and sets the mute flag to 1, thereby indicating that the audio is muted. Then, control is returned to the decryptor program routine (FIG. 15) via oval 1631.

Thus, the PADEC routine controls operation of DEC 1002 to effect a common time shared function which is responsive to the decipherment control bits (D-bits) from each of a plurality of received audio signals for obtaining plain text data corresponding to each of the received audio signals and for generating corresponding encryption requests as set out in Table 4 above. Additionally, the PADEC routine controls DEC 1002 to controllably utilize, again on a common time shared basis, the cipher text data generated by the CENCHR routine described below for decrypting the received audio samples. As described above, the PADEC routine employs a plurality of process state counters, i.e., DBCNTRJ step 1606, for directing operations, in accordance with Table 4, for each of the received signal channels on a time shared basis.

It is noted that the common control arrangement of the invention does not merely repeat the same function N times for the N audio signals but can perform any one of a multiplicity of operations for each of the N audio signals as directed by the process state counter, i.e., D-bit counter associated with the particular audio signal. Thus, the decryptor, in accordance with the invention, decrypts simultaneously received, randomly phased audio signals. In this example, 128 operations are directed by each of the D-bit counters and each of the N channels may require a different one of those operations.

It is further noted, that although the invention is employed in this example to decrypt audio signals, it is equally applicable to any other type of data signal.

FIGS. 20 and 21 connected as shown form a flowchart of the CENCHR subroutine called in operational blocks 1515 and 1517 of the decryptor program routine shown in FIG. 15. The CENCHR subroutine is the controller for performing the plain text encryption for each of the VTS audio signals. Accordingly, the CENCHR subroutine is entered via oval 2001. Thereafter, operational block 2002 sets counter J to 1.

Conditional branch point 2003 tests whether data link J contains an encryption request according to Table 4 of operational block 1608 of the PADEC subroutine shown in FIG. 16. If the test is false, operational block 2004 sets counter J equal J+1.

Conditional branch point 2005 tests whether J>N. If the test result is false, control is returned to conditional branch point 2003. If the test result in step 2005 is true, conditional branch point 2006 tests whether the control processor 1006 requested a command to be executed by the audio decryptor. If the test result in step 2006 is false, control is returned to the decryptor program routine of FIG. 15 via oval 2007. However, if the test result in step 2006 is true, operational block 2008 reads the control processor command and causes one of four operations to be effected depending on the command which is read. The operations are read encryption mode, set encryption mode, read memory 1405, and write memory 1405, which are effected by operational blocks 2009, 2010, 2011 and 2012, respectively.

Operational block 2009 transfers the encryption mode in the ENCMODE register to register CPIO located in control processor bus interface 1409 of FIG. 14.

Operational block 2010 sets the register ENCMODE to the value in register CPIO located in control processor bus interface 1409.

Conditional branch point 2013 tests whether the decryption process is bypassed. If the condition is true, control is transferred to operational block 2014. If the test result is false, operational block 2015 transfers the decryption key information from the scratchpad memory 1405 into the DES module 1407.

Operational block 2011 sets the MEMADDR register to the value of CPIO to indicate which location in memory 1405 should be read.

Operational block 2016 reads the contents of memory 1405 as described by the address located in register MEMADDR and transfers the contents to register CPIO in control processor bus interface 1409.

Operational block 2012 writes the location of memory 1405 at the address designated by MEMADDR with the contents described by register CPIO.

Operational block 2017 transfers the contents of register MEMADDR to register CPIO to indicate to the control processor 1006 which location of memory 1405 was written.

Operational block 2014 acknowledges command completion to control processor 1006. Control is returned to the decryptor program routine via oval 2007.

Returning to conditional branch point 2003, which tests whether data link J contains an encryption request according to Table 4 of operational block 1608 of the PADEC subroutine shown in FIG. 16. If the test result in step 2003 is true, operational block 2018 clears the encryption request and proceeds through conditional branch point 2019.

Conditional branch point 2019 tests whether the encryption mode is to bypass encryption. If the test result in step 2019 is true, conditional branch point 2020 tests which cipher text block located in scratchpad memory 1405 (FIG. 14) is to be cleared to 0. If the test result in step 2020 is false, operational block 2021 clears the cipher text block 1 in scratchpad memory 1405. If the test result in step 2020 is true, operational block 2022 is entered which clears the cipher text block 0 in scratchpad memory 1405.

Returning to conditional branch point 2019, which tests whether the encryption mode is to bypass encryption. If the test result is false, operational block 2023 is entered, which transfers the plain text counter contents located in memory 1405 into the DES module 1407 (FIG. 14).

Operational block 2024 instructs the DES module 1407 to perform the cipher rounds, i.e., the encryption of the plain text.

Conditional branch point 2025 tests which cipher text block located in scratchpad memory 1405 (FIG. 14) is to be loaded with the DES module cipher text. If the condition is true, operational block 2026 is entered which transfers the cipher text from the DES module into the cipher text block 0. If the test result in step 2025 is false, operational block 2027 is entered which transfers the cipher text from the DES module into the cipher text (CT) block 1.

Then, control is returned to the decryptor program routine shown in FIG. 15 via oval 2028.

Thus, the CENCHR routine controls the operation of DEC 1002 to effect common time shared operation of DES module 1407 to generate in response to encryption requests from PADEC (Table 4) and utilizing the supplied plain text data from PADEC the corresponding cipher text data that is used to decrypt the incoming audio samples.

Audio Bridge

Details of audio bridge 1003 of FIG. 10 are shown in simplified block diagram form in FIG. 22. Audio bridge 1003 includes digital signal processor (DSP) 2201, digital signal processor (DSP) 2202, host processor 2203, program memory 2204, output register 2205, program memory 2206, output register 2207, interrupt controller 2208, timer module 2209, host processor memory 2210 and control processor interface 2211. Units 2204 through 2211 are inter-connected to host processor 2203 via bus 2212. Program memory 2204 and output register 2205 are associated with DSP 2201 while program memory 2206 and output register 2207 are associated with DSP 2202. Program memories 2204 and 2206 appear as dual port storage systems. DSPs 2201 and 2202 have read-only access to memories 2204 and 2206, respectively, for fetching instructions and program constants. Host processor 2203 has read-write access to memories 2204 and 2206 in order to down-line load the DSP programs and to modify certain of the memory locations that appear as constants. DSPs 2201 and 2202 communicate via output registers 2205 and 2207, respectively, to host processor 2203. DSP 2201 under program control can direct its output to output register 2205 or to DSP 2202. Similarly, DSP 2202 can direct its output to output register 2207 or via 1015 to audio encryptor 1004. Each of DSPs 2201 and 2202 includes RAM memory which as described below stores audio input samples AU and also processed audio output samples PAU. It is noted that two DSPs, i.e., DSP 2201 and DSP 2202, are employed in this embodiment to enhance the audio bridge throughput, i.e., speed up the audio processing. To this end, DSP 2201 processes samples represented by bits A9 through A16 while DSP 2202 processes samples represented by bits A1 through A8. Anyone of a number of digital signal processing (DSP) units known in the art may be employed in audio bridge 1003. One such DSP unit is described in several articles in The Bell System Technical Journal, Vol. 60, No. 7, Part 2, dated September 1981 and manufactured by Western Electric Company. Similarly, host processor 2203 may be any of the known microprocessors. In this embodiment a Motorola MC 6809 microprocessor unit is employed.

It is important to note that there is no fixed assignment of the VTS links to conference rooms and/or other MLCTs. Accordingly, audio bridge 1003 under program control effects, in accordance with an aspect of the invention, programmable audio mixing in the incoming audio signals from the VTS links. Additionally, it is possible to controllably reconfigure an on going conference without disrupting it. To this end, audio bridge 1003 processes the incoming audio from the rooms in the conference, in accordance with an aspect of the invention, by employing a partial sum algorithm which employs matrix multiplication to insure the appropriate audio mix is sent to the rooms in the conference. Use of the partial sum arrangement is important to obtain the desired audio mixes when more than one MLCT is used in a conference.

Audio bridge 1003 of FIG. 22 must controllably process the audio information obtained from rooms serviced by the MLCT and also the audio information from rooms serviced by one or more remote MLCTs. Since more than one MLCT may be in a conference and since MLCT's communicate to one another over one out-going data link a straight summation of the audio information cannot readily be realized. This problem of audio mixing is overcome, in accordance with an aspect of the invention, by advantageously using a partial summing process in each MLCT. To this end, the audio information from rooms serviced by a particular MLCT are summed locally and transmitted as a partial sum to the other MLCTs in the conference. The partial sums from the other MLCTs are controllably selectively combined with the locally generated partial sum to generate the appropriate audio mixes for the rooms serviced by the MLCT.

This summing is realized, in accordance with an aspect of the invention, by control processor 1006 (FIG. 39) under program control a programmable matrix operation which in this example employs two N.times.N matrices determined according to the MLCT in-links assignments and the desired audio mixes, namely, ##EQU1## Where the processed audio version PAU1 for out-link J is generated via matrices 1 from the in-link audio (AU) from the appropriate in-links. The process performed by DSP 2201 and DSP 2202 is ##EQU2## where PAU represents the processed audio information, J is the out-link, I is the in-link and AU is the in-link audio information. Constants K, I, and J are determined by control processor 1006 from the link assignments provided by processor 1006 and a noise guard algorithm provided from audio bridge 1003 host processor 2210 (FIG. 22).

The first matrix provided from (1) is called a NO-LOSS matrix and the second is called a LOSS matrix. The NO-LOSS matrix contains either 0.0 or 1.0 as elements K depending on the conference link assignments, i.e., which rooms are active, namely,

KNOLOSS[I,J]=KASSIGN[I, J], (3)

and

KLOSS[I, J]=KNOLOSS[I, J].multidot.L[I] (4)

where L[I]=-12 db except when the particular link is a MLCT in-link. Then, L[I]=1.0 or 0 db.

The noise guard algorithm described below chooses appropriate columns K from the NOLOSS matrix or the LOSS matrix depending on whether there is audio or no audio on a given in-link I. The constants K from the column chosen by control processor 1006 are provided to DSP 2201 and 2202 for multiplication with the incoming audio information AU and, therefore, generating the audio mixes as described below. This allows for the controllable insertion of loss in the audio information in those links in which no speech is present to attenuate noise.

Thus, from matrix (3) it is seen that by appropriate selection of constant K any weighted sum of the input audio samples AU can be generated for each of the processed audio output samples PAU. Consequently, the partial audio sums to be transmitted to other MLCT and also the audio mixes for each conference location are readily obtainable under program control. Additionally, from gain matrix (4) it is seen that any predetermined loss value, can be readily inserted in any of the audio input signals AU. Moreover, if desired any predetermined gain value is also readily inserted in any of the audio input signals AU. In this example, not to be construed as limiting the scope of the invention a loss of -12 db is controllably inserted as desired.

As shown in the flow charts and described below audio bridge 1003 operates under program control to generate the desired processed audio samples. To this end, the incoming audio samples are converted from mu-law PCM into linear form. The linear samples from a currently received frame are stored in a first buffer memory, e.g., ABUFA[I], while the linear samples from the last previous frame are stored in a second buffer memory, e.g., ABUFB[I]. While inputting audio samples into ABUFA[I], the audio samples in ABUFB[I] are processed via a matrix multiplication, in accordance with an aspect of the invention, to generate desired partial sum processed audio samples for each location in the conference, as well as, the appropriate partial summation of locations served by the MLCT for transmission to other MLCTs in the conference, if any. When inputting samples into ABUFB[I], the samples stored in ABUFA[I] are being processed. The processed samples are converted from linear to mu-law PCM and supplied to encryptor 1004 for further processing. FIGS. 23, 24, 25, and 26 connected as shown form a flowchart of a program stored in program memory 2204 for controlling operation of digital signal processor 2201 (FIG. 22). It is noted that the references to registers in the following flow chats are registers in the RAM memory of either DSP 2201 or DSP 2202.

Accordingly, the program routine is entered via oval 2301 Thereafter, operational block 2302 initializes the digital signal processor interface (not shown in FIG. 22).

Operational block 2303 sets counter J=1.

Operational block 2304 initializes the register ABUFA containing audio information for port J to O.

Operational block 2305 initializes the audio energy accumulator MGRD associated with port J to a constant value of -NTHSLD.

Operational block 2306 increments the counter J, i.e., sets J=J+1.

Conditional branch point 2307 tests whether counter J is greater than N. If the test result is false, control is returned to operational block 2304 and steps 2304-2307 are iterated until step 2307 yields a true result. Then, operational block 2308 sets counter SMPLCT to the value NSMPL.

Conditional branch point 2309 tests for the start of a DS-1 frame, i.e., for the DS-1 frame sync. If the test result is false, step 2309 loops until a true test result is obtained.

Then, operational block 2310 sets counter J=1.

Operational block 2311 sets counter I=1 and the audio accumulation sum register ASUM=0.

Operational block 2312 sets the audio accumulation sum to its previous value plus the audio associated with port I after multiplying by a matrix element K[I,J] located in the data memory associated with the digital signal processor 2201 of FIG. 22.

Operational block 2313 increments the counter I, i.e., sets I=I+1.

Conditional branch point 2314 test whether I>N. If the test result is false, control is returned to operational block 2312 and steps 2312, 2313 and 2314 are repeated until the test result in conditional branch point 2314 is true. When the test result in step 2314 is true, operational block 2315 is entered to receive audio information associated with port J (i.e., bits A-1 through A-8) from audio decryptor 1002 via link 1013 in FIGS. 14 and 22 and stores it in register AEVEN associated with port J.

Operational block 2316 performs a linear to mu transformation on the contents of the audio accumulation contained in ASUM previously computed in operational block 2312 and stores it in register PAODD.

Operational block 2317 sends audio information, i.e., bits A-1 through A-8 previously stored in register AEVEN in step 2315 to digital signal processor 2202.

Operational block 2318 receives audio information, i.e., bits A-9 through A-16 from audio decryptor 1002 via link 1013 in FIG. 14 and performs a mu to linear transformation and then stores the result in register ABUFB associated with port J.

Operational block 2319 sends to digital signal processor 2302 the contents of register PAODD which were computed in step 2316.

Operational block 2320 increments counter J, i.e., sets J=J+1. Thus, steps 2310 through 2320.

Conditional branch point 2321 tests whether J>N. If the test result is false, control is returned to operational block 2311 in which case steps 2311-2321 are iterated until step 2321 yields a true result. Then operational block 2322 sets counter J=1.

Operational block 2323 causes the absolute value of register ABUFA associated with port J to be added to the absolute value of register ABUFB associated with port J. The result of the addition is multiplied by a predetermined constant AVGWT. The result of the multiplication is added to the value in register NGRD associated with port J.

Operational block 2324 increments counter J, i.e., sets J=J+1.

Conditional branch point 2325 tests whether J>N. If the test result is false, control is returned to operational block 2323 and step 2323-2325 are iterated until step 2325 yields a true result.

Steps 2326-2338 are substantially identical to steps 2309-2321 except for several differences, namely, steps 2329 and 2335. In step 2329, ABUFB associated with J is utilized instead of ABUFA and in step, 2335 ABUFA associated with port J is utilized instead of ABUFB. Operational block 2339 decrements counter SMPLCT.

Conditional branch point 2340 tests if counter SMPLCT is equal to 0. If the test result is false, control is returned to conditional branch point 2309. If the test result in step 2340 is true, operational block 2341 is entered which sets counter SMPLCT to a predetermined value NSMPL.

Operational block 2342 sets counter J=1 and sets the active audio energy register AENGY=0.

Operational block 2342 causes information to be supplied to host processor 2203 indicating which ports have active audio information. In the event that a port has audio information, an associated bit in register AENGY is set to be a logical 1.

Operational block 2344 sets the audio energy accumulator NGRD associated with port J to a predetermined value -NTHSLD.

Operational block 2345 increments counter J, i.e., sets J=J+1.

Conditional branch point 2345 tests whether J>N. If the test result is false, control is returned to operational block 2343 and steps 2343-2345 are repeated until step 2345 yields a true result. Then, operational block 2346 sends the active audio register AENGY contents to the host processor 2203 via output register 2205 and link 2212. Thereafter, control is returned to conditional branch point 2309.

FIGS. 27, 28, 29 and 30 connected as shown form a flowchart of a program routine stored in program memory 2206 for controlling digital signal processor 2202. Steps 2701-2746 of the program are substantially identical to steps 2301-2346 of the program routine shown in FIGS. 23-26 and described above. The differences are that the program routine shown in FIGS. 23-26 causes digital signal processor 2201 to pass audio bits A-1 through A-8 to digital signal processor 2202 and causes audio bits A-9 through A-16 to be mixed according to steps 2315-2320 (FIGS. 23-26). On the other hand, the program routine shown in FIGS. 27-30 passes through mixed audio bits A-9 through A-16 from digital signal processor 2201 and mixes audio bits A-1 through A-8 as described in steps 2715-2720. Accordingly, the remaining steps of the program routine shown in FIGS. 27-30 will not be described in detail again.

FIG. 31 is a flowchart of a DSP control (DSPCTL) program task stored in host processor memory 2210 for operating host processor 2203 under control of a standard operating system to interact with digital signal processors 2201 and 2202.

Accordingly, the DSPCTL task program routine is entered via oval 3101. Thereafter, operational block 3102 sets counter J=1.

Operational block 3103 sets noise guard holdover counter NGHCT equal to a predetermined value HOLDVR associated with port J.

Operational block 3104 increments counter J, i.e., sets J=J+1.

Conditional branch point 3105 tests whether J>N. If the test result is false, control is returned to operational block 3103 and, thereafter, steps 3103, 3104 and 3105 are repeated until the test result is true.

Operational block 3106 places both Digital Signal Processor 2201 and Digital Signal Processor 2202 in the run state.

Oval 3107 places a call to the operating system executed by host processor 2203 to suspend the operation of program task DSPCTL until digital signal processor 2201 has sent output data to output register 2205.

Operational block 3108 calls a subroutine NGRD to perform the noise guard algorithm from audio energy samples associated with audio bits A-9 through A-16. A flowchart of the NGRD Subroutine is shown in FIG. 32 and is described below.

Oval 3109 places a call to the operating system executed by host processor 2203 to suspend the operation of the program task DSPCTL until digital signal processor 2202 has sent data to output register 2207 associated with audio energy of the incoming audio information.

Operational block 3110 calls subroutine NGRD to perform the noise guard algorithm from audio energy samples associated with audio bits A-0 through A-8 as described below.

Control is returned to oval 3107 and steps 3107-3710 are repeated continuously in an endless loop.

FIG. 32 shows a flowchart of the noise guard program subroutine (NGRD) utilized in the DSPCTL program task of FIG. 31. Accordingly, the NGRD subroutine is entered via oval 3201. Thereafter, operational block 3202 sets counter I=1.

Conditional branch point 3203 tests to determine whether audio energy is present from link I. If the test result is true, operational block 3204 sets the noise quard holdover counter associated with port I equal to the predetermined value HOLDVR. If the test result in step 3203 is false, conditional branch point 3205 tests whether the noise guard holdover counter NGHCT associated with port I is equal to 0. If the test result is false, operational block 3206 will decrement counter NGHCT associated with port I.

Operational block 3207 sets counter J=1.

Operational block 3208 transfers to digital signal processo