High security subscription television system employing real time control of subscriber's program reception4081831Abstract A high security subscription television system which includes the feature of dynamic scrambling and descrambling of cable-connected television signals in response to real-time coded control signals. The system also has the ability to precisely tune the frequency converter unit at the subscriber's site, in response to real time coded control signals provided by a computer at the central transmitting station. Various methods of scrambling and descrambling are described which use manipulation of the video signals at the baseband video level, and also at the RF level. Alternate embodiments of the descramblers include a secondary source for the reference carrier signal required for proper descrambler operation. In an ultra-stable embodiment of a subscriber's control terminal, a single crystal controlled master oscillator is used to control the frequency conversion unit, to provide a clean reference carrier signal for the descrambler unit, and to tune the control signal receiver, thereby removing the need for frequent fine tuning control adjustments, and further allowing simplified system design and fabrication. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
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% Standard Scrambled
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100 sync maximum white
75 black --
40 -- black
15 maximum white sync
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A further path routes the video signal via the line 214 to a sync separator 234, and thereafter to a lines 1-3 selector 236. These two elements are used to generate an amplitude reference pulse for insertion into the scrambled television signal for use in establishing a proper descrambler output signal level, as will be described in connection with the descrambler embodiment of FIG. 5. Referring briefly to FIG. 6A, where the inverted waveform as is shown at terminal 224 would appear, it will be noted that the sync levels which generally represent the highest transmitted power levels are not available to establish a useful AGC level. Thus the amplitude reference pulse which represents a 100% white level is generated for nominally 200 microseconds (three horizontal scan lines) during the blanking period just before the vertical sync pulse interval and is routed via a line 238 to a second input of the junction 230 where it is summed into the scrambled signal. The actuating means (not shown) for the scrambler commutator 216 may take a number of forms, including a pseudo random generator device which is strobed at some multiple of the vertical sync frequency to produce a time-chopped scrambling sequence in synchronism with the frame rate, which sequence may have an arbitrarily long repetition cycle. For present purposes the major feature required of the actuating means for the scramble commutator 216 is that the descramblers at the subscriber's control units, which do not have a prior knowledge of the encoded sequence, also have a means for responding to the same coded actuations. These means are provided as described below. Referring now to FIG. 4B, a detailed block diagram of a scrambling modulator operating at the RF level as shown. Functionally, this portion of the CTS fulfills the same purpose as the unit described in connection with FIG. 4A. As before, the scrambling method consists of the scrambling of successive fields of the television signals in a time coded way. The input video signal, as derived from a video tape reproduction system or the like, is applied via a line 210 to a conventional video processor 240, and thereafter via a line 242 to a first input of a video modulator 244. A carrier generator 252 is connected via a line 254 to a second input of the modulator 244. The output of the modulator 244, which is a standard amplitude modulated television signal (suppressed vestigial sideband) is routed via a line 246 to a first input of a combining network 248. The output of combining network 248 is applied to an output terminal 250 for subsequent application to the distribution cable. A second output of the carrier generator 252 is applied to a 180 degree phase shift network 256 and to a level control 258. The output of level control 258 is applied to a first input of a scrambler commutator 260, which performs the identical function as described in connection with the previous embodiment. The movable contact of the scrambling commutator 260 is connected via a line 262 to a second input of the combining network 248. Functionally, the combining network 248 accepts the standard amplitude modulated TV signal on its first input, and performs an algebraic summation of that waveform and the 180 degree phase shifted carrier waveform provided on its second input. The resulting output waveforms are then best described by reference to FIGS. 8A-8C. Therein, it will be noted that upon algebraic summation of an amplitude modulated waveform, the waveform of FIG. 8A, and a carrier waveform (having twice the peak amplitude of the amplitude modulated waveform, not shown to scale) wherein the carrier has been phase shifted 180.degree., as in FIG. 8B, the resulting waveform will experience a complete inversion of the amplitude modulation, as shown in FIG. 8C. By actuation of the scrambling modulator 260 in synchronism with various multiples of the field rate, a scrambled television waveform is produced having the desired characteristics and predetermined amplitude ratios as outlined in the tabulation in connection with FIG. 4A. Descrambler Description -- Baseband Video Method A basic descrambler circuit is shown in block diagram form in FIG. 5. Functionally, the descrambler reconstructs the scrambled television signals, which have been scrambled at the central transmitting station to prevent their unauthorized reception, back into standard format. The circuit as shown accomplishes this reconstruction at the baseband video level. Alternate embodiments described hereinbelow disclose how similar signal descrambling may be accomplished by operating on the scrambled signals at the RF level. Briefly, the descrambler 42A receives a scrambled input signal from the converter 32 on the line 36 and produces a standard television signal at its output on the line 44. The scrambled input signal from the converter 32 consists of an inverted video TV waveform such that a standard TV receiver cannot successfully process the sync pulses, in addition to producing a negative picture image, therefore precluding the useful reception of a TV program. The RF signal containing the inverted video waveform is applied via the line 36 to a first input of an AGC amplifier 310. Thereafter, the signal is routed to a filter 312, and via a line 314 to a limiter 316 and also to a video detector 318. The video detector 318, of conventional design, serves to amplitude envelope detect the video signal. The detected video signal is applied to a video amplifier 320 and thereafter via a line 322 to a first input of a modulator 324. A second output of the video amplifier 320 is applied via a line 326 to a peak detector 328. The output of the peak detector 328 is applied via a line 330 to a second input of the AGC amplifier 310 thereby forming a closed path automatic gain control loop. It is desirable that the video input to the modulator 324 be of substantially constant peak amplitude such that proper modulation of the reconstructed signal may be accomplished. The AGC loop assures this. The limiter 316 receives the amplified RF signal via the line 314 and performs a double-ended amplitude clipping action on the waveform. The output of limiter 316, which now contains only the RF carrier information with all amplitude information removed, is applied to a filter 332 and thereafter via a line 334, through a link 336 and via a line 338 to a second input of the modulator 324. For present purposes it may be assumed that the output of filter 332, the carrier signal only, is applied directly to the second input of modulator 324. The final process in the descrambler is accomplished in the modulator 324 which is a conventional TV amplitude modulation circuit causing the video input, from the line 322, to be amplitude modulated on the carrier input, from the line 338, in the conventional (lower sideband attenuated) manner. Two features worthy of note in this final modulation process are: Firstly, as the modulation percentage depends on the relative magnitudes of the input carrier and modulating signal waveform, these input magnitudes must be closely controlled. To this end, use is made of the 100%, white video amplitude reference pulse generated in the scrambling modulator, which was described in connection with FIG. 4A. This pulse appears in the scrambled signal as the most positively modulated signal and is used as a good amplitude reference for the closed AGC loop. The peak detection 328 is especially configured to operate on this reference pulse which may be of order 200 microseconds in duration. In addition to the clipped and filtered carrier signal of the line 334, alternate sources of the required carrier signal may be inserted into the modulator 324 by transferring the select link 336. Via an input line 340, either a crystal oscillator or a phase lock loop regenerated carrier signal may be injected into the modulator 324. An embodiment describing the phase lock loop method for regenerating a clean carrier signal will be described in connection with FIG. 10. An embodiment showing the use of a crystal oscillator for this purpose is shown in FIG. 13. Secondly, it is essential that the correct polarity of video be applied to the modulator 324 in order that the sync signals represent the highest amplitude of the reconstructed amplitude modulated TV waveform. This is assured by having an odd number of sign changes in the video amplifier chain between the input signal on line 36 and the input to the modulator 324 on the line 322. Therefore, the output of modulator 324 will consist of a standard TV waveform having the sync signals of the proper modulation percentage and other necessary characteristics such that they can be processed by a standard TV receiver. The output of modulator 324 is applied via the line 44 to the Pay/Regular selector 38 of the SCU and thereafter with no further signal processing directly to the subscriber's television receiver. To further clarify this video inversion technique, reference is made to FIGS. 6A-6D which show waveforms associated with the descrambler. FIG. 6D shows an amplitude modulated composite televisiion waveform as normally transmitted by a TV broadcasting station and the type of signal with which a standard TV receiver can most successfully operate. This waveform will appear on the output line 44. FIG. 6A shows a waveform of a composite television signal wherein the video levels have been inverted, (scrambled) as would appear on the input line 36. In this scrambled waveform, it should be noted that the sync signals rather than being the highest amplitude portion of the modulated waveform, now occupy the portion where the modulation depth is the lowest. This waveform would not successfully be processed by a standard TV receiver, as the receiver circuitry is designed to recognize the sync signals from the highest peak amplitude available. FIGS. 6B and 6C show the detected video signals corresponding to the scrambled (inverted) and the descrambled (standard) wave-forms of FIGS. 6A and 6D respectively. Alternate Descrambler -- RF Clipped Carrier Method Referring now to FIG. 7, an alternate circuit for descrambling a television signal is shown in block diagram form. Briefly, the scrambling/descrambling method used is analogous to the previously described baseband video method in that it uses inverse video modulation but the method differs in that the modulation scrambling and descrambling is accomplished at the RF level rather than at the video level. The scrambled RF signal is applied via the line 36 to the first input of an AGC amplifier 410 whose output is fed to a filter 412. The output of filter 412 is routed via a line 414 to a first input of a combining network 416, and further also via the line 414 to the input of a limiter 418, and to the input of a video detector 420. The output of the limiter 418 is applied via a series connected filter 422, phase shifter 424, level control 426 and a line 428 to a second input of the combining network 416. The output of the video detector 420 is routed to a peak detector 430. The output of the peak detector 430 is applied to a second input of the AGC amplifier 410 via a line 432. As before, the purpose of the video AGC loop is to maintain a substantially constant output RF level on the line 414 for further processing within the descrambler. The AGC loop is of conventional design, is identical to that described in connection with FIG. 5, and it should be noted that the output on line 414 is maintained within predetermined limits by processing of the video signal, especially the 100% white reference pulse previously described. In operation, the constant peak amplitude RF signal on line 414, is applied to the first input of the combining network 416. The RF signal applied to the limiter 418 is double ended amplitude clipped such that only the carrier waveform emerges, is filtered by filter 422 and routed to the phase shifter 424. The output of phase shifter 424, which introduces a 180.degree. phase shift into the carrier, is then applied via the level control 426 to the combining network 416. Thus the second input to the combining network 416 is a clean carrier reference signal, shifted 180.degree. from the waveform on line 414. The combining network 416 performs the algebraic summation function, providing on the output line 44 a standard television signal. The waveform of FIG. 8A is a simplified representation of an amplitude modulated composite television waveform wherein the video information has been inversely modulated on the carrier as described in connection with FIG. 4B. This would be representative of the scrambled waveform as applied to the input of the descrambler via the line 36 and as also would appear in amplitude form on the line 414. The waveform shown in FIG. 8B represents the output of the 180.degree. phase shift network 424, as would appear on the line 428. It is apparent that when the carrier signal of FIG. 8B is shifted 180.degree. to the carrier of signal of FIG. 8A, and both signals are combined in an algebraic addition process, there would result a signal wherein the higher amplitudes of FIG. 8A would then become the lowest amplitudes in the resulting waveform of FIG. 8C. This is exactly what is accomplished in the combining network 416 and is illustrated in simplified form by the waveform at FIG. 8C. Dynamic Descrambling--Baseband Video Method An alternate embodiment of a baseband video descrambler including the feature of dynamic descrambling is shown in block diagram form in FIG. 9. The descrambling per se is accomplished identically as the basic embodiment described in connection with FIG. 5, and the major part of the circuitry is the same as in that embodiment. As described, the scrambled input signal, as shown by the waveform of FIG. 6A, is applied via the input line 36. The descrambled output signal, as shown by the waveform of FIG. 6D, is produced on the output line 44 for connection to the subscriber's TV set via the Pay/Regular selector 38. The elements required to accomplish the dynamic descrambling merely alter the video input to the modulator 524 such that both inverted and standard video are selectively made available via a commutating switch actuated by CTS generated coded control signals. The elements numbered 510 through 538 are identically connected, with the minor exception that lines 522 and 526 are rerouted as clearly shown, as those described with the counterpart numbers 310 through 338 of FIG. 5. Operationally, the elements serve identical purposes. An output from video amplifier 520 is routed via a line 522 to the input of an inverting amplifier 550; and to a first input of a commutating switch 552; and to a peak detector 528; and lastly to the input of a vertical sync separator 554. The video amplifier 520 produces at its output a descrambled baseband video signal when the CTS is transmitting a scrambled signal, and of course, vice versa. The output of inverting amplifier 550 is fed via a line 556 to a second input of the commutating switch 552, whose movable pole is routed via a line 558 to the video input of a modulator 524. The commutating switch 552 is shown, for simplicity, as a single-pole-double-throw switch, but may be any one of a variety of high speed solid state switching means. An input line 560 accepts coded control signals as derived in the control logic processor, as will be described hereinbelow, and routes them to a first input of a descramble decoder 562, which then actuates the commutating switch 552 via the simply actuating means 564. The vertical sync separator 554 provides a second input to the descramble decoder 562 via a line 566. Functionally, the control signals on line 560 provide the real time dynamic orders required to actuate the commutating switch 552 in synchronism with the scrambling scheme being employed at the CTS at the time of transmission. Thus the CTS, which may employ a straightforward algorithm such as scrambling alternate fields; or scrambling selected M out of N fields; or scrambling fields based on a pseudo random selection process, has complete control of the system and the descrambler contains no a priori knowledge of the code in use. To achieve precise synchronism at each subscriber's location, the vertical sync pulses are recovered and used as an auxiliary input to the descrambler decoder to assure that the scramble/descrambler transition is effected during the vertical blanking interval. As with the previously described embodiment, a number of carrier reference signals may be used by insertion into the carrier select link input 540. Also, the peak detector 528 operates to control the AGC loop substantially by use of the 100% white reference pulse, but in addition has available to it the standard sync pulses during those times when an unscrambled signal is being transmitted. Alternate Descrambler -- RF Phase Lock Loop Method Referring now to FIG. 10, there is shown a preferred embodiment of the descrambler circuit. This particular embodiment includes selected features from the previous embodiments described. The descrambling of the present embodiment is accomplished at the RF level, as was the embodiment associated with FIG. 7, and includes the use of dynamic coded descrambling, similar to the technique described in connection with FIG. 9. As described, the scrambled input signal, as shown by the waveform of FIG. 8A, is applied via the input line 36. The descrambled output signal, as shown by the waveform of FIG. 8C, is produced on the output line 44 for connection to the subscriber's TV set via the Pay/Regular selector 38. The major additions of the present embodiment being the inclusion of a phase lock loop circuit for regenerating an improved phase stable carrier signal for use in the output combining process, and the inclusion of the dynamic descrambling capability previously described. The elements numbered 610 through 630 are identically connected (with the exception of the insertion of the phase lock loop 662 into the line 628) as those described with the counterpart numbers of 410 through 430 of FIG. 7. Operationally, they serve the same purposes. An output from a limiter 618 is routed to a filter 622 and thereafter via a line 650 to a first input of a phase detector 652. The output of the phase detector 652 is routed to a DC amplifier 654, whose output is fed via a line 656 to a voltage controlled oscillator (VCO) 658. The output of the VCO is routed via a line 660 to a second input of the phase detector 652 thereby forming a phase lock loop 662. Functionally, the phase lock loop 662 serves to provide a phase coherent carrier for use in the combining network 616. The output of the phase lock loop is further routed via the line 660 to the phase shifter 624 and thereafter to the level control 626. The output of the level control 626 is fed via a line 664 to a first input of a commutating switch 666 whose movable pole is routed via the line 628 to the carrier input of the combining network 616, A terminating resistor 668 is connected to a secondary input of the commutating switch 666. As distinct from the baseband video method wherein alternate polarities of video were required for remodulation as part of the descrambling process, the RF descrambler requires a carrier shifted by 180 degrees to effectively descramble a scrambled signal. For those fields transmitted using standard modulation (unscrambled) in the RF method, no carrier subtraction is required, therefore the termination is used in lieu of a particular signal. A line 670 routes the output of the video detector 620 to the input of a vertical sync separator 672 and thereafter via a line 674 to an auxiliary input of a descramble decoder 676. A source of coded control signals, as derived in the control logic processor, is connected via the input line 678 to a primary input of descramble decoder 676. Operationally, the control signals on line 678, which originate at the CTS and are processed in the control logic processor, provide the real time dynamic orders to actuate the commutating switch as previously described which synchronously descrambles the television waveform. Control Logic Processor Referring now to FIG. 11, there is shown a detailed block diagram of the control logic processor. By referring briefly to FIG. 2, it will be seen that the control logic processor 48 is positioned to operate on the output signals from the FSK control receiver 34, and to provide output control signals to the converter 32 and to the descrambler 42. In operation, the control logic processor 48 receives and processes the downstream control signals from the central transmitting station, validates the received control signals both as to address (subscriber's identification) and function (pay channel frequency tuning), and provides the positive control actuating signals for the channel selecting and descrambling portions of the SCU. The control logic processor 48 is implemented entirely by means of well known, conventional logic circuitry, the elements of which are readily available commercially. The output from the FSK control receiver 34, as described in connection with FIG. 12, is applied to the input of the control logic processor 48 via the line 46. The input signal being processed is characterized as a bisphase encoded digital bit stream in the form of TTL compatible voltage levels. This input signal is applied to a zero crossing detector 710 which reconstitutes the logic signal levels. The output of the zero crossing detector 710 is fed directly to a bisphase decoder 712 which provides both the conventional data and clock outputs. At this point it is useful to briefly describe the contents of the incoming digital signals such that the manner of their subsequent processing can be more readily understood. The digital signals consist of a serial bit stream containing an address code and a function code for each of the plurality of subscribers and a descramble code which is used by all of the subscribers being served by the central transmitting station. In a predetermined interval, the serial bit stream contains interleaved messages such that all subscribers in the network are messaged regularly in the predetermined interval. The specific format for the message to each subscriber consists of a 25 bit word. These 25 bits are divided into an 18 bit address code, a 5 bit function code, a single bit descramble code, and a single bit for parity checking. Thus, each subscriber may be unambigiously addressed via his unique 18 bit address code, 5 bit function code provides for establishing the proper first local oscillator frequency of the conversion unit within the SCU, after validation of the address bits, and the descramble bit is used to synchronously descramble the pay television programs. The biphase decoder 712 provides the biphase output data stream, and regenerated clock signal, at the bit frequency, to a number of elements within the control logic processor 48. The biphase coded data signal is applied via a line 714 to a data input node of a shift register 716, and to a first input of a serial parity generator 718, and also to a first input of a serial comparator 720. A clock output of the biphase decoder 712 is applied via a line 722 to a first input of a bit counter 724; to a missing pulse detector 726; to a second input of the serial parity generator 718; and to a control gate 727. The output of the control gate 727 is applied via a line 723 to a clock input node of the shift register 716. An address comparator 725 is shown as comprised of a unit address straps 729, a multiplier 730 and the serial comparator 720. The unit address straps 729 provides its output via a plurality of lines 728 to a plurality of first inputs of the multiplier 730. A second plurality of inputs are supplied to the multiplier 730 via a plurality of lines 732, which are provided by the bit counter 724. The output of multiplier 730 is routed directly to a second input of the serial comparator 720. The output of the missing pulse detector 726, which constitutes an unambigious signal designating that the end of a particular 18 bit word transmission has occurred, is provided via a line 734 to a number of locations within the control logic processor 48. The line 734 provides the end of transmission (EOT) signal to a second input of the bit counter 724; to a third input of the serial comparator 720; to a third input of the serial parity generator 718; and to a third input of a control AND gate 736. The serial parity generator 718 provides an output signal via a line 738 to a first input of the control AND gate 736. A first output from the bit counter 724 is supplied via a line 740 to a second input of control gate 727. A second output of the bit counter 724 is applied via a line 742 to a second input of the control AND gate 736. A fourth input to the control AND gate 736 is provided via a line 744 from an output of the serial comparator 720. Thus, when the logically derived conditions required to simultaneously enable all of the four inputs to the control AND gate 736 are present, a strobe output from control AND gate 736 is applied via a line 746 to a command latch 748. The input to the command latch is a plurality of lines via a path 750, which lines contain the function code (channel frequency tuning) and the descramble code portion of the shift register 716 contents. Upon receiving the strobe input on the line 746, the command latch 748 outputs the 5 bit address code via a plurality of lines 752 to a plurality of analog switches 754, and also to a pay program detector 756; and outputs the single descramble bit via a line 758. The pay program detector 756 provides excitation signals to a pay indicator 760 which indicates to the subscriber that a pay program is being received. The output of the analog switches 754, which is a predetermined DC voltage representative of the coded control signals containing the function code (tuning) which had originated at the CTS, is applied via a line 762 to the input 50 of the converter 32 shown in FIG. 3. The descramble signal, an on/off command bit is applied via the line 758 to the input 560 of the wider descrambler 42C (shown in FIG. 9), or to the input 678 of the RF descrambler 42D (shown in FIG. 10). Thus, the precise voltage required to perform the CATV channel selection function by controlling the frequency of VCO 118 of FIG. 3, and the dynamic descrambling signals for the baseband video descrambler of FIG. 9 (or RF descrambler of FIG. 10) are accomplished. FIG. 12 is a detailed block diagram of the FSK control receiver, shown in more general form in FIG. 2 as the system block 34. Briefly, the purpose of this section of the subscriber's control unit is to extract the coded control signals from the cable-carried signal and to provide them at baseband logic level to the control logic processor shown in FIG. 2 as the block 48. The receiver thus demodulates the logic data which had been frequency shift keyed on a VHF subcarrier at the central transmitting station. The input signal is applied via the line 30 to a tuned RF amplifier 810 which allows the passage only of the desired band of VHF frequencies which contain the biphase encoded control signals. The output of the RF amplifier 180 is routed via a line 812 to a first input of a mixer 814. The output of a fixed frequency crystal oscillator 816 is applied via a line 818 to a second input of the mixer 814. The output of the mixer 814 is applied to an IF amplifier/limiter 820, and thereafter to a discriminator 822. The output of the discriminator 822 is available via the line 46 for subsequent use in the control logic processor as will be described. An exemplary embodiment may be implemented using straightforward frequency shift keying (FSK) at the central transmitter station to represent the biphase coded control signals. As only binary information is to be handled by this portion of the system, only two discrete frequencies are transmitted, received and processed. After amplification and limiting in the IF amplifier and limiter 820, the resulting signal, which at this point is one of the two discrete frequencies representing either a logic "1" or "0", is routed to the conventional discriminator 822 which produces two DC levels corresponding to the two frequencies being processed. The output levels are compatible with a wide range of solid state logic processors, including conventional TTL logic levels. Typical frequencies of an illustrative embodiment of the FSK receiver are as follows. The center frequency of the RF amplifier 810 may be 116.5 MHz, and the amplifier may have an effective bandwidth of 500 kHz; the crystal oscillator 818 may be set to 110.5 MHz (derived from a master oscillator of 27.625 MHz which has been frequency multiplied by a factor of 4); the center frequency of the IF amplifier 820 may be set to 6 MHz. FIG. 13 is a detailed block diagram of a preferred, highly stable embodiment of the subscriber's control unit. Functionally, this embodiment carries out the same processes as the SCU described in connection with FIG. 2, and includes the elements, shown there plus the additional elements described below. Reference numerals 932 through 952 are connected identically as were the corresponding reference numerals 32-52 of FIG. 2. Briefly, the input signal from the cable is applied via the line 30, where it is processed by a converter 932 and an FSK control receiver 934. Subsequent to the complete television signal processing as described previously, the output signal is routed via a Pay/Regular selector 938 to the output terminal 40 for connection to and use by a conventional TV receiver at the subscriber's location. In the descriptions of various embodiments of the major elements of the SCU, the use of predetermined reference frequencies were specified for performing a number of functions. For example, the FSK control receiver 34 calls for a 110.5 Mhz signal for use as its local oscillator. The present embodiment shows a configuration wherein a master oscillator 960, and a plurality of related frequency multipliers 960A-960C provide the key reference frequencies required throughout the SCU. The master oscillator 960, which may be a highly stable crystal controlled oscillator, has its basic frequency chosen such that predetermined multiples of that frequency provide a set of harmonically related frequencies of the uses outlined. Specifically, a basic master oscillator frequency 27.625 of Mhz may be multiplied by a factor of two in multiplier 960A and routed to line 152 (of FIG. 3) of converter 932, thereby providing a carrier reference frequency of 55.25 Mhz to the converter 932 and establishing the desired output frequency of the converter 932 for compatibility with VHF broadcast channel two. A second multiplication by two is done in multiplier 960B and applied via the line 540 (of FIG. 9) to the descrambler 942, the preferred embodiment of the RF level dynamically descrambled unit, to provide a precise, stable reference carrier source also at 55.25 Mhz. A third multiplier 960C provides frequency multiplication by a factor of four to yield a signal at 110.5 Mhz which is applied via the line 818 (of FIG. 12) thereby providing the local oscillator signal for FSK control receiver 934. The particular frequencies cited represent one successful configuration for implementing a SCU, obviously other combinations are also possible. The resulting SCU is characterized by a high degree of stability, reducing the need for frequent adjustments both by subscriber's and at the central transmitting station. Also, the RF descrambling method which requires a high degree of phase coherence of its carrier signal for proper stable combining operation is greatly enhanced when implemented using the above SCU embodiment. Although the invention has been described in terms of selected preferred embodiments, the invention should not be deemed limited thereto, since other embodiments and modifications will readily occur to one skilled in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications as fall within the true spirit and scope of the invention.
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