Apparatus for performing frequency conversion in a communication system5521938Abstract An efficient apparatus for performing frequency conversion from a final IF frequency to a baseband frequency is described. A counter (401) generates two logical signals G1 (402) and G2 (403) which are passed to an exclusive-OR gate (404) and a multiplexer (406). When a control signal (411) is deasserted, multiplexer (406) passes signal G1 to I1 and signal G2 to I2; when control signal (411) is asserted, multiplexer (406) passes binary signal G1 to I2 (410) and signal G2 to I1 (407). Similarly, multiplexer (405) swaps its input real and imaginary samples when the output of exclusive-OR gate (404) is asserted; otherwise, it performs no operation on its input samples. Signals I1 (407) and I2 (410) are used to control arithmetic inverters (408) and (409) respectively. When the controlling signal for either inverter is asserted, the inverter performs arithmetic inversion, otherwise it performs no operation. Claims What we claim is: Description FIELD OF THE INVENTION
TABLE 1
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Multiplexer
G1 G2 (405) I1 I2
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0 0 0 1 1
0 1 X 1 -1
1 1 0 -1 -1
1 0 X -1 1
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TABLE 1 describes the truth table for operation of the frequency converter of FIG. 4 in the downconvert mode of operation.
TABLE 2
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Multiplexer
G1 G2 (405) I1 I2
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0 0 0 1 1
0 1 X -1 1
1 1 0 -1 -1
1 0 X 1 -1
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TABLE 2 describes the truth table for operation of the frequency converter of FIG. 4 in the upconvert mode of operation. In TABLE 1 and TABLE 2, an `X` indicates that multiplexer (405) swaps the real and imaginary components of the complex signal I+jQ formed at the output of the delay element (200) and Hilbert filter (201). Delay element (200) and Hilbert filter (201) in combination form a Hilbert filter configuration. The state of the inverters (408) and (409) is indicated by the sign of columns I1 and I2. In downconvert mode, it can be seen that the resulting baseband signal (412) follows the sequence {I+jQ, Q-jI, -I-jQ, -Q+jI, I+jQ, . . . }. It will be appreciated that, as discussed above, since the complex-equivalent frequency downconversion sequence generated by e.sup.-jk.pi./2 is {1+j0, 0-j1, -1+j0, 0+j1, 1+j0, . . . }, and since multiplication of I+jQ by that sequence generates the sequence {I+jQ, Q-jI, -I-jQ, -Q+jI, I+jQ, . . . }, the output of the circuit of FIG. 4 performs frequency downconversion by a normalized frequency of 0.25 as required by the general method of FIG. 2 when f.sub.s =4f.sub.c. Likewise, in upconverter mode, as described by the truth table, TABLE 2, the output sequence generated by the circuit is {I+jQ, -Q+jI, -I-jQ, Q-jI, I+jQ, . . . }. Since this is equivalent to multiplication by the sequence e.sup.+jk.pi./2, the circuit is performing frequency upconversion by a normalized frequency of 0.25. Clearly, elements (100, 102, 200, 201) would generally not precede the upconverter mode of operation since they are required solely for frequency downconversion. Rather, the complex signal entering the multiplexer (405) would be the output of a complex modulator or spreader and the output (412) would feed a filter and transmit amplifier. The remainder of the circuit is identical, however, so the upconverter form is not explicitly shown. It will be appreciated that the switches and inverters shown in FIG. 4 may be implemented as either digital or analog discrete-time structures depending on whether a digital implementation is used, or a discrete-time analog implementation, such as a switch-capacitor design, is employed. In the digital case, the switches and inverters would be formed from digital multiplexers and two's-complement inverters; in the analog case, operational amplifier circuits would be used. Note also that the Gray counter could be replaced with a binary counter or any other 4-state sequential machine. Also, any desired oversampling rate for the complex baseband symbols in a digital communications receiver observable at (411) may be achieved by setting the final IF frequency f.sub.c to be equal to the desired oversampling rate. The relationship between f.sub.c and f.sub.s is as before. The frequency converter of FIG. 4 may be modified to also perform DS-SS despreading as shown in FIG. 5. In FIG. 5, A/D converter (102), delay (200), and Hilbert filter (201) follow the scheme outlined in FIG. 2, with the received passband signal now centered at f.sub.c =4/T.sub.c where T.sub.c is the chip interval. Starting from a clock (500) operating at frequency f.sub.clk =8f.sub.c, two dividers (501, 503) generate a chip-rate clock signal suitable for clocking the short and long PN generators (504, 505, 506). The state variable outputs G1 and G2 (508, 509) of a 4-state Gray counter (507) clocked at frequency 4f.sub.c are then passed along with the PN generator outputs (504, 505, 506) to a decoder (510) which controls the function of the accumulators S1 and S2 (514, 516) via signals I1 and I2 (511, 512). If I1 or I2 are not asserted, the corresponding accumulator S1 or S2 adds the signal sample argument provided by multiplexer (515) to its respective accumulated value, otherwise the argument is subtracted from the accumulated value. At the same time, clock signal (500) is divided by two and passed to A/D converter (102) as the conversion clock. Clock signal (500) is also fed directly to a multiplexer (515). When clock signal (500) (also labeled signal SW (513) in the figure) is asserted, multiplexer (515) swaps the in-phase and quadrature components of the complex signal arguments generated by the delay and Hilbert filter (200, 201), otherwise the complex signal sample passes directly into the accumulators S1 and S2 (514, 516). For each complex signal sample emerging from the delay and Hilbert filter (200, 201), therefore, two samples are either positively or negatively accumulated by accumulators S1 and S2 (514, 516) per change of state of the Gray counter (507). Equivalently, eight samples are accumulated per change of PN generator output. The contents of the accumulators are then corrected for channel phase rotation (311, 312) and quantized (313) as in FIG. 3. The operation of the block diagram may be better understood by reference to TABLE 3, which also defines the logic required in the decoder (510).
TABLE 3
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LPN LPN
.sym.
.sym. PN* CVT PN .times. CVT
SPN-I
SPN-Q
G1
G2
Re{ }
Im{ }
Re{ }
Im{ }
Re{ }
Im{ }
I1(0)
I1(1)
I2(0)
I2(1)
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0 0 0 0 1 -1 1 0 1 -1 1 1 1 -1
0 1 0 0 1 1 1 0 1 1 1 -1 1 1
1 0 0 0 -1 -1 1 0 -1 -1 -1 1 -1 -1
1 1 0 0 -1 1 1 0 -1 1 -1 -1 -1 1
0 0 0 1 1 -1 0 -1 -1 -1 -1 1 -1 -1
0 1 0 1 1 1 0 -1 1 -1 1 1 1 -1
1 0 0 1 -1 -1 0 -1 -1 1 -1 -1 -1 1
1 1 0 1 -1 1 0 -1 1 1 1 -1 1 1
0 0 1 1 1 -1 -1 0 -1 1 -1 -1 -1 1
0 1 1 1 1 1 -1 0 -1 -1 -1 1 -1 -1
1 0 1 1 -1 -1 -1 0 1 1 1 -1 1 1
1 1 1 1 -1 1 -1 0 1 -1 1 1 1 -1
0 0 1 0 1 -1 0 1 1 1 1 -1 1 1
0 1 1 0 1 1 0 1 -1 1 -1 -1 -1 1
1 0 1 0 -1 -1 0 1 1 -1 1 1 1 -1
1 1 1 0 -1 1 0 1 -1 -1 -1 1 -1 -1
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The first two columns of the table show the possible states of the exclusive-OR'ed short and long PN sequences, while the columns titled "G1" and "G2" indicate the Gray counter (507) output states (508, 509). The next column--marked "PN*"--shows the real and imaginary parts of the complex conjugate of the original quadriphase spreading signal, while the column entitled "CVT" indicates the complex multiplier required to implement the simplified frequency conversion scheme described in FIG. 4 and which is controlled by the Gray counter output. Column "PN*xCVT" indicates the resulting complex arithmetic product of columns "PN*" and "CVT". This column provides the required values of signals I1 and I2 (511, 512) during consecutive period of the clock signal SW (513). In TABLE 3, the value of I1 during the first clock period is indicated as "I1(0)" while that for the second period is indicated as "I1(1)". Signal I2 is similarly treated. Also, I1 and I2 are listed in terms of the arithmetic function implemented by the accumulator under their respective control, although they are of course logical signals derivable from TABLE 3 through the mapping {0,1}<->{1,-1}. As an example, consider the configuration of PN sequences and Gray counter states G1 and G2 indicated by the first row of TABLE 3. Under this configuration of PN generator and Gray counter states, accumulator S1 first adds to its internal accumulated value the real component of the sample at the delay/Hilbert filter output (200, 201) during the first period of clock signal SW (513), and then adds the imaginary component of the delay/Hilbert filter during the second period of SW. At the same time, accumulator S2 first adds the imaginary part of the signal sample at the delay/Hilbert filter output, then subtracts the real part, during the following period of SW. Clearly, the block diagram of FIG. 5 substantially simplifies that of FIG. 3 by eliminating frequency converter (300), one of the A/D converters (301), and much of the complex conjugator (308) complex multiplier (309), and accumulator (310). It will be readily appreciated by one skilled in the art that the block diagram of FIG. 5 can be easily modified for biphase spreading by simply removing one of the short PN generators (504) or (505) as an input to the decoder, and slightly modifying TABLE 3. FIG. 6 shows an efficient implementation for a combined frequency upconverter and quadriphase spreader to be used on the transmit side of a DS-SS radio where the underlying modulation consists of antipodal samples (such as those generated by BPSK at the symbol rate and M-ary orthogonal signalling at the orthogonal symbol chip rate). In FIG. 6, a clock (600) running at frequency f.sub.s =4f.sub.c feeds directly to a Gray counter (606) and, via a divide by four operation, to the quadriphase spreading sequence generators (602, 603, 604). The biphase modulated data sample M (613), the Gray counter state (represented by state variables G1 (607) and G2 (608)), and the spreading sequences are then passed to a decoder (609) which generates two signals K1 (610) and K2 (611) which represent the quadriphase spread transmit signal. These are then converted to passband frequency after conversion by a 1-bit D/A converter (612). The operation of the block diagram and the logical function implemented by the decoder block (609) may be more easily understood with reference to the truth table in TABLE 4.
TABLE 4
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LPN LPN Logical
.sym.
.sym. PN CVT PN .times. CVT
PN .times. CVT
SPN-I
SPN-Q
G1
G2
Re{ }
Im{ }
Re{ }
Im{ }
Re{ }
Im{ }
Re{ }
Im{ }
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0 0 0 0 1 1 1 0 1 1 0 0
0 1 0 0 1 -1 1 0 1 -1 0 1
1 0 0 0 -1 1 1 0 -1 1 1 0
1 1 0 0 -1 -1 1 0 -1 -1 1 1
0 0 0 1 1 1 0 1 -1 1 1 0
0 1 0 1 1 -1 0 1 1 1 0 0
1 0 0 1 -1 1 0 1 -1 -1 1 1
1 1 0 1 -1 -1 0 1 1 -1 0 1
0 0 1 1 1 1 -1 0 -1 -1 1 1
0 1 1 1 1 -1 -1 0 -1 1 1 0
1 0 1 1 -1 1 -1 0 1 -1 0 1
1 1 1 1 -1 -1 -1 0 1 1 0 0
0 0 1 0 1 1 0 -1 1 -1 0 1
0 1 1 0 1 -1 0 -1 -1 -1 1 1
1 0 1 0 -1 1 0 -1 1 1 0 0
1 1 1 0 -1 -1 0 -1 -1 1 1 0
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The first two columns represent the exclusive-OR of the long PN sequence with each short PN sequence, while the columns labeled "G1" and "G2" show the states (607, 608) of the Gray counter (606). The column titled "PN" shows the real and imaginary arithmetic signals corresponding to the first two columns, while column "CVT" shows the complex frequency upconversion sequence derived from the Gray counter state. Column "PNxCVT" lists the result of multiplying the complex PN spreading sequnce with the upconversion sequence, with column "Logical PNxCVT" showing the logical equivalent under the mapping {0,1}<->{1,-1}. Signals K1 (610) and K2 (611) are finally generated by exclusive-ORing the real and imaginary parts respectively of column "Logical PNxCVT" with the modulator signal M (614). The decoder block (609) therefore implements the logical functions required to exclusive-OR the long PN and short PN sequences, generate the "Logical PNxCVT" signals from the resulting composite PN sequence and Gray counter states G1 and G2 (607, 608). One skilled in the art will appreciate that these logical functions may be reduced to a minimal logical form by use of simple techniques such as Karnaugh mapping. It will also be appreciated that the invention may be extended to include the case of biphase spreading by eliminating one of the PN generators. While the invention has been particularly shown and described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
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