Remote control security system5604488Abstract A remote control keyless security system for remotely controlling the locking and unlocking control functions of a lock mounted on a vehicle or the like. A receiver is mounted on a vehicle proximate to the lock to be controlled. A transmitter is located remote from the receiver and includes a plurality of selectively actuatable switches each representative of a control function to be performed by the lock and circuitry responsive to actuation of one of the switches for transmitting a digital signal including a first portion having a multi-bit security code uniquely identifying the transmitter from that of a plurality of similar transmitters, a multi-bit sequence control code adapted to be sequentially changed in response to each actuation of a switch and a multi-bit function code identifying one of a plurality of control functions to be performed by the lock. The transmitter changes the sequence control code after each operation with the change being dependent upon information contained in the security code identifying the transmitter. The receiver stores a multi-bit receiver security code identifying a specific transmitter from which the receiver may validly receive a digital signal. The received security code is compared with the stored receiver security code to determine whether the security codes match. The receiver also stores a multi-bit sequence control code. Claims Having described the invention, the following is claimed: Description FIELD OF THE INVENTION
TABLE A
______________________________________
SEQUENCE CONTROL CODE METHOD OF VARIATION
Security Code: Axxxxxxx Bxxxxxxx Cxxxxxxx Dxxxxxxx
ABCD
______________________________________
0000 Increment by
1
0001 3
0010 5
0011 7
0100 9
0101 11
0110 13
0111 15
1000 Decrement by
1
1001 3
1010 5
1011 7
1100 9
1101 11
1110 13
1111 15
______________________________________
As shown in Table A, the security code SC is comprised of four eight bit bytes. The most significant bits of these bytes may respectively be referred to as bits A, B, C and D and which are arranged in the lefthand column under the title ABCD. Sixteen variations of the digital value of this four bit number are represented in Table A, each providing a different algorithm for changing the present sequence control code to the next digital value of the sequence control code. For example, if the bits ABCD have a digital value of 0010, then the new sequence control code is determined by taking the old or present sequence control code and incrementing it by five. Similarly, if the digital value of the word ABCD in Table A is 0101, then the sequence control code is incremented by eleven to obtain the new digital value of the sequence control code. It is noted that the last eight algorithms in this Table provide for a decrement in the value of the sequence control code. Continuing now with the programmed operation of the microcomputer, it is seen that in step 224, the transmitter microcomputer calculates the checksum code by examining the bits in the security code, the sequence control code and the function code. A binary addition is performed on these eight bytes in order to calculate the checksum code. In accordance with step 226, the calculated checksum code is then stored in the transmitter checksum code register 46 prior to assembling the various bytes for transmission in the digital signal S. Before the bytes of the digital signal S are transmitted by the transmitter T, the bits in each of the bytes forming the security code SC, the sequence control code SSC and the function code are scrambled in accordance with one of a plurality of scrambling algorithms as set forth in Table B below.
TABLE B
______________________________________
KEY TO SCRAMBLING METHOD
CHECKSUM
CODE SCRAMBLING METHOD
______________________________________
0000 xxxx 1. XOR with SCC-1 - Shift Left
1 & Invert
0001 xxxx 2. XOR with SCC-1 - Shift Left
1
0010 xxxx 3. XOR with SCC-1 - Shift Left
2 & Invert
0011 xxxx 4. XOR with SCC-1 - Shift Left
2
0100 xxxx 5. XOR with SCC-1 - Shift Left
3 & Invert
0101 xxxx 6. XOR with SCC-1 - Shift Left
3
0110 xxxx 7. XOR with SCC-1 - Shift Left
4 & Invert
0111 xxxx 8. XOR with SCC-1 - Shift Left
4
1000 xxxx 9. XOR with SCC-1 - Shift Right
1 & Invert
1001 xxxx 10. XOR with SCC-1 - Shift Right
1
1010 xxxx 11. XOR with SCC-1 - Shift Right
2 & Invert
1011 xxxx 12. XOR with SCC-1 - Shift Right
2
1100 xxxx 13. XOR with SCC-1 - Shift Right
3 & Invert
1101 xxxx 14. XOR with SCC-1 - Shift Right
3
1110 xxxx 15. XOR with SCC-1 - Shift Right
4 & Invert
1111 xxxx 16. XOR with SCC-1 - Shift Right
4
______________________________________
With reference to Table B, it is seen that the scrambling algorithm employed is determined by examining the four most significant bits of the checksum code. The term SCC-1 refers to the first byte of the sequence control code SCC. In this Table, it is seen that it is possible to have as many as sixteen different methods of scrambling which adds to the degree of difficulty in attempting to analyze a captured signal as by a thief or the like. Thus, for the moment, assume a checksum code of 00110000. An examination of the four most significant bits indicates that the scrambling algorithm employed is algorithm No. 4 which directs that each byte of the data to be transmitted (with the exception of the checksum code) be combined in an exclusive OR manner with the first byte SCC-1 of the sequence control code. That combination is then shifted left by two places without an inversion taking place. Similar calculations are shown for other combinations in Table B. The algorithms, as set forth in Table B, are stored in the transmitter's microcomputer memory, such as in ROM in a manner well known in the art. In step 228 the programmed microcomputer selects the scrambling method to be employed by using the four most significant bits of the checksum code (represented at 230) to address Table B, represented at 232, in order to fetch one of the sixteen scrambling algorithms to be used. The bits within the data bytes, with the exception of the checksum code, are then scrambled in accordance with the selected scrambling algorithm in step 234 with the scrambled data then being stored in accordance with step in registers 40, 42 and 44. The eight data bytes to be transmitted include four bytes of security code, three bytes of sequence control code and one byte of function code. In addition to scrambling these bytes as discussed above with respect to steps 228, 230, 232 and 234, the scrambled bytes may be transmitted in an order other than that as depicted in FIG. 2. The checksum byte is always in the same position. In the example given herein, the checksum byte is in the byte 1 position of the nine bytes following the wake up and initiation bits. The remaining eight data bytes are transmitted in one of sixteen different transmission orders as set forth in Table C below.
TABLE C
______________________________________
CHECKSUM CODE KEY TO OUTPUT ORDER
______________________________________
xxxx 0000 Output order 1
xxxx 0001 2
xxxx 0010 3
xxxx 0011 4
xxxx 0100 5
xxxx 0101 6
xxxx 0110 7
xxxx 0111 8
xxxx 1000 9
xxxx 1001 10
xxxx 1010 11
xxxx 1011 12
xxxx 1100 13
xxxx 1101 14
xxxx 1110 15
xxxx 1111 16
______________________________________
As is seen from examining Table C, the selection of one of the sixteen output orders is controlled by the four least significant bits of the checksum code. Thus, if the four least significant bits of the checksum code are 0111, then the order of transmitting the data bytes will be output order No. 8 out of the potential output orders one through sixteen. The exact order of transmitting the data is not presented herein as various combinations may used for any one of the possible sixteen orders. For example, output order No. 4 may take the following sequence: SCC1, SC1, SC2, SC3, SC4, function code, SCC2 and SCC3 (it being understood that SC1 stands for security code byte one, etc., whereas SCC1 stands for sequence control code byte 1, etc.). Similarly, output order No. 6 (0101) may require that the order be as follows: SC1, SCC1, function code, SC3, SCC2, SC2, SCC3 and SC4. Similarly, output order No. 8 (checksum code xxxx0111) may require the following transmission order: function code, SC3, SCC2, SC1, SCC3, SC4, SCC1 and SC2. Table C is contained in a look-up memory in the transmitter's microcomputer in a known manner. In step 238, the transmitter's microcomputer selects the order in which to output the data bytes described hereinabove. To do so, the microcomputer examines the four least significant bits for the checksum codes stored in register 46, and uses those bits to access Table C containing the order information. The data to be transmitted is then re-ordered according to the order information read from look-up Table C. Data is then transmitted in the new order. The transmission is performed in step 244, wherein the wake up and initiation bits are initially transmitted, followed by the checksum byte and the eight data bytes (organized in the new order) representing the security code, the sequence control code and the function code. The transmitter is then powered down to await a switch closure commanding another transmission of a digital signal. Reference is now made to FIG. 4 which presents a flow chart showing the manner in which the microcomputer in the receiver R is programmed to accomplish various functions to be described herein. Initially, in accordance with step 300 the receiver is in a power-down standby condition awaiting reception of a digital signal S from a transmitter, such as transmitter T. When such a signal is received, the wake-up bit will activate the wake up signal detector 62 and, as represented in step 302, will cause the wake-up circuit 64 to power up and provide power to the microcomputer 80 within the receiver. In step 304, following the microcomputer's usual initiation steps, the microcomputer responds to the start or initiation portion of the digital signal to read the incoming digital signal and store same in the temporary registers in the microcomputer. As stated above, the incoming digital signal is scrambled and the data bytes are out of order with the exception of the checksum code. This code is always in the same place. In the example being described it is in byte position one of the nine bytes that follow the initiation and wake up bits. The checksum code byte is stored in the checksum code register 110 at the receiver R. In accordance with step 306, the four least significant bits of the checksum code stored in the receiver register 110 are examined to determine which of a plurality of sixteen transmission orders was employed in transmitting the eight data bytes to the receiver. In step 310 the four least significant bits of the checksum code are used to access a look-up table (indicated at step 308) in the receiver's microcomputer memory. This table is the same Table C discussed hereinbefore. Thus, for example, if the four least significant bits of the checksum code are 0101, order No. 6 will be retrieved from Table C. That order may have the data bytes arranged as follows: SC1, SCC1, function code, SC3, SCC2, SC2, SCC3 and SC4. Employing this information from the look-up table in step 310, the data bytes are now placed in the correct order and stored in appropriate temporary memory registers in the receiver's microcomputer. In step 312, the receiver's microcomputer examines the four most significant bits of the checksum code stored in the microcomputer's register 110. From the previous discussion of Table B it will be recalled that the four most significant bits of the checksum code determine which one of sixteen scrambling algorithms was employed at the transmitter to scramble the eight data bytes. Similarly, the four most significant bits of the checksum code received and stored in the checksum code register 110 at the receiver R are used to choose a complementary descrambling method for restoring the data bytes to their original form. Consequently, the inverse of Table B is stored in a look-up table B' in the receiver's microcomputer, such as in ROM. This Table B' is like Table B, except that the stored instructions accomplish the de-scrambling of the bytes scrambled according to Table B. The microcomputer examines the four most significant bits of the checksum code in step 312 and then obtains from Table B', in accordance with step 314, the correct de-scrambling method for purposes of performing a reverse scrambling operation in accordance with step 316. Reference is now made to Table B' produced below.
TABLE B'
______________________________________
Key to De-scrambling Method
Checksum
Code De-scrambling Method
______________________________________
0000XXXX 1. Invert -
Shift Right
1 - XOR with SCC-1
0001XXXX 2. Shift Right
1 - XOR with SCC-1
0010XXXX 3. Invert -
Shift Right
2 - XOR with SCC-1
0011XXXX 4. Shift Right
2 - XOR with SCC-1
0100XXXX 5. Invert -
Shift Right
3 - XOR with SCC-1
0101XXXX 6. Shift Right
3 - XOR with SCC-1
0110XXXX 7. Invert -
Shift Right
4 - XOR with SCC-1
0111XXXX 8. Shift Right
4 - XOR with SCC-1
1000XXXX 9. Invert -
Shift Left
1 - XOR with SCC-1
1001XXXX 10. Shift Left
1 - XOR with SCC-1
1010XXXX 11. Invert -
Shift Left
2 - XOR with SCC-1
1011XXXX 12. Shift Left
2 - XOR with SCC-1
1100XXXX 13. Invert -
Shift Left
3 - XOR with SCC-1
1101XXXX 14. Shift Left
3 - XOR with SCC-1
1110XXXX 15. Invert -
Shift Left
4 - XOR with SCC-1
1111XXXX 16. Shift Left
4 - XOR with SCC-1
______________________________________
For example, if the checksum code for the four most significant bits is 0111, then it is known that the data that has been received was scrambled at the transmitter by performing an exclusive OR for each byte in the digital code with the first byte SCC-1 in the sequence control code which is then shifted left by four places with no inversion. Performing the opposite or reverse operation, each bit will be shifted right four places and then each byte will be exclusively ORed with byte SCC-1 (except SCC-1 and then placed in the temporary register at the receiver's microcomputer pursuant to step 318. In step 320, the checksum of the true data is calculated. In step 322, the resulting checksum is compared with the received checksum code being retained in register 100. If the calculated and received checksum codes match, then the program proceeds to step 324 discussed below. If a match is not obtained then this indicates that an invalid digital signal was received and a determination is made as to whether or not the power down conditions have been satisfied in step 326. If the microcomputer is finished looking for a digital signal (e.g., if more than a specified minimum "awake" interval has elapsed since power-up), then the conditions are satisfied to power down and the microcomputer can be placed in a standby condition to thereby return to step 300 and await sensing of a new digital signal. If the power down conditions are not satisfied, as in the case where the microcomputer is not finished looking for a digital signal (e.g., the minimum "awake" interval has not yet elapsed), then the computer will return to step 304 and then continue to read and store incoming signals and repeat steps 306 through 322. If the calculated and received checksum codes match in step 322, then, in step 324, the security code in register 100 is read. In decision step 328 the security code in register 100 is compared with the security code of the received signal to determine whether authorized security code A (identifying a first acceptable transmitter) matches the received security code. If a match is not obtained, then authorized security code B (identifying a second acceptable transmitter) is retrieved (step 330) and compared with the received code (step 332). If a match is not found here, either, the microcomputer again jumps to step 326 to determine whether the power down conditions are satisfied. Returning now to step 328, if the security code A in register 100 matches the received security code, then the program advances to step 334 (FIG. 4B) wherein the appropriate security code A is read from register 100 for purposes of updating the sequence control code. In step 336, the appropriate sequence control code A is read from register 102. This is the old sequence control code and the next sequence control code is calculated by incrementing (or decrementing) the old sequence control code in accordance with instructions retrieved from Table A (indicated at 338 in FIG. 4B). Table A is accessed in accordance with a four bit nibble formed by assembling together the most significant bits in each of the four bytes in the security code read from register 100 in step 334. The look-up Table A responds with the correct increment/decrement algorithm from the Table. The new sequence control code is calculated at step 340. For example, if the most significant bits of the four bytes in the security code read from register 100 combine to form the nibble 0011, then the next sequence control code is calculated by incrementing the old code by seven. Also, if the digital value of the present or old sequence control code at byte 3 (SCC-3) is 00000001 (decimal 1) then the next valid byte 3 in the series will be 00001000 (decimal 8). For a series of eight sequence control codes, the foregoing will be followed by 00001111 (decimal 15), 0010110 (decimal 22), 00011101 (decimal 29), 00100100 (decimal 36), 00101011 (decimal 43), 00110010 (decimal 50) and 00111001 (decimal 57). In this sequence there have been N sequence control codes, wherein N=8. Having calculated the next eight sequence control codes, each calculated sequence control code, in step 342, is compared with the sequence control code embedded in the received digital signal S in order to determine whether the two match. If the received sequence control code matches any of the eight newly calculated sequence control codes, then the program operation branches to step 344, during which the sequence control code is updated to reflect the received sequence control code and written into the appropriate sequence control register 102 or 106. The matching of the sequence control codes provides the required confirmation that a valid digital signal S has been received by the receiver. In step 346, the microcomputer finally performs the requested function of either locking the vehicle door, or unlocking the vehicle door, or opening the trunk lid in dependence upon the function represented by the function code stored in register 108 at the receiver. Once the requested function has been performed, a decision is made at step 348 as to whether the power down conditions have been satisfied. If so, the microcomputer steps to a power-down standby condition awaiting reception of a new digital signal from a transmitter. On the other hand, if the power-down conditions are not satisfied, the microcomputer will jump to step 304 to thus continue to read and store incoming signals. Step 342 may be considered as an option 1 step. In addition to step 342 an option 2 step may be employed in the event that the received sequence control code does not match with one of the N calculated sequence control codes from step 340. Whether or not an option 2 step is employed is determined and implemented when the receiver is programmed. If the option 2 step is employed then, whenever step 342 determines that no match was found between the received sequence code and any one of the N calculated sequence control codes, a decision is made to go to step 350 (option 2 step) if option 1 (step 342) was not selected to the exclusion of step 342. Otherwise, the microcomputer jumps to step 348 to determine whether the power down conditions have been satisfied, as previously discussed. If step 352 results in a negative decision, the microcomputer advances to step 350. In step 350 (option 2 step) the microcomputer determines if the function code is "LOCK" meaning that the function requested is to lock the vehicle's doors. If so and if the received sequence control code is of a value greater than any of the N calculated new sequence control codes (from step 340), then the received signal is considered a validly received digital signal. In step 344 the sequence control code is updated with the sequence control code of the received signal. If either (a) the command was not a "LOCK" command or (b) the received sequence control code is not higher than the calculated next step, then the received signal is not considered valid and therefore the requested output function is not performed and the microcomputer commands that the system be powered down. It is possible for the transmitter and receiver to become out of synchronism as a result of the transmitter being activated outside the range of the system, or when within range, random noise prevents correct transmission of a signal to the receiver. Whenever the operator realizes that the receiver might be out of synchronism, all the operator is required to do (when option 2 is used) is activate the LOCK switch 12 on the transmitter and the system will become re-synchronized. Thus, whenever the system is out of synchronism, the transmitted sequence control code will always be higher than the receiver's stored sequence control code and higher than any of the N calculated new sequence control codes (from step 340). In step 350, as discussed above, the received signal will be considered valid and in step 344 the sequence control code is updated with the sequence control code of the received signal. The system is now re-synchronized. Therefore, any would-be thief who has captured and recorded a previously transmitted digital signal containing a LOCK command will not be able to re-synchronize the system since his recorded sequence control code would be lower than, or at best equal to, the current sequence control code in the receiver. The initial synchronization of the system takes place during the programming of the securing code as described in my previous U.S. Pat. No. 4,881,148. The procedure requires that a hardwired input (programming pin) in the receiver be grounded and then any of the switches 12, 14, or 16 on the transmitter be actuated. This step causes the security code and the current sequence control code of the transmitter to be received and then stored in the EEPROM memory of the receiver. It is to be noted that the checksum code does more than provide the key to the scrambling and data arrangement order methods. This code also serves as a check on the accuracy of the transmitted message. Its use herein permits more information (scrambling and order methods) to be transmitted without adding more bits to the transmitted signal. It is to be further noted that it is quite likely that different scrambling methods will be employed in consecutive transmissions of digital signals using the same transmitter. This adds to the degree of difficulty in trying to analyze a captured digital signal. From the above description of the invention, those skilled in the art will perceive improvements, changes and modifications. Such improvements, changes and modifications within the skill of the art are intended to be covered by the appended claims.
|
Same subclass Same class Consider this |
||||||||||
