Stream/block cipher crytographic system4316055Abstract The system disclosed comprises a dual function cryptographic system capable of operating in either a stream or block cipher mode. Further, with minimal alteration the system is capable of performing either encoding or decoding functions. The system requires three inputs, the first of which is the raw data, and the second two inputs comprise a first and a second unique user supplied key. One of the keys is utilized to control a permutation function for both the stream and block cipher mode and the other key is combined directly with the data in the block cipher mode prior to a series of non-linear transformations. In the stream encipherment mode of operation the second key is entered in its entirety into the system where it is successively and continuously transformed as a function of said first key whereby the function of said system becomes a pseudo-random number generator whose output is serially combined with the raw data to form the stream enciphered cryptogram. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 1
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##STR1##
P = 0 :
##STR2##
##STR3##
P = 1 :
##STR4##
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where: .sym. denotes mod2 addition.
AND-gate 7 is enabled in the stream mode, via a control signal from switch SW1(5), and thereby gates the input message stream to adder 18 where said message stream is summed, modulo-2, with the pseudo-random binary bit-stream fed to Adder 18 from the Main Shift Register 14. The system output, i.e., the "Processed Output", is taken from the output of Adder 18. In the block mode of system operation, AND-gate 7 is inhibited (by the zero-valued control signal from switch SW1(5)) from gating the input message stream to Adder 18. In this mode, the output of AND gate 7 takes on the value of zero and thereby causes Adder 18 to pass the signals from the Main Shift Register (14) to the "Processed Output" line without modification. MSR Multiplexer 10 performs four functions under system control; (1) accepts input from KSR2 (8) in the stream mode to load the Main Shift Register (14) with Key 2 data; (2) accepts input from Adder (9) in the block mode to load the MSR (14) with the modulo-2 sum of input data and Key 2 data; (3) accepts input from Input Message Line (1) in the block mode to load the MSR (14) with input data for decipherment operations; and, (4) provides a bi-directional recirculation path around MSR (14) in both stream and block modes of system operation. C. Control Subsystem The control subsystem comprises a micro-programmed finite-state sequential controller which can monitor input signals and produce appropriate output signals to control the system hardware resources. Within Control ROM 22 are stored bit patterns, organized as microwords, which when accessed in the appropriate sequence by the State Counter 23 determine the actions and/or status of system hardware resources in such a manner as to produce required signal processing operations in the process subsystem and appropriate sequences of output control signals and state transitions in the control subsystem. State Counter 23 is controlled by the State Counter Control Network 21. The counter 23 can hold its current value, increment the current value by one, or branch to another value by parallel loading the State Counter with the branch address established on BUS A by a field in the Control ROM output microword. State Counter Control Network (21) generates appropriate increment and branch control signals for the State Counter (23) as a function of: (a) the state transition control field in the Control ROM(22); and, (b) the input from Input Multiplexer (20) in those instances where a particular state transition is to be dependent upon external conditions. Repetitive sequences of operations can be performed a specified number of times by means of the operations counter (25). An initial count may be loaded into the operations counter (via Bus A) from the Control ROM 22. By decrementing the operations counter 25 as part of an operational sequence and testing whether the count therein has reached zero (via input port (3) of Input Multiplexer (IMPX 20), looping can be controlled as required. Control Pulse Mask Network 26 enables the generation of one (or more) of the pulsed output control signals emanating therefrom. A mask of 9 bits from a field in the Control ROM 22 output microword enables (inhibits) specific output control signals when the associated bits in the mask are set to one (zero). Control pulses so generated are synchronized by the System Clock (24) output pulse, CP, shown entering the Control Pulse Mask Network (26) at the lower left. Sustained, or level, control signals are derived directly from the Control ROM output microword. For example, the "MSR MPX ADDR" (address lines for the control of MSR Multiplexer (10)) and the "SL/SR" (shift direction control line for KSR1(11) and Main Shift Register (14)) are control signals that need to be maintained at a given value over many system clock cycles and hence are obtained from the Control ROM output microword. AND-gate 27 is enabled (by "A27 ENABLE" from Control Read-Only Memory 22 in the block mode at the end of each decipher operation. It thereby causes the contents of the Main Shift Register 14 and Key Shift Register 2 (8) to take place in the modulo-2 adder (18). Detailed Description of the Flow Charts Before proceeding with a detailed description of the operation of this system with respect to the flow charts and operational sequence charts it should first be noted generally in FIG. 3 that the first blocks, i.e., 0,1, and 2, comprise a series of three common operations that occur regardless of the mode of operation and it is only on the exit from block 2 that a decision is made as to whether or not the system is in stream or block mode. The remainder of FIG. 3 as is apparent is devoted to the operations which occur during stream mode. Similarly, FIG. 4 takes off at point B in the flow chart of FIG. 3, and thus FIG. 4 is the flow chart of block mode operation. It will be noted that only key-1 shift register 11 is loaded during the generalized portion of the system operations as it is used identically in either mode, however, key-2 is utilized somewhat differently in the block mode, and therefore must be loaded separately as shown on FIG. 4. Key-2 is shown to be loaded in blocks 9 and 24 respectively on FIG. 4 depending upon whether the system is in encipher or decipher mode. The operation of the system will now be described in detail with respect to the operational sequence charts, it being noted that first FIG. 3 will be described and then FIG. 4. Referring briefly to the operational sequence charts appearing subsequently in the specification to the present description, each of these charts contains two columns. The left-hand column labeled Flow Chart Label is the actual block number used in the flow charts of FIGS. 3 and 4 during which the specific operations called for in the operational sequence charts are performed. It will be noted that some blocks require only one specific hardware control function and others require a plurality such as block 3. Referring to FIG. 3, it will be noticed that the first block at the top of the page entitled `Initialize System` contains no specific reference symbol as this includes the various operations which an operator would be required to perform before the system is placed in operation and put on stream, either in a communication environment or internally to a computing system. The initialization operations would include setting the mode switches to determine whether or not block encipherment or stream encipherment is to occur and similarly the operator sets the encode/decode switch also in the hardware. The operator must also load the two user supplied keys into the storage units 3 and 4 on FIG. 2, the contents of which are ultimately gated into the two key shift registers 8 and 11 as appropriate. Assuming that the operations required of the initialization step have been performed the system proceeds normally to block 0. This block asks the question is there a "message present". To do this the microprogram sequence starts from the read only memory 22 and causes input port 1 of the input of the IMPX 20 to be addressed or energized. As will be noted this is the EOM line. As soon as a message is present this line will have a 1 thereon and at the end of a message the line will fall to zero. As soon as the 1 is present at input port 1 to the IMPX 20, the system continues to block 1. In block 1 the next control word energizes the "load KSR-1" line which causes the user supplied key-1 to be loaded from storage device 4 into the KSR-1 shift register 11. The system then proceeds to block 2, this time the mode setting of switch one, SW 1, is tested by interrogating input port 0 of the IMPX 20. As will be noted in referring to FIG. 2 the mode control switch, SW 1, will be connected to a zero signal going in the block cipher mode into a 1 signal in the stream cipher mode. Thus, the operational sequence charts indicate that if the output of the IMPX 20 is 0 the system branches to block 8 which is the block encipherment mode or if a 1, the system continues to block 3. Assuming that the system continues to block 3, the operations required to achieve the loading of the Main Shift Register with key-2, as well as set up a number of additional system control lines, which control the sequential operation of the stream encipherment mode are as follows. First the `load KSR 2` line from ROM 22 is activated which causes the user supplied key-2 to be input into the KSR-2 shift register 8 from the storage device 3. Next the operation counter 25 is loaded with the number 63 from the ROM 22. Next the MSR multiplexer 10 input port 0 is selected by the ROM 22, the SL/SR line going into the bottom of the key-1 shift register is set to a 1, which will cause the register to shift to the right. Next, the output of the control pulse mask network 26 is set by the output from the control word in the read only memory 22 such that the "shift MSR" line, the "shift KSR 2" line and the "count to zero" line is activated. The IMPX 20 input port 3 is activated again by the control word from the read only memory 22. For each clock pulse fed to the counter, a pulse is fed out of the Control Pulse Mask Network to the MSR and to the KSR 2 to shift said items one bit position. After 64 pulses have caused the counter to reach zero, the registers (MSR and KSR 2) will have been sequentially shifted 64 times. The state control counter network 21 is set so that as soon as the input 3 to the IMPX 20 becomes 1, it causes the state counter to increment and begin the next control sequence as required by block 4 of FIG. 3. Block 4 states that the destination field of the MSR is to be loaded. In order to do this the "load MSR DF" line from the control mask network 26 becomes active. This input line into the lower left-hand corner of the MSR is brought up. As will be apparent to those skilled in the art, what this accomplishes is to gate the current contents of fields A and B of the MSR into the two substitution boxes 12 and 13. At the same time the permutation control line from the key-1 shift register 11 is activated to a 1 or a 0, and depending upon this setting, a permutation will occur in the two permutation control multiplexers 15 and 19 under control of the permutation control line. Thus, assuming the bit of key-1 is a 0, the contents of substitution box SF-1 would pass through multiplexer 15, modulo-2, and adder 16, where it is combined with the prior contents of field C and ultimately passes into field C as the destination field of the MSR. Similarly, field A would pass through substitution block 12 through multiplexer 19, and modulo-2 adder 17 where it is combined with the prior contents of field D of the MSR and this combined output would be resident finally in field D of the MSR. As stated all of the control connections are physically built into the disclosed system, the only command required actually is the occurrence of the "load MSR DF" pulse into MSR from the control pulse mask network 26. The system then proceeds to block 5. At this point the control microprogram causes the SL/SR line to be set to 1, i.e., shift right and also sets the MSR input multiplexer port to 3 so that the output for MSR is end-around connected back to its input as will be apparent from an examination of FIG. 2. Next a "shift MSR" pulse is produced from the output of the control pulse mask network 26 which is then applied to MSR and an output pulse is produced from the MSR which passes back through the input multiplexer 10 for the MSR and also proceeds to the modulo-2 adder 18. Concurrently with the arrival of the output pulse from the MSR a data pulse is applied through AND circuit 7 as a second input to the modulo-2 adder 18 and the output is the stream cipher output from the system. It will be noticed that since this is the stream mode, AND circuit 27 is not enabled and there is no input at the bottom of modulo 2 adder 18. The synchronization of the first data pulse with the first MSR output pulse is assumed. It could be readily achieved such as by storing the input data stream on a temporary storage tape, magnetic memory or some other convenient storage medium within the skill of a person knowledgeable in the art. The system then continues to block 6, which again sets the SL/SR line equal to 1, (i.e., a right shift) and "shift KSR 1" line from the control pulse mask network 26 is activated causing the key-1 shift register 11 to be shifted one position and thus bring a new key-1 bit into the view of the permutation control line. As anticipated in the present embodiment the key shift register 11 is illustrated and described as a simple end-around shift register, however, it will be appreciated that a great deal of convolutional logic could be built into such a shift register. The system then proceeds to block 7 where a check is made to determine if the end of the message has occurred, thus, the system can stop operating. This is done by again setting IMPX 20 input address to 1. If the EOM line is still on 1, it means that there is still a message present on the input line and the system will branch back to block 4 and blocks 4, 5, 6, and 7 will be repeated iteratively until the EOM line is set to a 0. When this occurs it means that the end of the message has occurred and the system then goes to label A or back to a standby condition where it will wait for the next message to be received (Block 0). This completes the description of the stream encipherment mode. It will be noted that the cipher/decipher switch SW-2 need never be interrogated in this mode. This is because regardless of encipherment or decipherment the same pseudo-random number stream will be produced by the present system and will always provide the identical input to the modulo-2 adder 18. It will readily be appreciated that after a first modulo-2 addition with a known binary stream, with a second known bianary stream, that a resultant third binary stream will be produced by such an adder. In order to then produce one of the original binary streams it is only necessary to have the combined output and one of the originals. In the present instance the pseudo-random number output stream from the MSR is duplicated at the receiving end and by producing this pseudo-random number stream and mixing or decoding in the modulo-2 adder 18 with the encoded data stream, the original clear-text binary stream is produced. Thus, in the stream mode of operation, encipherment and decipherment operations are essentially identical. The only difference is that in the encipherment case the received message is clear and in the decipherment case the received message would have been previously enciphered or be `ciphertext`. Assuming now that the test made in block 2 of the flow chart of FIG. 3 had indicated that a block mode encipherment operation was to occur, the system branches to block 8 on FIG. 4. Block 8 causes the following operations to occur. The IMPX 20 input port 2 is activated and a determination is made as to whether the system is working in an encipher or decipher mode. If the switch SW 2 is set to 0 (decipher), then the system would branch via the state counter control network 21, to block 18. If on the other hand the SW 2 line is set to a 1, this means the system is to perform an encipherment mode operation and will continue to block 9. In the present instance this latter situation will be assumed. In block 9 a signal is produced from ROM 22 to activate the "load KSR2" line from the control pulse mask network 26, which causes key-2 to be loaded in parallel into the key-2 shift register 8. The system then proceeds to block 10 wherein the asterisk denotes the concurrent loading and unloading of MSR. What occurs during this block is the complete unloading of the MSR, as processed output. It will be noted that it merely passes through the modulo-2, adder 18 in unaltered form since there is no output at either the top or bottom input to the adder, only the input from the MSR. Simultaneously, new data is fed into the MSR which is the modulo-2 addition of the 64 bit key stored in the key-2 shift register 8 and 64 bits of a new message block both of which are fed through the modulo-2 adder 9, passed through the input port 1 of the MSR multiplexer 10, and on into the MSR. The specific hardware which is activated to accomplish this action is as follows. The operation counter 25 is set to 63 via BUS A from the ROM 22. The microprogram control sequence causes the following hardware settings. The MSR multiplexer address is set to (1) as stated previously, and the IMPX 20 input is set to (3) to detect when the operation counter is returned to 0. The control pulse mask network 26 is set to enable the "shift MSR" line and the "shift KSR-2" line so that these two lines will receive the clock pulses (CP) as produced by the clock 24. Finally the state counter control network 21 and state counter are set so that when the input to the port (3) of IMPX 20 returns to a 0, the system will continue to block 11. What happens now is that as the system clock runs for a total of 64 total pulses, the MSR will be concurrently emptied at the one and loaded at the other, and when the final bit shift occurs, the operation counter will have been reset to 0, to produce an appropriate signal at port (3) of the IMPX 20. This causes the system to continue to block 11. Block 11, simply resets the operation counter to 63, via BUS A, however, this time the operations counter will control 64 cycles of cryptographic transformation of the block data and key currently stored in the MSR. Block 11 then proceeds to block 12 wherein a signal appears on the "load MSR DF" output line from the control pulse mask network 26. This operation is now identical to that of the previously described stream-mode operation which causes the contents of source fields A and B of the MSR to be gated through the substitution devices SF-0 and SF-1 and then through the two multiplexers 15 and 19, the modulo-2 adders 16 and 17 and finally into the two destination fields C and D. It will similarly be remembered that the two multiplexers 15 and 19 are controlled by the setting of the permutation control line emanating from the key-1 shift register 11. Depending on the setting of this line, the output of the two substitution devices 12 and 13 will pass through one or the other of the input ports of the multiplexers 15 and 19 to be subsequently combined in the modulo-2 adders with the prior contents of the destination fields C and D of the MSR. This operation will occur within one system cycle or clock pulse produced by the system clock 24, and upon completion, the system continues to block 13. What occurs in block 13 is a rolling or shifting of the MSR and the key-1 shift register 11. This is prior to the next encryption round so that new data is presented for both the permutation control and also for the primary cryptographic transformation. To do this the SL/SR line is set to 1 so that both registers will be shifted in the same direction, i.e., to the right, and the MSR multiplexer 10 address is set to (3) to allow for end-around shifting of the MSR, and finally, the "shift MSR" and "shift KSR-1" lines from the output of the control pulse mask network 26, are activated so that the next clock pulse causes the actual single shift of these two registers. At this point the system proceeds to block 14 where a test is made of the operation counter to see if all of the required cycles of encryption, (i.e. 64) have been completed. To do this the IMPX 20 address is set to (3) and the condition of the operation counter reset to 0. Its output line would automatically be set to a 1, which would mean that all of the necessary rounds of encryption had been completed and the system would go to block 16, if not the input to the multiplexer 20 (at port 3) would remain at 0 and the system would continue to block 15. Block 15 causes the operation counter 25 to be decremented via the appropriate output lines from control pulse mask network 26 and proceed back to block 12, wherein the current contents of the MSR are again cryptographically transformed as described previously with respect to blocks 12 and 13. This loop consisting of blocks 12, 13, 14, and 15, continues until it is determined that the operation counter has been ultimately reset to 0, at which point the system proceeds to block 16. Block 16 tests to see if this is the last member or block of the input message or whether there is still more message to be encrypted or decrypted. This is done by setting the IMPX 20 address to 1 which tests the condition of EOM line. It will again be remembered that the EOM line will be set at 0 as long as a message still exists and will go to a 1 when the end of message (EOM) signal is received. Assuming that there are still further message blocks to be decoded the system would return to block 9 of the flow chart and the ensuing sequences would be repeated until all blocks of data have been successfully enciphered or deciphered. If on the other hand the EOM line is set to a 1, the system will continue to block 17. At this point essentially half of the operation which occurred in block 10 is repeated, namely the MSR is unloaded as this is the last block of the encoded message. To accomplish this the operation counter is again loaded with the number 63 via BUS A from the ROM 22. The SL/SR line is set to 1 and the "shift MSR" line from the control pulse mask network 26 is activated. The IMPX 20 address is set to (3) and the state counter control network is set to increment the state counter 23 to branch back to block 0 upon exit from block 17. At this point the system clock 24 pulses (CP) cause the MSR to be shifted to the right to place this last block of enciphered data on the `processed output` line, and when 64 such shifts have occurred the output from the operation counter changes from a 0 to a 1, which as stated previously, causes the instruction sequence to branch back to the standby or initialization state represented by block 0. This completes the description of the encipherment half of the block cipher mode of operation. What will be described next is the decipherment mode which will be remembered is a test made back in block 8 which causes clock 18 of the flow chart to be entered. It will be remembered from the above paragraph that block 18 is the initial step or phase of a deciphering operation. At this point it should be recalled that the enciphered block of data which is being received as the input message was combined with the user supplied key-2 from the key-2 shift register 8 prior to the cryptographic transformations. Thus, what must occur during decryption is that this input message must be placed directly into the MSR without the modulo-2 combination with the key-2 till a complete set of decryption has occurred and finally the output of the partially cryptographically deciphered block of data passes through the modulo-2 adder 18 where it is modulo-2 combined with key-2 via AND circuit 27 to produce the final deciphered stream. In order to gate the incoming encrypted message blocks directly into the MSR, port (2) of the MSR multiplexer 10 is energized. The SL/SR line is set to 1 since this is to be simply a loading operation and encryption is not involved as will be explained later. The operation counter 25 is again set to 63 via BUS A from ROM 22. The "shift MSR" line of the control pulse mask network 26 is activated and the IMPX 20 port (3) is addressed to monitor the condition (i.e. 0) of the operation counter 25. The state counter control network 21 is set so that when the output from the input multiplexer equals 1, the state counter will be incremented, thus, the system will continue to block 19. As will be remembered at this point with the present controls set, the clock pulses from the system clock 24 consecutively pass through the control pulse mask network to cause 64 bits of input message, which is to be decrypted, to be loaded into the MSR. This loading operation is continuously monitored by the operation counter 25 and thus the state counter control network 21 is activated when the operation counter goes to 0 so that its output line raises to a 1 which will cause the next instruction to be accessed from the ROM 22 which brings the system to block 19 of the flow charts. A block of encrypted data is currently sitting in the MSR and is waiting to be cryptographically transformed (decoded). At this point the encryption and decryption sequence of operations is identical with the exception of the fact that the MSR is shifted in the opposite direction, i.e., to the left, and the key-1 shift register 11 is similarly shifted to the left instead of to the right between transformation cycles. The loading of the destination fields, of the MSR, i.e., destination fields C and D from source fields A and B, is identical in that fields A and B pass through the two substitution boxes 12 (SF0) and 13 (SF1), the multiplexers 15 and 19 under control of the permutation control line and thence through the modulo-2 adders 16 and 17 into the ultimate destination fields C and D. Subsequent to each such transformation a new shift to the left occurs. Thus, blocks 20 and 21 are identical to blocks 13 and 12 respectively of the encipherment mode with the exception that the shift direction is the opposite and as will be noted blocks 20 and 21 are in effect inverted with respect to blocks 12 and 13. This as will be apparent cryptographically reverses or inverts the encryption operation. Block 22 is identical to block 14 in that it tests the setting of the operation counter to determine whether the necessary decryption cycles (64) have been completed. If not the operation counter is decremented and blocks 20 and 21 are repeated and again the test is made in block 22. A specific description of the hardware operations performed by blocks 20, 21, 22, and 23 will not be repeated here as they are essentially identical to those performed by blocks 12, 13, 14, and 15 just described previously. The actual operations which occur in these blocks clearly set forth in operational sequence charts. Assume the system has now continued to block 24. At this point the control pulse mask network 26 enables the "load KSR-2" line thus causing the user supplied key-2 to be loaded into key-2 shift register 8. The end of block 24 proceeds to block 25, wherein, two operations in the MSR occur simultaneously, that is the outputting of the contents of the MSR and the loading of a new block of enciphered data (if one is present, which is determined in block 26). It will be noted from the formula in block 25 that the outputting operation is accompanied by a modulo-2 addition of the contents of the MSR and the user supplied key-2 which, modulo addition occurs in box 18. The output from the MSR enters modulo-2 adder 18 directly from the left and key-2 is sequentially gated in synchronism with said MSR data through AND circuit 27 to the bottom input of block 18. This final modulo-2 addition completes the decryption operation which, as will be remembered, is the cryptographic and mathematical inverse of the encryption operation which will thus produce the correct decoded message as the ` processed output` from the system. Specifically block 25 requires the following operations to occur. The operation counter 25 is again loaded with the number 63 via BUS A, from the ROM 22. Concurrently, the MSR input multiplexer port (2) is enabled and the input port (3), of the IMPX 20 is enabled to allow monitoring of the operation counter 25. The MSR multiplexer input port is set to (2) to provide for the direct gating of the encrypted data into the MSR if there is in fact a block of data on the input message line at this time. The AND 27 Enable line is set to a 1 to open gage 27 to allow the appropriate gating of key-2 data therethrough and the SL/SR line is set to a 1 so that the MSR maybe unloaded through modulo-2 adder 18. The state counter control network 21 is set so that upon the occurrence of a 1 from the output from the output of the the IMPX 20 the system will proceed to block 26. Thus the MSR is concurrently loaded and unloaded under control of the system clock via 64 consecutive pulses therefrom, until the completed state of the operation counter indicates that block 26 is to be entered. At this point a test is made to see if the last block of data has been decrypted. In order to do this the EOM line is tested by addressing port (1), of the IMPX 20. If the EOM line is set to a 1 it means that there is still message data present, and the state counter control network 21 causes the system to branch back to block 19 which will cause a new block decryption round to occur. If on the other hand EOM line is set to 0 the state counter control network 21 causes the state counter 23 to be incremented to return the system back to flag A which returns the system to block 0 which is the waiting or standby condition. This completes the description of the detailed operation of the present stream/block cipher cryptographic system. From the above description the complete versatility of the present system will be apparent, especially the use of the function of the various hardware components during the various modes of system operations in an almost identical manner.
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STREAM/BLOCK CRYPTOGRAPHIC SYSTEM
OPERATIONAL SEQUENCE CHARTS
Flow
Chart
Operation
Label
Performed
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0..........
SET: *IMPX ADDRESS=1
WHEN IMPX.fwdarw.1, CONTINUE
1..........
LOAD KSR 1
2..........
SET: *IMPX ADDRESS=0
IF IMPX=0, GO TO LABEL B.fwdarw.(BLOCK 8)
IF IMPX= 1, CONTINUE.fwdarw.TO BLOCK 3
Stream Mode Operations
3..........
LOAD KSR2
LOAD OPNCTR (BUS A=63)
SET: *MSR MPX ADDRESS= 0
*SL/SR= 1
*CONTROL PULSE MASK to enable SHIFT MSR,
SHIFT KSR2, and COUNT TO ZERO
*IMPX ADDRESS=3
*STATE TRANSITION CONTROL such that when
IMPX.fwdarw.1, CONTINUE (TO BLOCK 4)
4..........
LOAD MSRDF
5..........
SET: *SL/SR=1
*MSR MPX ADDRESS=3
SHIFT MSR
6..........
SET: *SL/SR=1
SHIFT KSR1
7..........
SET: *IMPX ADDRESS =1
IF IMPX=0, GO TO LABEL A (end)
IF IMPX=1, GO TO BLOCK 4
Block Mode Operations
8..........
SET: *IMPX ADDRESS= 2
IF IMPX=0, GO TO LABEL 18
IF IMPX= 1, CONTINUE
9..........
LOAD KSR2
10..........
LOAD OPNCTR with 63 via BUS A
SET: *MSR MPX ADDRESS=1
*IMPX ADDRESS=3
*CONTROL PULSE MASK to enable SHIFT MSR
and SHIFT KSR2
*STATE COUNTER CONTROL NETWORK such that when
IMPX.fwdarw.1, CONTINUE (TO LABEL 11)
COUNT TO ZERO
11..........
LOAD OPNCTR with 63 via BUS A
12..........
LOAD MSRDF
13..........
SET: *SL/SR=1
MSR MPX ADDRESS=3
SHIFT MSR and SHIFT KSR1
14..........
SET: *IMPX ADDRESS=3
IF IMPX=1, GO TO BLOCK 16
IF IMPX=0, CONTINUE
15..........
DECR OPNCTR
GO TO BLOCK 12
16..........
SET: *IMPX ADDRESS= 1
IF IMPX=0, GO TO BLOCK 9
IF IMPX=1, CONTINUE to BLOCK 17
17..........
LOAD OPNCTR (BUS A=63)
SET: *SL/SR=1
*CONTROL PULSE MASK TO ENABLE SHIFT MSR
*STATE COUNTER CONTROL NETWORK such that when
IMPX.fwdarw.1, GO TO LABEL 0
*IMPX ADDRESS=3
COUNT TO ZERO
18..........
LOAD OPNCTR (BUS A=63)
SET: *SL/SR=1
*MSR MPX ADDRESS=2
*CONTROL PULSE MASK TO ENABLE SHIFT MSR
*IMPX ADDRESS=3
*STATE COUNTER CONTROL NETWORK such that when
IMPX.fwdarw.1, CONTINUE (to BLOCK 19)
COUNT TO ZERO
19..........
LOAD OPNCTR to 63 via BUS A
20..........
SET: *MSR MPX ADDRESS=3
*SL/SR=0
SET CONTROL PULSE MASK TO ENABLE SHIFT MSR and SHIFT KSR1
21..........
SET CONTROL PULSE MASK TO ENABLE LOAD MSRDF
22..........
SET: *IMPX ADDRESS=3
IF IMPX=1, GO TO LABEL 4
IF IMPX=0, CONTINUE
23..........
SET CONTROL PULSE MASK TO ENABLE DECR OPNCTR
GO TO LABEL 20
24..........
SET CONTROL PULSE MASK TO ENABLE LOAD KSR2
25..........
LOAD OPNCTR to 63 via BUS A
SET: *MSR MPX ADDRESS= 2
*IMPX ADDRESS=3
*A27 ENABLE= 1
*SL/SR=1
*STATE COUNTER CONTROL NETWORK such that when
IMPX=1, CONTINUE (to BLOCK 26)
26..........
SET: *IMPX ADDRESS=1
IF IMPX=1, GO TO BLOCK 19
IF IMPX=0, Means "END OF MESSAGE" return to BLOCK 0
GO TO LABEL 0
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CONCLUSIONS It should be readily understood that while the presently disclosed system represents what is `considered` to be the preferred hardware embodiment for practicing the invention, that nevertheless many variations of the basic concepts are possible. For example, the user supplied key referred to herein as key-2 could be many multiples of 64 bits and be sequentially applied as required, which would obviously produce a further level of security to the system. Similarly, the specific configuration of the transformations utilized in the Transformation Element could take on many variations still under control of the key, referred to herein as user supplied key-1. More than two transpositions matrices or permutation boxes could be used, and similarly more than two substitution blocks could readily be utilized. Additionally, the details of the control subsystem could vary quite widely and a number of the loading operations could be changed from serial to parallel to save time at an attendant cost in hardware. However, the underlying concept of utilizing essentially the same hardware to generate a pseudo-random number stream for use as a stream cryptographic system or as a rather complex block cryptographic system is considered to be basically unique. While the invention has been disclosed and described with respect to the herein disclosed embodiment as well as the above suggested changes, it will be apparent that still other and different modifications to the system could be made within the spirit and scope of the invention.
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