Bilateral digital data transmission system

Abstract

A digital data transmission system for transmitting digital data from digital data handling hardware over a transmission line by analog signal representation and for receiving analog signal representation for reception of digital signals by the digital data handling hardware, incorporates an integrated circuit PSK modem. The modem has a transmitter which includes an encoder for encoding digital data into a first format for conversion to corresponding PSK signals and a transmitter modulator, implemented in switched capacitor circuits, for phase modulating a first carrier frequency according to the first format. The modem has a receiver that includes a demodulator, implemented in switched capacitor circuits, for demodulating PSK signals on a second carrier frequency to provide a second format for conversion to corresponding digital signals, and an encoder for encoding the second format into corresponding digital signals. In the preferred embodiment, the transmitter includes a buffer for the accommodation of a variety of modem protocols, a first filter for compensation of gain distortion in the transmission line, and a second filter for compensation of phase distortion in the transmission line. In this preferred embodiment, the receiver includes compensating filters for transmission line gain and phase distortion, automatic gain control and adaptive equalization filtering for reducing cross-talk noise between the transmission and receiving lines.

Claims

What is claimed is:

1. A bilateral digital data communication system for originating digital signals and for transmitting PSK modulated signals representative thereof on a first carrier frequency over a first transmission line, and for receiving PSK modulated signals on a second carrier frequency over a second transmission line, and for conversion to digital signals representative thereof, comprising:

(a) digital data originating and receiving means;

(b) PSK modem transmit encoding means connected to receive digital data from the digital data originating and receiving means for encoding digital data into a first format for conversion to corresponding PSK signals;

(c) PSK modem transmit modulating means, implemented in switched capacitor circuitry and connected to receive the first format for phase modulating the first carrier frequency according to the first format to provide corresponding PSK signals;

(d) PSK modem receive demodulating means, implemented in switched capacitor circuitry, for demodulating the PSK signals on the second carrier frequency to provide PSK signals in a second format for conversion to corresponding digital signals; and

(e) PSK modem receive encoding means connected to receive the second format for encoding the second format into corresponding digital signals and connected to send the corresponding digital signals to the digital data originating and receiving means.

2. The system of clam 1, further comprising:

(f) PSK modem transmit buffer means connected between the digital data originating and receiving means, and the PSK modem transmit encoding means, for synchronizing asynchronous digital signals received from the digital data originating and receiving means.

3. The system of claim 2, wherein the PSK modem transmit buffer means further comprises:

(f)

(i) means for selecting one of a plurality of modem protocols;

(ii) means, responsive to the selected protocol, for generating a desired bit rate; and

(iii) scrambling means responsive to the selected protocol, for selectively scrambling the synchronous digital signals.

4. The system of claim 1, further comprising:

(g) PSK modem transmit amplitude filter means, implemented in switched capacitor circuitry, connected to the PSK modem transmit modulating means, for compensating for amplitude distortion caused by the first transmission line.

5. The system of claim 4, further comprising:

(h) PSK modem transmit phase filter means, implemented in switched capacitor circuitry, connected to the amplitude filter means, for compensating for phase distortion caused by the first transmission line.

6. The system of claim 3, further comprising:

(g) PSK modem transmit amplitude filter means, implemented in switched capacitor circuitry, and connected to the PSK modem transmit modulating means, for compensating for amplitude distortion caused by the first transmission line.

7. The system of claim 6, further comprising:

(h) PSK modem transmit phase filter means, implemented in switched capacitor circuitry, connected to the amplitude filter means, for compensating for phase distortion caused by the first transmission line.

8. The system of claim 1, further comprising:

(g) PSK modem receive filter means, implemented in switched capacitor circuitry, connected between the second transmission line and the PSK modem receive demodulating means to receive the PSK modulated signals therefrom, for filtering and compensating for gain and phase distortion caused by the second transmission line.

9. The system of claim 5, further comprising:

(g) PSK modem receive filter means, implemented in switched capacitor circuitry, connected between the second transmission line and the PSK modem receive demodulating means to receive the PSK modulated signals therefrom, for filtering and compensating for gain and phase distortion caused by the second transmission line.

10. The system of claim 9, further comprising automatic gain control means, implemented in switched capacitor circuitry, connected between the PSK modem receive demodulation means and the psk modem receive filter means, for adjusting the gain of the PSK signals to a predetermined magnitude.

11. The system of claim 1, wherein the demodulating means comprises clock recovery means for providing sampling signals from the demodulated incoming PSK signals.

12. The system of claim 10, wherein the demodulating means comprises clock recovery means for providing sampling signals from the demodulated incoming PSK signals.

13. The system of claim 1, further comprising:

(k) PSK modem receive buffer means, connected between the modem receive encoding means and the digital data originating and receiving means for selectively unscrambling scrambled decoded digital signals.

14. The system of claim 3, wherein the PSK modem transmit buffer means further comprises means for adding and deleting stop bits to and from the digital signals depending upon the selected protocol.

15. The system of claim 7, wherein the PSK modem transmit buffer means further comprises means for adding and deleting stop bits to and from the digital signals depending upon the selected protocol.

16. The system of claim 13, wherein the PSK modem receive buffer means further comprises means for adding stop bits to the decoded signals when they have been deleted.

17. The system of claim 1, wherein the digital data originating and receiving means comprises a data terminal.

18. The system of claim 7, wherein the digital data originating and receiving means comprises a data terminal.

19. The system of claim 8, wherein the digital data originating and receiving means comprises a data terminal.

20. The system of claim 16, wherein the digital data originating and receiving means comprises a data terminal.

21. An integrated circuit PSK modem formed on a single semiconductor chip for transmitting and receiving PSK signals, derived from digital signals, impressed on a first and second carrier frequency on a first and second transmission line, respectively, comprising:

(a) transmit encoding means for encoding digital data into a first format for conversion to corresponding PSK signals;

(b) transmit modulating means, implemented in switched capacitor circuitry, connected to the first transmission line for phase modulating the first carrier frequency according to the first format to provide corresponding PSK signals;

(c) receive demodulating means, implemented in switched capacitor circuitry, for demodulating the PSK signals from the second transmission line to provide PSK signals in a second format for conversion to corresponding digital signals; and

(d) receive encoding means connected to receive the second format for encoding the second format into corresponding digital signals.

22. The modem of claim 21, further comprising:

(e) transmit buffer means connected to the transmit encoding means for synchronizing asynchronous digital data.

23. The modem of claim 22, wherein the transmit buffer means further comprises:

(e)

(i) means for selecting one of a plurality of modem protocols;

(ii) means responsive to the selected protocol, for generating a desired bit rate; and

(iii) scrambling means, responsive to the selected protocol, for selectively scrambling the synchronous digital signals.

24. The modem of claim 21, further comprising:

(f) transmit amplitude filter means, implemented in switched capacitor circuitry, connected to the transmit modulating means, for compensating for amplitude distortion caused by the first transmission line.

25. The modem of claim 24, further comprising:

(g) transmit phase filter means, implemented in switched capacitor circuitry, connected to the amplitude filter means, for compensating for phase distortion caused by the first transmission line.

26. The modem of claim 23, further comprising:

(f) PSK modem transmit amplitude filter means, implemented in switched capacitor circuitry, connected to the transmit modulating means, for compensating for amplitude distortion caused by the first transmission line.

27. The mode of claim 26, further comprising:

(g) transmit phase filter means, implemented in switched capacitor circuitry, connected to the amplitude filter means, for compensating for phase distortion caused by the first transmission line.

28. The modem of claim 21, further comprising:

(h) receive filter means, implemented in switched capacitor circuitry, connected between the second transmission line and the demodulating means to receive the PSK modulated signals therefrom, for filtering and compensating for gain and phase distortion caused by the second transmission line.

29. The modem of claim 25, further comprising:

(h) receive filter means, implemented in switched capacitor circuitry, connected between the second transmission line and the PSK modem receive demodulating means to receive the PSK modulated signals, for filtering and compensating for gain and phase distortion caused by the second transmission line.

30. The modem of claim 21, further comprising automatic gain control means, implemented in switched capacitor circuitry, for adjusting the gain of the PSK signals to a predetermined magnitude.

31. The modem of claim 29, further comprising automatic gain control means switched capacitor circuitry, connected between the receive demodulting means and the receive filter means.

32. The modem of claim 21, wherein the demodulating means comprises clock recovery means for providing sampling signals from the demodulated incoming PSK signals.

33. The modem of claim 31, wherein the demodulating means comprises clock recovery means for providing sampling signals from the demodulated incoming PSK signals.

34. The modem of claim 21, further comprising:

(j) receive buffer means, connected to the modem receive encoding means, for selectively unscrambling scrambled decoded digital signals.

35. The modem of claim 23, wherein the transmit buffer means further comprises means for adding and deleting stop bits to and from the digital signals depending on the selected protocol.

36. The modem of claim 34, wherein the PSK modem transmit buffer means further comprises means for adding and deleting stop bits to and from the decoded signals depending on the selected protocol.

37. The modem of claim 34, wherein the receive buffer means further comprises means for adding stop bits to the decoded signals when they have been deleted.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to bilateral digital data communication and in particular to the transmission and reception over a pair of lines at different frequencies of phase shift keying (PSK) modulated signals utilizing a PSK modem for communication with digital data handling apparatus.

2. Description of the Prior Art

Discrete component bilateral digital data transmission systems are well known in the prior art. These systems include PSK type modem components.

Single semiconductor chip frequency shift keying (FSK) modems are known in the prior art. See, for example, copending patent application Ser. No. 269,214, filed June 2, 1981, entitled "Integrated Circuit FSK Modem" and assigned to the assignee of this invention. The FSK technique has certain disadvantages with respect to requiring a large band width and relatively slow data rates.

The PSK modem employed in this invention provides all of the necessary modulation, demodulation, and filtering functions on a single chip. The analog functions of the circuit are implemented using switched capacitor technology.

BRIEF SUMMARY OF THE INVENTION

A digital data handling device is connected to transmit digital data to and receive digital data from a PSK modem formed on a single semiconductor chip. Switched capacitor technology is employed for the analog functions, implemented in field effect transistors and capacitors. Specifically, the field effect transistors are metal oxide semiconductors (MOSFET). The digital circuits of this invention employ MOSFETs as well.

Switched capacitor technology is known (see Bell System Technical Journal Volume 58, No. 10, December 1979) and in this preferred embodiment is equivalent to the combination of a resistor connected to one input of an operational amplifier whose other input is grounded and whose output is fed back through a capacitor to its one input.

The modem transmitter includes a buffer adapted to communicate with various types of modem receivers at the other end of the line. The transmission buffer is bypassed when the digital data handling apparatus operates synchronously with the corresponding apparatus on the other end of the line. Depending upon the modem protocol (type of modem at the receiving end) a buffer will scramble the digital data and the PSK modulator will modulate a carrier frequency suitable for the selected protocol. The buffer adds stop bits at the end of a character when the bit rate from the digital data handling hardware is lower than the bit rate of transmission. The buffer also has provision for removing one out of four or one out of eight stop bits, depending upon the selected protocol, when the bit rate from the digital data handling hardware is higher than the transmission line bit rate required.

The transmitter section of the modem has an encoder for receiving a train of digital pulses from the buffer and for translating those pulses into phase shift information. In this preferred embodiment, four phase PSK is employed. That is, phase shifts at zero degrees, 90 degrees, 180 degrees and 270 degrees have significance, determined by the selected protocol. Two bits (dibits) are required to represent those four phase shifts and the dibits are formed by the encoder. The dibits are used to derive clock gating signals for the transmitter analog section.

The transmitter analog section is made up of an I channel and a D channel. The gating clock signal derived from one dibit is applied in one channel and the gating clock signal derived from the other dibit is applied in the other channel, the timing such that the I channel provides a digital representation mixed with the cosine of the carrier and the Q channel provides the information mixed with the sine of the carrier. The two channels are combined to provide a single channel PSK wave train.

The transmitter is also provided with filters for receiving the PSK channel signals for gain and phase distortion anticipated in the transmission line which is typically a telephone line.

In this preferred embodiment, the receiver of the modem has filters for receiving a PSK modulated waveform from a transmission line, the filters designed to compensate for gain and phase distortion of the telephone line. The gain of the filter is also adjustable by an automatic gain control circuit for optimizing the gain.

A carrier recovery circuit receives the filtered, gain controlled PSK modulated waveform and separates it into an I channel (cosine of the carrier) and a Q channel (sine of the carrier).

A clock recovery circuit recovers clock timing from the I and Q data information to provide a clock for sampling the incoming information at the proper time.

The receiver has an adaptive equalizer filter for receiving the I channel (baseband) and Q channel (baseband) information to remove from those basebands unwanted signals cross-coupled from the associated transmitter line.

The receiver has a decoder that decodes the sampled baseband information into dibit information which is combined to form a train of digital signals.

Finally, the receiver is provided with a buffer which, in the case of synchronously originated data, is bypassed. When the incoming data characters have more than one stop bit, the receiver ignores the extra stop bits. If the data coming in had stop bits deleted, the buffer adds stop bits of an appropriate width to maintain synchronization. Also, if the incoming data was scrambled, the buffer unscrambles it. The treated digital data is then sent to the digital data handling hardware.

The principal object of this invention is to provide a data transmission system employing an integrated circuit PSK modem, substantially self-contained in a single integrated circuit chip.

Another object of this invention is to provide a data transmission system having an integrated circuit PSK modem with its analog and digital functions implemented in a single semiconductor chip.

Another object of this invention is to provide a data transmission system having modulation, demodulation, filtering, and clock and carrier detect functions on one single semiconductor chip.

Still another object of this invention is to provide a data transmission system having an integrated circuit PSK modem implemented in switched capacitor technology employing a MOSFET circuitry to perform its analog functions.

These and other objects of this invention will be made evident in the detailed description that follows.

FIG. 1 is a block diagram of the bilateral digital data transmission system of this invention.

FIG. 2 is a block diagram of the transmit buffer of this invention.

FIGS. 3A-3C, FIGS. 3A', 3B' and 3C' are part of FIGS. 3A, 3B, 3C respectively form a schematic diagram of the DTE and SCT clock generation circuits, the start-stop counter, the character bit counter, input sampling, stop bit detect, up/down counter and FIFO, of the transmit buffer.

FIG. 4 illustrates data bit sampling.

FIG. 5 schematically illustrates stop bit insert-delete control of the transmit buffer.

FIG. 6 schematically illustrates modem selection circuitry for the transmit buffer.

FIGS. 7A and 7B and 7C illustrate the scrambler and dibit generator of the transmit buffer.

FIG. 8 illustrates circuitry for the generation of signals used in the transmitter.

FIG. 9 illustrates circuitry for the generation of control signals for the up/down counter.

FIGS. 10A and 10B are schematic diagram illustrating the development of timing signals for the transmitter.

FIG. 11 is a schematic diagram illustrating the development of timing signals for the I and Q channel timing for the transmitter.

FIG. 12 is a schematic diagram illustrating the development of data derived timing signals for modulating the I and Q channels.

FIG. 13 is a schematic diagram illustrating the development of signals used in shaping the input square wave digital signals.

FIG. 14 contains timing signals of the transmitter.

FIG. 15 illustrates signals used in the carrier generation.

FIGS. 16A and 16B form a schematic diagram of the transmitter modulator.

FIG. 17 is a schematic diagram of the switching circuits for switching capacitance in and out of the circuit.

FIG. 18 is a schematic diagram of the transmitter gain compensation filter.

FIG. 19 is a schematic diagram of the transmitter phase compensation filter.

FIG. 20 illustrate waveforms at various points within the transmitter.

FIGS. 21-25 illustrate circuits for the development of timing signals used in the modem receiver.

FIG. 26 is a schematic diagram of a continuous filter for receiving a PSK signal followed by a sampled low pass filter followed by a block indication of the PSK receive filter.

FIGS. 27A and 27B form a schematic diagram of circuitry for the development of signals controlling the gain of the PSK receive filter.

FIG. 28 is a schematic diagram of the development of the energy detect signal.

FIGS. 29A-29E and FIGS. 29a'-29e' are part of FIGS. 29A-29E respectively form a schematic diagram of the receive filter.

FIG. 30 is a block diagram of the automatic gain control and associated circuits.

FIGS. 31A-31C form a schematic diagram of the specific AGC fircuit.

FIG. 32 is a block diagram of a digital voltage controlled oscillator used in the carrier recovery loop.

FIGS. 33-35 are schematic diagrams illustrating the development of gating signals for the phase shifting network.

FIGS. 36A-36D are schematic diagrams of circuits for the voltage controlled oscillator and signal development therefor.

FIGS. 37A-37D schematically illustrate the A to D converter and signal development therefor.

FIGS. 38A and 38B form a schematic diagram of the count control circuit.

FIGS. 39A and 39B form the phase shifter circuit schematic.

FIG. 40 is a schematic diagram of a buffer filter.

FIGS. 41, and 42A and 42B are schematic diagrams illustrating the development of timing signals for the clock recovery loop.

FIGS. 43A and 43B schematically illustrate the clock recovery loop.

FIGS. 44A-44H are schematics illustrating the development of timing signals for the adaptive equalizer.

FIGS. 45A and 45B are schematic diagram of the adaptive equalizer.

FIG. 46 is a schematic diagram of the development of the input signal for the AGC circuit.

FIG. 47 is a block diagram of the baseband to digital converter.

FIG. 48 is a schematic diagram of the baseband to digital converter.

FIG. 49 is a block diagram of the receive buffer.

FIG. 50 is a block diagram of the scrambler and data loop recovery counter.

FIGS. 51A-51E form a schematic diagram of the receive buffer.

FIG. 52 illustrates an input waveform with stop bits removed and a corresponding output waveform with stop bits added.

FIG. 1 is a block diagram of the entire system. Data terminal 5 is shown as the digital data handling hardware of this invention. In this preferred embodiment, terminal 5 is a Texas Instruments Incorporated Model 787 portable communications data terminal, fully described in Texas Instruments Manual #2265938-9701, copyright 1980. The digital data handling hardware could, of course, be any digital computer, terminal, or any other hardware source for receiving and/or sending out digital data.

Terminal 5 is shown connected to transmit buffer 11 whose output is shown connected to transmit encoder 12. Transmit encoder 12 sends encoded information to transmit analog 13 which sends a PSK modulated waveform into (in this preferred embodiment) a transmit equalizer circuit. The above circuits are clocked by transmit clocks generated from signal OSCIN.

PSK modulated waveform RCVA is received by receive filter 18 which is acted upon by receive AGC 19 for adjusting gain of the input signal. Carrier recovery circuit 20 receives the filtered signal, splits it into baseband signals and adaptively equalizes the baseband signals to remove cross-talk between the transmitter and receiver transmission lines. The baseband signals are sent to clock recovery circuit 21 which recovers the clock used in the transmission for decoding the baseband signals in receive decoder 22. The output of receive decoder 22 is shown entering receive buffer 23.

Referring to FIG. 2, a block diagram of the transmit buffer 11 is shown. DTE clock generation 25 is shown having control signals FAST and HLFSPD and a clock input of 4 MHz. The output is 16X DTE which is input to start-stop counter 60. The output of start-stop counter 60 is signal DTE which is applied to character bit counter 65, to input sampling 75, and to DTE-to-SCT sync 130. Character bit counter 65 also has signals C1 and C2 for determining character length applied. Its output, signal ENDCHAR is sent to stop bit detect 70. Input sampling 75 has the input signal XMTD applied and its output goes to stop bit detect 70 and to FIFO 100. Stop bit detect 70 has output signal STOP which goes to DTE to SCT sync 130 and to start-stop counter 60.

SCT clock generation 40, having BELL/RV, FAST and 4 MHz inputs provides output clock 16XSCT which is applied to SCT clock 90 and to DTE-to-SCT sync 130. SCT clock 90 has control signal HLFSPD applied and its output signal NHSCT is applied to DTE to SCT sync 130. An output from clock 90 is also applied to FIFO 100 and to stop-bit-insert-delete control 140.

DTE-to-SCT sync 130 provides output signals S STOP and SDTE which are applied to control 140. Control 140 also has signal 1/8 applied and provides output signals to UP/DOWN counter 80 and to FIFO 100. UP/DOWN counter 80 also applies signals to FIFO 100. FIFO 100 provides output signal FIFOUT, which is scrambled or not, depending upon the modem selection.

TRANSMIT BUFFER

FIGS. 3A and 3B schematically illustrate the data terminal equipment (DTE) clock generation circuit 25 of FIG. 2. An externally supplied oscillator square wave signal (at a frequency of 4,032 MHz in this preferred embodiment and hereafter referred to as 4 MHz) is applied through buffer circuit 26 which provides a "false" output after inverter 27 and a "true" output after inverter 28, the true output being applied to the input of clock generator circuit 33. Clock generator circuit 33 provides clocks 1 and 2 which are 180.degree. out of phase. The true output from buffer circuit 26 is inverted through inverter 29 and applied as an input to NOR gate 31 and as an enabling signal on NOR gate 32. The output of inverter 29 is inverted through inverter 30, providing an input to NOR gate 32 and an enabling signal for NOR gate 31. NOR gates 31 and 32 are cross coupled with NOR gate 31 providing clock 1 and NOR gate 32 providing clock 2. Clocks 1 and 2 are used for timing DTE clock generation circuit 25, a pseudo-random shift register, which is made up of flip flops FF10-FF18 by providing clock inputs to those flip flops. Flip flop 10 has its Q output connected to the D input of flip flop 11 and its Q and Q- outputs connected into programmed logic array (PLA) 38, as shown. The interconnections between the remaining flip flops are identical, with variations, of course, in the devices selected by the PLA38. Exclusive OR circuit 34 provides the logical exclusive OR of flip flops 14 and 18 to provide the D inputs to flip flop 10. The pseudo-random shift register is connected in a well known manner and provides an output signal, IGDTE-, which is 16 times the desired operational frequency.

It should be noted throughout this discussion, a "-" following a designation of signal indicates the inversion of the signal, while on the drawings, an inversion is indicated by a bar over the signal designation. Signals FAST and HLFSPD, and their inversions select lines of the PLA and cause the counting to be controlled in a desired fashion to provide the desired functioning of circuit 25. The origin of signals FAST and HLFSPD is discussed later.

The SCT clock generation circuit 40 provides the transmit data clock and is similar to circuit 25. It has clocks 1 and 2 provided to flip flops FF20-FF27 from clock generation circuit 41 which is identical to the clock generation circuit 33 described above. The input to clock generator circuit 41 is the same as that to circuit 33, that is, it is the true output from the buffer circuit 26.

Flip flop 20 has its Q output connected to the D input of flip flop 21 and also connected into PLA 42. The remaining flip flops are interconnected in exactly the same way. Each of the flip flops has its Q- output connected into the PLA. The devices selected by the PLA are done so as shown in a conventional manner to get the desired output. In this particular embodiment, signal BELL/RV and its inversion, and signal FAST and its inversion are applied as selection inputs to PLA 42. Exclusive OR circuit 45 provides the exclusive OR output from flip flops FF26 and FF27. Exclusive OR circuit 44 provides the exclusive OR output of flip flops FF21 and FF22. These outputs, in turn, are exclusively ORed by exclusive OR circuit 43 whose output provides the D input to flip flop 20. OR gate 48 receives its inputs from the first two row lines of PLA 42 and OR gate 49 receives the three inputs from the next three lines of PLA 42. NOR gate 46 receives its four inputs from lines 3-6 of PLA 42. AND gates 51 receive their inputs from the clock 1 and OR gates 48 and 49, respectively. AND gates 51 and 52 provide inputs to cross coupled NOR gates 53 and 54. NOR gate 53 provides signal 16SCT- and NOR gate 54 provides signal 16SCT, which are 16 times the frequency of the desired transmitting input signal.

Inputs C1 and C2 shown on FIG. 3B indicate the number of bits in the particular character to be transmitted. That is, in combination, they provide a selection of 8, 9, 10, or 11 bits. Signals C1 and C2 are buffered through buffer circuits 61 and 62, which are identical to buffer circuit 26, with the two outputs and their inversions being applied as selection inputs to PLA 68 of character bit counter 65 shown in FIG. 3C. Toggle flip flops FF35-FF38 provide the counting mechanism. The count is established by addressing the associated PLA 68. Flip flop FF39 provides a "1" output on its Q terminal when a character of the correct bit length has been read in, clocking flip flop 70, the stop bit detect flip flop. The Q- output of stop bit detect flip flop 70 is a "0" when a "start" bit is received via the data input XMTD and XMTD-, the "start" bit also being a "0". A designation of "1" and "0" is completely arbitrary and in this preferred embodiment, a "1" represents a positive voltage and a "0" represents zero volts. these values may be referred to as "true" and "false" and "high" and "low", respectively.

The Q- output of stop bit detect flip flop 70 is a "0" and is gated out by the Q output of flip flop 39. The Q- output of flip flop 70 provides one input to NOR gate 63, enabling that gate for the reception of the output signal 16 DTE-, previously described. At the conclusion of the start bit, the Q output of flip flop FF39 goes to "0", thereby blocking any further transfer on the Q output of the stop bit detect flip flop 70, permitting continued entry of signal IGDTE- through gate 63.

PLA 68 is activated by signals C1 and C2 to provide a character of 8, 9, 10 or 11 bits. PLA 68 provides the logical structure, as connected to flip flops FF35-FF38, to permit those flip flops to count to the selected number of bits. The Q output of flip flop FF39 provides the preset inputs to each of flip flops FF35-FF38 and provides one input to NOR gate 66, whose other input is provided by the signal DTE-. The output of NOR gate 66 provides the clock input to flip flop FF35 whose Q- output provides the clock input to flip flop 36. Flip flops FF37 and FF38 are interconnected in the same fashion. All of flip flops FF35-38 have their Q and Q- outputs connected as shown to PLA 68 to insure that the proper count is reached. The counting of the character bit counter is started by a 0 output from the Q terminal of flip flop FF39, together with a 0 DTE- signal, clocking flip flop FF35. The count continues until the predetermined character bit length is reached, at which time flip flop 39 goes high, providing clocking for stop bit detect flip flop 70.

As mentioned above, the 16 DTE- signal is passed through NOR gate 63 and causes the counting of toggle flip flops FF30-FF33, thereby dividing the input frequency of 16 DTE down to frequency DTE.

The modem of this invention is designed to operate synchronously and asynchronously at various frequencies, depending upon the system with which the modem is compatible. Providing a frequency of approximately 16 times the expected data rate enables the sampling of data near the midpoint of each bit. This is illustrated in FIG. 4 where the input data is shown as signal XMTD and the divided sampling signal is shown as DTE. DTE1 illustrates a possible shift of 29.5% from the center of the bit and DTE2 illustrates a 10.5% shift from the center. These shifts are the result of different input frequencies.

This is an acceptable deviation and signal DTE is used to clock input sampling flip flop 75 of FIG. 3C which has data signal XMTD applied to its J input and signal XMDT applied to its K input. The Q- output of flip flop FF39 is applied as one input to NOR gate 95 which is connected to the preset input of flip flop FF40 which is clocked by the STOP signal. The Q output from flip flop FF40 provides one input to NOR gate 96 whose other input is provided by signal DTE- from the Q output of flip flop 33 of start-stop counter 60, which also provides the J input to flip flop FF41. The output of NOR gate 96 provides the K input to flip flop 41 whose Q output is signal SDTE- and whose Q- output is SDTE.

The Q output of input sampling flip flop 75 provides an input to NOR gate 120 and to NOR gate 121. The other input to NOR gate 121 is the STOP signal. The Q- output of input sampling flip flop 75 provides one input to NOR gate 122 whose other input is provided by the STOP- signal. The output of NOR gate 121 provides the K input to flip flop FF48 and the output from NOR gate 122 provides the J input to flip flop FF48. Flip flop FF48 provides the SSTOP and SSTOP- signals on its Q and Q- outputs, respectively. The sampled DTE and STOP signals are generated therefore by flip flops FF41 and FF48, and associated circuitry, shown as DTE, SCT, SYNC130 in FIG. 2.

SCT clock generation circuit 41 is shown in FIGS. 3A and 3B. Clock generation circuit 41, which is identical to clock generation circuit 33, receives an input from oscillator buffer circuit 26, providing output clocks 1 and 2. Clocks 1 and 2 are provided as clocking inputs to dynamic flip flops FF20-FF27. These flip flops and PLA 42 are interconnected, with associated logic, to provide a pseudo random shift register for providing output signals 16 SCT and 16 SCT-, a frequency of approximately 16 times the expected input data frequency. The frequency is varied by input signal BELL/RV, and its inversion, being applied to PLA 42. Also, FAST input and its inversion may be applied to PLA 42. The Q and Q outputs of flip flops FF20-FF27 are connected to appropriate lines of PLA 42. Exclusive OR circuit 44 provides the exclusive OR function for the outputs of flip flops FF21 and FF22. Exclusive OR circuit 45 provides the exclusive OR function for the outputs of flip flops FF26 and FF27. The outputs of exclusive OR circuits 44 and 45 are inputs to exclusive OR circuit 43, whose output provides the D input to flip flop 20. The output of SCT clock generation circuit 40 is provided through appropriate logic circuits 46-54 as shown with signal 16 SCT being provided from NOR gate 54 and signal 16 SCT being provided from NOR gate 53.

Reference is now directed to FIG. 8 where SCT clock circuit 90 is shown in detail. Flip flips FF55-FF59 divide the input signal 16 SCT from the 16 SCT clock generation circuit 41 by 16, using four of the flip flops, or by 32, using all five of the flip flops. Signal 16 SCT clocks flip flop 55, whose Q output clocks flip flop 56 and so on through flip flop 58. Each of the Q- outputs of flip flops FF55 through FF58 provide inputs to NOR gate 132. Flip flop FF59 is clocked by signal SCTA and its Q input is provided by signal DBTA which is a 600 Hz clock. The Q- input of flip flop 59 has signal DBT- applied. AND gate 131 has signal HLFSPD and signal DBT- applied as inputs and provides the final output to NOR gate 132. NOR gate 132 provides an input to NOR gate 134 and through inverter 133 provides an input to NOR gate 135. Signal 16 SCT- provides the other input to each of NOR gates 134 and 135. NOR gate 134 provides output signal NHSCT and NOR gate 135 provides signal HSCT. The Q- output from flip flop FF58 provides an input to AND gate 137. Signal CSEL- is inverted through inverter 139 and provides the other inputs to AND gate 137. It also provides one input to AND gate 136 whose other input is provided by signal TCLK. AND gates 136 and 137 provide inputs to NOR gate 138 whose output is signal SCT.

FIGS. 3B and 3C detail the structure of FIFO 100. FIFO 100 is made up of three flip flops, FF50, FF51 and FF52, together with supporting logic circuitry. The sampled data input to FIFO 100 comes through NOR gate 120 as signal FIFOIN, inverted through inverter 119 and applied to the J input of flip flop FF52 and not inverted and applied to the K input of that flip flop. Signal FIFOIN also provides an input to each of exclusive OR circuits 105 and 108 and to AND gate 102. Flip flop FF52 is clocked by signal MDTE and its Q- output provides an input to exclusive OR gate 105. The other signals for this exclusive OR gate are signal B0 and its inversion. The output of exclusive OR gate 105 provides the J input to flip flop FF51 and, inverted through inverter 116, provides the K input. The Q- output of flip flop FF51 provides an input to exclusive OR gate 108 whose other inputs are provided by signal B1 and B1-. The output of exclusive OR gate 108 provides an input to the J terminal of flip flop FF50 and, through inverter 118, to the K input of that flip flop. Flip flop FF51 is clocked by the output of NOR gate 112 whose inputs are provided by AND gates 109, 110 and 111. Signals B1 and B0- provide the inputs to NOR gate whose output provides one input to AND gate 111 and is inverted through inverter 107 to provide an input to AND gate 109. Signal MDTE is inverted through inverter 115 and provides an input to each of AND gates 110 and 111. The clocking of flip flop FF51 is directly dependent on the values of signals B1 and B0-.

Flip flop FF50 is clocked by circuit 113 which comprises a NOR gate having three AND gates input with signal MDTE- providing an input to two of those AND gates. Signal HSCT is inverted through inverter 114 and provides an input to two of the AND gates of circuit 113. Signal EMPTY provides an input to one of the AND gates and inverted through inverter 117 provides an input to another one of the AND gates of circuit 113 as shown. The output of inverter 117 also provides an input to AND gate 103. The other input to AND gate 103 is provided by the Q output of flip flop FF50. Signals B0 and B1 provide the inputs to NOR gate 101 and to the output which is the EMPTY signal and which applies an input to AND gate 102. AND gates 102 and 103 provide inputs to NOR gate 104 whose output is signal FIFOUT.

As indicated above, the transmitter buffer provides for various rates of transmission. If the incoming asynchronous data is too fast for the transmission capability of the buffer, stop bits may be removed. If the rate of asynchronous data in is too slow, stop bits may be added. This is accomplished through the interplay between FIFO100, up-down counter 80 and stop-bit insert-delete control 140.

First consider up-down counter 80 which is shown in FIGS. 3B and 3C. Up-down counter 80 comprises flip flops FF42, FF43, FF45 and FF46 and associated control circuitry. Each of the flip flops is preset by signal ETD- from the modem receiver circuit, to be described later. Flip flops FF42 and FF46 are clocked by the signal F UP. Flip flops FF43 and FF45 are clocked by the signal F DOWN. Exclusive OR circuit 86 provides the exclusive OR of signals B0 and B1. The output of exclusive OR circuit 86, and its inversion through inverter 91, provide inputs to exclusive OR circuits 83, 84, 87 and 88. The Q and Q- outputs of flip flops FF42, FF43, FF45 and FF46 provide the other inputs to each of the exclusive OR circuits 83, 84, 87, and 88, respectively. The outputs of exclusive OR circuits 83, 84, 87 and 88 provide the J input, and inverted, the K input to flip flops FF42, FF43, FF45 and FF46, respectively. Exclusive OR circuit 81 provides the exclusive OR function for the outputs of flip flops FF42 and FF43 to provide output signal B0 and, inverted through inverter 82, output signal B0-. Exclusive OR circuit 89 provides the exclusive OR of the outputs of flip flops FF45 and FF46 to provide output signal B1 and, through inverter 94, signal B1-.

FIG. 5 details stop-bit insert-delete control circuit 140. Sample stop signal SSTOP provides the J input to flip flop FF60 and the clock input to flip flop FF61. Signal SSTOP- provides the K input to flip flop FF60. The Q and Q- outputs of flip flop FF60 provide the J and K inputs of flip flop FF61, respectively. Signal HSCT provides the preset input for flip flop FF61. The Q output of flip flop FF61 provides one input to NOR gate 143 whose other input is provided by signal 1/8- from the receiver circuit. The Q output of flip flop FF61 provides the preset input for toggle flip flops FF63 and FF64, while the output of NOR gate 143 provides the preset input for toggle flip flop FF62. The Q- output of flip flop FF64 provides the clock input for flip flop FF63 whose Q- output, in turn, provides the clock input for flip flop FF62. The Q output of each of flip flops FF62-FF64 provide an input for NOR gate 144 whose output provides one input to NOR gate 145. The other input to NOR gate 145 is signal SSTOP- and whose output provides clocking for flip flop FF64.

OR gate 146 has the output of NOR gate 144 as one input and the J output from flip flop FF61 as its other input. The output of OR gate 146 provides one input to NAND gate 147 whose other input is provided by signal B1. The output of NAND gate 147 is signal DELETE- which is inverted through inverter 148 and provides one input to NOR gate 151 which is cross coupled with NOR gate 149. The output of NOR gate 151 provides one input to NOR gate 152 whose other input is provided by signal EMPTY, the output of NOR gate 152 being signal ADD- which is inverted and provides one input to exclusive OR circuit 153. The other inputs to exclusive OR circuit 153 are signals NHSCT, DELETE- and HSCT. The output of circuit 153 provides one input to OR gate 152 whose other input is signal SSTOP-. The output of OR gate 142, together with signal SDTE-, provide the inputs to NAND gate 141 whose output is signal MDTE, providing the clocking for toggle flip flop F60.

FIG. 9 illustrates the development of the F UP and F DOWN signals which control the operation of the UP DOWN counter 80. Signal MDTE is inverted through inverter 177 and provides one input to NOR gate 179. Signals B1 and B0- provide the inputs to AND gates 178. Signals S STOP and ADD- provide the inputs to AND gate 180. AND gates 178 and 180 provide the inputs to NOR gate 179 whose output is signal F UP.

Signal HSCT is inverted through inverter 181 and provides one input to NOR gate 182. Signal EMPTY provides another input to NOR gate 182. Signals S STOP and DELETE- inputs to AND gate 183 whose output provides another input to NOR gate 182. The output of NOR gate 182 is signal F DOWN.

FIFO 100, shown in detail in FIG. 3C, holds none, 1, 2, or 3 bits. Its contents are controlled by UP DOWN counter 80 and STOP-BIT-INSERT-DELETE control 140. Control circuit 140 receives the signal 1/8- from the receiver circuit, indicating that, when high, the circuit may provide an additional stop bit for every 8 characters. If the signal is low, then one stop may be provided for every four characters. When a stop bit is present, the extra stop bit may be added or a stop bit may be deleted, depending upon the contents of the FIFO 100. Control circuit 140 keeps track of when a stop bit was set, through its three toggle flip flops FF62-FF64. UP DOWN counter 80 is a gray code type counter which is controlled in its count by the state of signals F DOWN and F UP which in turn are controlled by the various signals shown in FIG. 9. If the incoming data signal rate is too high, then a stop bit will be inserted, at a point dependent upon the incoming rate. If the incoming data rate is too slow, stop bits will be removed. The UP DOWN counter 80 controls setting of FIFO stages and permits additions or deletions, depending upon the status of the FIFO.

FIG. 6 illustrates the application of external inputs OVSPD, S/A, PD, BELLRV. Also, 600 BPS input is applied through buffer circuit 171 which is identical to buffer circuits 26, (as are buffer circuits 172-175), providing a false output through inverter 164 to AND gate 166 and to NOR gate 163. The overspeed signal (OVSPD) is applied through buffer 172. Using the false output as an input to NOR gate 167 and through inverter 161 as an input to AND gate 162. The synchronous/asynchronous signal (S/A) is applied through buffer circuit 173, using the true output as an input to NOR gate 156 and through inverter 157 to NOR gate 158. Also, signal S/A provides an input to NOR gate 167. Signal PD is applied through buffer circuit 174, using its true output to provide one input to NOR gate 156 and the second input to NOR gate 160. The output from NOR gate 160 is signal PE. Externally applied signal BELL/RV is buffered through buffer circuit 175, using the true output to apply the final input to NOR gate 156 whose output is signal V22 and to NOR gate 159 whose output is signal VAD. Signal VAD also provides an input to AND gate 162 whose output provides an input to NOR gate 163. The output from NOR gate 158 provides another input to gate 163 and signal V22 provides the final input, the output being signal HLFSPD. The output from NOR gate 167 is signal FAST.

This logic simply provides the signals that are used to control various portions of the transmit buffer.

Referring now to FIG. 7A, an important selection circuit is shown with signal synchronous/asynchronous (S/A) being of prime importance. That is, when that signal is high, then a synchronous mode has been selected and all of the circuitry heretofore described is bypassed. As shown, signal S/A and signal XMTD provide inputs to AND gate 181 while signal S/A- and signal FIFOUT provide inputs to AND gate 180. AND gates 180 and 181 provide the inputs to NOR gate 182 whose output signal S DATA- either comes directly from XMTD when S/A is high or from FIFO 100 when S/A is low. Depending upon the input modem protocol selection, signal SDATA- will be scrambled or will be sent unscrambled through a 17 stage register made up of flip flops FF70-FF87. Signal PE, the output from NOR gate 160, is inverted through inverter 183 and is gated through NOR gate 184, providing an input to NOR gate 185 and to AND gate 186. Signal SDATA- provides the other input to NOR gate 185 and to AND gate 186 whose output provide the input to NOR gate 187. The output of inverter 183 provides an input to NOR gate 188 whose other input, on line 207, comes from the output of exclusive OR circuit 206. The output of NOR gates 187 and 188 provide the inputs to NOR gate 189 and to AND gate 190. Gates 189 and 190 provide the inputs to NOR gate 191. These series exclusive OR circuits then enable signal SDATA-, to be applied through inverter 193 to the J input of flip flop 70 and directly to the K input. The Q and Q- outputs of flip flop FF70 are connected to the J and K inputs, respectively, of flip flop FF71. The interconnection between the remaining flip flops FF72 through FF87 are exactly the same.

Exclusive OR circuit 206 provides the exclusive OR function of the outputs from flip flop FF84 and flip flop FF87. The output of exclusive OR circuit 206 is gated into the logic described above the incoming data is scrambled in the pseudo random shift register formed by flip flops FF70-FF87, depending upon the state of signal PE, which is the pseudo random enable. If PE is high, the signal is scrambled by the contents of the 14th and 17th flip flop. If low, there is no scrambling. The reason for scrambling for some of the modem protocols is to prevent a long period of time without any signal transition that may disrupt the operation of phase lock loops used in the modem. In the unlikely event that such a long period of time without transitions occurs even using the scrambler technique, counter 208 is employed to compensate for such an eventuality. Counter 208 comprises flip flops FF88-FF95. Signals HLFSPD and its inversion are applied to exclusive OR circuit 194, together with signals DBT and SCTA to provide signal SCMCK at the output of exclusive OR circuit 194. Signal SCMCK provides the clock input to toggle flip flop FF88 whose Q output provides the clock input to toggle flip flop FF89 and so on through toggle flip flop FF94. The Q and Q- output of flip flop 94 provide the J and K inputs, respectively, for flip flop FF95. Flip flop FF95 is also clocked by signal SCMCK. The Q output of flip flop FF95 provides one input to NAND gate 192 whose other input is provided by the Q output of flip flop FF70 of the scrambler. The output of NAND gate 192 provides the preset input for toggle flip flops FF88-FF94. The Q- output of flip flop FF94 provides signal FIXT which is input to NOR gate 184 whose other input, as indicated earlier, is the pseudo random enable signal, inverted.

Counter 208 monitors data through the scrambler by looking at the Q output of flip flop FF70, the first of the flip flops in the chain. NAND gate 192 presets the flip flops FF88-FF94. If a continual string of marks (1's) from FF70 are present, the output of NAND gate 192 is a 0, permitting the counting up of flip flops FF88-FF94. When FF94 is set, then the signal FIXT causes an inversion of the next bit going into the scrambler. Also, the gate signal of flip flop FF95 changes to cause presetting of the counter. In this manner, when counter 208 fills with a series of 1's from the scrambler, the next bit to the scrambler is forced to be a space to conform with certain of the protocols for preventing a remote data loop back.

FIG. 7B illustrates the phase and code logic which involves circuitry for determining the particular phase for a given modem protocol. That is, two bits of data (dibit) select four different phases. This selection for the various protocols is set out below in Table 1.

                  TABLE 1
    ______________________________________
    Bell                  V22
    ______________________________________
    Originate
             (1200 Hz)    Originate
                                   (1200 Hz)
    Answer   (2400 Hz)    Answer   (2400 Hz)
    ______________________________________
    Dibit Phase     (degrees) Dibit
                                   Phase   (degrees)
    ______________________________________
    00    +90                 00   +270
    01    0                   01   +180
    11    +270                11   +90
    10    +180                10   0
    ______________________________________
    RV
    Originate (2250 Hz)
                      Answer (1150 Hz)
    Dibit Phase     (degrees) Dibit
                                   Phase   (degrees)
    ______________________________________
    00    +270                00   +90
    01    +90                 01   +270
    11    +180                11   +180
    10    0                   10   0
    ______________________________________