PARTICULAR ALGORITHMIC FUNCTION ENCODING

Shared galois field multiplier

6701336

Abstract

Two types of shared-field multipliers for performing multiplications on field elements of different sizes are presented. One type uses a "cyclic" Galois field GF(2.sup.m), that is, a Galois field GF(2.sup.m) generated by an irreducible polynomial x.sup.m +x.sup.m-1 +x.sup.m-2 + . . . +x+1, and the other type uses a composite field structure. Each shared-field multiplier includes computation circuitry for receiving field elements as inputs, the computation circuitry being responsive to a control signal to perform computations based on the inputs having a first size to produce an output of the first size, or to perform computations based on the inputs having a second, different size to produce an output of the second size.


Claims

What is claimed is:

1. A Galois field multiplier comprising:

computation circuitry for receiving an input;

the computation circuitry being responsive to a control signal to perform computations based on the input having a first size to produce an output of the first size, or to perform computations based on the input having a second, different size to produce an output of the second size, the computation circuitry comprising shifting circuitry only for performing a cyclic shifting of bits of the input, the shifting circuitry comprising a single shifting circuit for use with both the input having the first size and the input having the second size.

2. The Galois field multiplier of claim 1, wherein the computation circuitry comprises:

select circuitry, responsive to the control signal, for configuring the computation circuitry.

3. The Galois field multiplier of claim 2, wherein the input is an element of a cyclic Galois field and wherein the shifting circuitry is coupled to and responsive to the select circuitry.

4. The Galois field multiplier of claim 3, wherein the first size is 10 bits and an associated input is an element of the cyclic Galois field GF(2.sup.10).

5. The Galois field multiplier of claim 4, wherein the cyclic Galois field GF(2.sup.10) is generated by the irreducible polynomial r.sub.10 (x)=1+x+x.sup.2 +X.sup.3 +x.sup.4 +x.sup.5 +x.sup.6 +x.sup.7 +x.sup.8 +x.sup.9 +x.sup.10.

6. The Galois field multiplier of claim 3, wherein the second size is 12 bits and an associated input is an element of the cyclic Galois field GF(2.sup.12).

7. The Galois field multiplier of claim 6, wherein the cyclic Galois field GF(2.sup.12) is generated by the irreducible polynomial r.sub.12 (x)=1+x+x.sup.2 +X.sup.3 +x.sup.4 +x.sup.5 +x.sup.6 +x.sup.7 +x.sup.8 +x.sup.9 +x.sup.10 +x.sup.11 +x.sup.12.

8. The Galois field multiplier of claim 3, wherein the shifting circuitry further comprises:

a plurality of shifting units connected in parallel, a first one of the shifting units for receiving input values for input and cyclically shifting the input values, each next consecutive one of the other shifting units receiving a cyclically shifted output from a previous one of the shifting units and cyclically shifting the cyclically shifted output.

9. The Galois field multiplier of claim 8, wherein the input is a first input and the computation circuitry further receives a second input of the same size as the first input and has second input values, further comprising:

a plurality of AND gates, each of the AND gates coupled to a one of the second input values of the second input, a least significant one of the AND gates coupled to the received input values of the input, a next most significant one of the AND gates coupled to cyclically shifted output of the first one of the shifting units, and each next most significant one of the AND gates coupled to and receiving a cyclically shifted output from the next consecutive one of the other shifting units to form product values; and

a plurality of Galois field adders, one adder for each of the input values, each adder for receiving one of the product values for a corresponding one of the input values from each of the AND gates, for producing a set of multiplier output values of the output.

10. The Galois field multiplier of claim 2, wherein the input is a first input and the computation circuitry further receives a second input of the same size as the first input, wherein the first and second inputs are elements of an extended Galois field GF((2.sup.m).sup.k) over a field GF(2.sup.m).

11. The Galois field multiplier of claim 10, wherein m=5 and k=2.

12. The Galois field multiplier of claim 10, wherein m=6 and k=2.

13. The Galois field multiplier of claim 10, wherein the computation circuitry is implemented to compute the product of the first and second inputs using the Karatsuba-Ofman algorithm and further comprises:

a plurality of base multipliers coupled to the control line, each of the base multipliers for performing multiplications over the field GF(2.sup.m).

14. The Galois field multiplier of claim 13, wherein each of the plurality of base multipliers includes base multiplier computation circuitry for receiving base multiplier inputs to produce base multiplier outputs, the base multiplier computation circuitry being responsive to the control signal.

15. An encoder comprising:

a plurality of field multipliers for receiving code word symbol inputs and multiplying the received code word symbol inputs by generator polynomial constant values; and

wherein each of the plurality of field multipliers includes computation circuitry for receiving the code word symbol inputs, the computation circuitry being responsive to a control signal to perform computations based on the code word symbols inputs having a first size to produce an output of the first size, or to perform computations based on the code word symbol inputs having a second, different size to produce an output of the second size.

16. The encoder of claim 15, wherein the first and second sizes comprise Galois field sizes.

17. The encoder of claim 16, wherein the first size comprises 10 bits and the second size comprises 12 bits.

18. The encoder of claim 15, wherein the code word symbol inputs are derived based on an irreducible polynomial.

19. The encoder of claim 18, wherein the irreducible polynomial contains only coefficient values of "1".

20. The encoder of claim 15, wherein the computation circuitry comprises:

select circuitry, responsive to the control signal, for configuring the computation circuitry.

21. The encoder of claim 20, wherein each code word symbol input comprises elements of a cyclic Galois field and wherein the computation circuitry further comprises:

shifting circuitry, coupled to and responsive to the select circuitry, for performing a cyclic shifting of bits of the code word symbol input.

22. The encoder of claim 15, wherein the first size is 10 bits and a code word symbol input is an element of a cyclic Galois field GF(2.sup.10).

23. The encoder of claim 22, wherein the cyclic Galois field GF(2.sup.10) is generated based on irreducible polynomial r.sub.10 (x)=1+x+x.sup.2 +x.sup.3 +x.sup.4 +x.sup.5 +x.sup.6 +x.sup.7 +x.sup.8 +x.sup.9 +x.sup.10.

24. The encoder of claim 15, wherein the second size is 12 bits and a code word symbol input is an element of a cyclic Galois field GF(2.sup.12).

25. The encoder of claim 24, wherein the cyclic Galois field GF(2.sup.12) is generated based on an irreducible polynomial r.sub.12 (x) 1+x+x.sup.2 +x.sup.3 +x.sup.4 +x.sup.5 +x.sup.6 +x.sup.7 +x.sup.8 +x.sup.9 +x.sup.10 +x.sup.11 +x.sup.12.

26. The encoder of claim 15, wherein the computation circuitry comprises:

a plurality of shifting units connected in parallel, a first one of the shifting units for receiving input values for the code word symbol input and cyclically shifting the input values, each next consecutive one of the shifting units receiving a cyclically shifted output from a previous one of the shifting units and cyclically shifting a cyclically shifted output.

27. The encoder of claim 26, wherein the input values comprise a first input and the computation circuitry further receives a second input of the same size as the first input and has second input values, the computation circuitry further comprising:

a plurality of AND gates, each of the AND gates coupled to one of the second input values of the second input, a least significant one of the AND gates coupled to received input values of an input, a next most significant one of the AND gates coupled to cyclically shifted output of the first one of the shifting units, and each next most significant one of the AND gates coupled to and receiving a cyclically shifted output from a next consecutive one of the other shifting units to form product values; and

a plurality of Galois field adders, one adder for each of the input values, each adder for receiving one of the product values for a corresponding one of the input values from each of the AND gates, for producing a set of multiplier output values of the output.

28. A decoder comprising:

functional units for performing decoding computations;

wherein at least one of the functional units employs a plurality of field multipliers for performing multiplication associated with at least one of the decoding computations; and

wherein each of the plurality of field multipliers includes computation circuitry for receiving inputs, the computation circuitry being responsive to a control signal to perform computations based on the inputs having a first size to produce an output of the first size, or to perform computations based on the inputs having a second, different size to produce an output of the second size.

29. The decoder of claim 28, wherein the multiplication is a general multiplication of two polynomial inputs.

30. The decoder of claim 29, wherein the at least one of the decoding computations is a Berlekamp-Massey computation for computing error locator polynomials.

31. The decoder of claim 29, wherein the at least one of the decoding computations is a Euclidean algorithm for computing error locator polynomials.

32. The decoder of claim 28, wherein the multiplication is a constant multiplication of a polynomial by a constant.

33. The decoder of claim 32, wherein the at least one of the decoding computations is a syndrome computation.

34. The decoder of claim 32, wherein the at least one of the decoding computations is a root finding computation.

35. The decoder of claim 28, wherein the first and second sizes comprise Galois field sizes.

36. The decoder of claim 28, wherein the first size comprises 10 bits and the second size comprises 12 bits.

37. A Galois field multiplier comprising:

computation circuitry for receiving an input;

the computation circuitry being responsive to a control signal to perform computations based on the input having a first size to produce an output of the first size, or to perform computations based on the input having a second, different size to produce an output of the second size, the input comprising an element of a cyclic Galois field;

the computation circuitry further comprising:

select circuitry, responsive to the control signal, for configuring the computation circuitry; and

shifting circuitry, coupled to and responsive to the select circuitry, for performing a cyclic shifting of bits of the input, the shifting circuitry including a plurality of shifting units connected in parallel, a first one of the shifting units for receiving input values for the input and cyclically shifting the input values, each next consecutive one of the other shifting units receiving a cyclically shifted output from a previous one of the shifting units and cyclically shifting cyclically shifted output.

38. The Galois field multiplier of claim 37, wherein the input is a first input and the computation circuitry further receives a second input of the same size as the first input and has second input values, further comprising:

a plurality of AND gates, each of the AND gates coupled to a one of the second input values of the second input, a least significant one of the AND gates coupled to the received input values of the input, a next most significant one of the AND gates coupled to cyclically shifted output of the first one of the shifting units, and each next most significant one of the AND gates coupled to and receiving a cyclically shifted output from the next consecutive one of the other shifting units to form product values; and

a plurality of Galois field adders, one adder for each of the input values, each adder for receiving one of the product values for a corresponding one of the input values from each of the AND gates, for producing a set of multiplier output values of the output.

39. A multiplier for multiplying elements of a finite field, comprising:

multiple shifting units, each of the multiple shifting units producing an output having a first size or an output having a second size; and

logic elements which combine outputs of the multiple shifting units;

wherein each of the multiple shifting units comprises:

a shifting circuit which cyclically shifts inputs to the multiplier based on a size of the finite field, the shifting circuit including selecting circuitry to configure the shifting circuitry to accommodate either the first size or the second size, the selecting circuitry comprising a multiplexer and an AND gate that are responsive to a control signal indicative of the first size or the second size.

40. The multiplier of claim 39, wherein:

inputs to the shifting circuit are defined as a.sub.0.sup.i, a.sub.1.sup.i, a.sub.2.sup.i, a.sub.3.sup.i, a.sub.4.sup.i, a.sub.5.sup.i, a.sub.6.sup.i, a.sub.7.sup.i, a.sub.8.sup.i, a.sub.9.sup.i, a.sub.10.sup.i, a.sub.11.sup.i and a.sub.12.sup.i ;

outputs to the shifting circuit are defined as a.sub.0.sup.o, a.sub.1.sup.o, a.sub.2.sup.o, a.sub.3.sup.o, a.sub.4.sup.o, a.sub.5.sup.o, a.sub.6.sup.i, a.sub.7.sup.o, a.sub.8.sup.o, a.sub.9.sup.o, a.sub.10.sup.o, a.sub.11.sup.o and a.sub.12.sup.0 ; and

cyclic shifting performed by the shifting circuit comprises:

when the control signal indicates the first size, a.sub.11.sup.o and a.sub.12.sup.o outputs are not used and a.sub.10.sup.i input is connected to a.sub.0.sup.o output via the multiplexer; and

when the control signal indicates the second size a.sub.12.sup.i input is connected to a.sub.0.sup.o output via the multiplexer; a.sub.10.sup.i input is shifted to a.sub.11.sup.o output via the AND gate, and a.sub.11.sup.i input is connected to a.sub.12.sup.o output.

41. The multiplier of claim 39, wherein the first size comprises 10 bits and the second size comprises 12 bits.

42. The multiplier of claim 39, wherein the multiplier is operable on cyclic Galois fields comprising a 10-bit field GF (2.sup.10) and a 12-bit field GF (2.sup.12) the 10-bit field being generated based on an irreducible polynomial comprising:

r.sub.10 (x)=1+x+x.sup.2 +x.sup.3 +x.sup.4

+x.sup.5 +x.sup.6 +x.sup.7 +x.sup.8 +x.sup.9 +x.sup.10, and

the 12-bit field being generated based on an irreducible polynomial comprising:

r.sub.12 (x)=1+x+x.sup.2 +x.sup.3 +x.sup.4 +x.sup.5 +x.sup.6 +x

7+x.sup.8 +x.sup.9 +x.sup.10 +x.sup.11 +x.sup.12.


Description

BACKGROUND OF THE INVENTION

The invention relates generally to error correcting systems and, more particularly, to error correcting systems which perform Galois field multiplication during encoding and decoding processes.

As storage systems migrate to longer sector sizes, error correcting codes (ECC) with longer block lengths are needed. One way to achieve format efficiency is to use different field element (e.g., symbol) sizes--smaller symbols for shorter sectors and larger symbols for longer sectors. Symbols of different sizes can share some frequently used field operations. For example, addition may be performed for differently sized symbols using exclusive-OR adders. Galois field multiplication, which multiplies two elements in a Galois field, is frequently used in error correction encoding and decoding hardware, such as Reed-Solomon encoders or decoders, but requires dedicated multiplier hardware for each different symbol size. Consequently, error correction systems having one type of Galois field multiplier to accommodate a symbol/sector size are incompatible with alternative symbol/sector sizes. Some well-known field multipliers are described in Berlekamp, Algebraic Coding Theory, Academic Press, 1968, at pps. 47-48, as well as Peterson and Weldon, Error Correction Codes, 2d Edition, MIT Press, 1972, at pps. 170-182.

SUMMARY OF THE INVENTION

This invention features a Galois field multiplier that can operate on field elements of more than one size.

Generally, in one aspect of the invention, a Galois field multiplier includes computation circuitry for receiving an input, the computation circuitry being responsive to a control signal to perform computations based on the input having a first size to produce an output of the first size, or to perform computations based on the input having a second, different size to produce an output of the second size.

Embodiments of the invention may include one or more of the following features.

The computation circuitry can include select circuitry, responsive to the control signal, for configuring the computation circuitry.

In one embodiment, the input can be an element of a Galois field GF(2.sup.m) of a cyclic type ("cyclic Galois field"), that is, having a generator polynomial of the form x.sup.m +x.sup.m-1 +x.sup.m-2 + . . . +x+1, and the computation circuitry can further include shifting circuitry, coupled to and responsive to the select circuitry, for performing a cyclic shifting of bits of the input.

The first size can be 10 bits and the associated input an element of the cyclic Galois field GF(2.sup.10). The second size can be 12 bits and the associated input an element of the cyclic Galois field GF(2.sup.12). The shifting circuitry can further include a plurality of shifting units connected in parallel, a first one of the shifting units for receiving input values for the input and cyclically shifting the input values, each next consecutive one of the other shifting units receiving a cyclically shifted output from a previous one of the shifting units and cyclically shifting the cyclically shifted output.

The input can be a first input and the computation circuitry can receive a second input of the same size as the first input. The field multiplier can further include: a plurality of AND gates, each of the AND gates coupled to a value of the second input, a least significant one of the AND gates coupled to the received input values of the first input, a next most significant one of the AND gates coupled to cyclically shifted output of the first one of the shifting units, and each next most significant one of the AND gates coupled to and receiving a cyclically shifted output from the next consecutive one of the other shifting units to form product values; and a plurality of Galois field adders, one adder for each input value, each adder for receiving one of the product values for a corresponding one of the input values from each of the AND gates, for producing a set of multiplier output values of the output.

In another embodiment, the input can be a first input and the computation circuitry can receive a second input having the same size as the first input. The first and second inputs of the Galois field multiplier can each be elements of an extended Galois field GF((2.sup.m).sup.k) over a field GF(2.sup.m). In this alternative embodiment, the computation circuitry can be implemented to compute the product of the first and second inputs using the Karatsuba-Ofman algorithm and can further include a plurality of base multipliers coupled to the control line, each of the base multipliers for taking the multiplications over the field GF(2.sup.m). Each of the plurality of base multipliers can include base multiplier computation circuitry for receiving base multiplier inputs to produce base multiplier outputs, the base multiplier computation circuitry being adapted to respond to the control signal.

The shared-field multiplier of the invention offers several advantages. First, it performs the job of at least two dedicated multiplier circuits with reduced hardware complexity by exploiting common attributes of multiplication operations in different fields. Second, the shared-field multiplier allows ECC systems to satisfy different sector length requirements with flexibility and efficiency. ECC systems designed for a first symbol size may be compatible with and can therefore be upgraded to a second symbol size as sector and ECC block formats change.

Other features and advantages of the invention will be apparent from the following description taken together with the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a single field multiplier having shifting units for cyclically shifting inputs.

FIG. 2 is a detailed diagram of the shifting units of FIG. 1.

FIG. 3 is table depicting logic complexity and delay associated with the single field multiplier shown in FIG. 1.

FIG. 4 is a shared field multiplier having shared shifting units for cyclically shifting as inputs either 10-bit or 12-bit symbols.

FIG. 5 is a detailed diagram of the shared shifting units of FIG. 1.

FIG. 6 is table depicting logic complexity and delay associated with the shared-field multiplier shown in FIG. 4.

FIG. 7 is a schematic diagram of a composite shared field multiplier.

FIG. 8 is a depiction of the multiplication of two GF(2.sup.5) field elements.

FIG. 9 is a depiction of the multiplication of two GF(2.sup.6) field elements.

FIG. 10 is a block diagram of the base multiplier shown in FIG. 7.

FIGS. 11-18 illustrate in detail the various logic circuits of the base multiplier shown in FIG. 7.

FIG. 19 is a schematic diagram of the constant multiplier of the shared-field multiplier shown in FIG. 7.

FIGS. 20-21 are tables depicting the gate count and delay associated with the 10-bit and the 12-bit composite field multipliers, respectively.

FIG. 22 is a block diagram of an exemplary encoder which includes a plurality of field multipliers that may be implemented as the shared field multiplier of either FIG. 3 or FIG. 7.

FIG. 23 is a block diagram of an exemplary decoder having functional units which may perform Galois field multiplication using the shared field multiplier of either FIG. 4 or FIG. 7.

DETAILED DESCRIPTION

Referring to FIG. 1, a single field multiplier 10 designed for the Galois field GF(2.sup.m) is used to perform multiplication operations on field elements, such as error correction code symbols. The single field multiplier 10 receives first input values (or multiplicand) a.sub.0 through a.sub.m 12, at a first one of a plurality of parallel-connected consecutive shifting units ("SU") SU.sub.1, SU.sub.2, SU.sub.3, . . . , (or more generally, "shifting circuitry" 14). The first SU, SU.sub.1, shifts the received input values by one place. Each subsequent, consecutive one of the shifting units 14 then shifts previously shifted input values received from a previous shifting unit by one place. A set of AND logic circuits 16 for ANDing the first input values with a second input or second input values (multiplier) b.sub.0 through b.sub.m are also provided. Each of the AND gates 16 is coupled to and therefore corresponds to a different value of the second input, from least significant to most significant. A first one of the AND gates 16 corresponding to the least significant second input value (b.sub.0) is coupled to each of the received first input values. A next most significant one of the AND gates 16 having b.sub.1 as input is coupled to shifted first input values as provided at the output of the first SU, SU.sub.1, and each next most significant one of the AND gates 16 is similarly coupled to the output of a corresponding next consecutive one of the shifting units in the shifting circuitry 14. The results of each AND circuit 16 for each of the input values are exclusive-ORed with the results of every other AND circuit 16 for corresponding ones of the input values by XOR circuits 20 to produce output values c.sub.0 through c.sub.m 18. Although the multiplier is an m-bit field multiplier, for reasons which will be made apparent in the discussion to follow, it requires m+1 input/output lines (as shown).

The single field multipler 10 has a cyclic property, that is, it operates on a GF(2.sup.m) field generated by an irreducible polynomial of the form x.sup.m +x.sup.m-1 +x.sup.m-2 + . . . +x.sup.2 +x+1. These cyclic-type fields will be referred to herein as "cyclic Galois fields". This type of "cyclic" single field multiplier is described in a co-pending U.S. application Ser. No. 08/786,894, entitled "Modified Reed-Solomon Error Correction System Using (W+I+1)-Bit Representations of Symbols of GF(2.sup.W+I)," in the name of Weng et al., incorporated herein by reference. For further discussion of fields of the cyclic type, reference may be had to a paper by Jack Keil Wolf entitled, "Efficient Circuits for Multiplying in GF(2.sup.m) for Certain Values of m," Discrete Mathematics 106/107, Elsevier Science Publishers B.V. 1992, at pps. 497-502. For a discussion of cyclic codes and their properties, see pages 206-268 of the above-referenced book by Peterson and Weldon.

Two fields which belong to the cyclic class of field multipliers are GF(2.sup.10) and GF(2.sup.12). The 10-bit field GF(2.sup.10) can be generated by the irreducible polynomial

r.sub.10 (x)=1+x+x.sup.2 +x.sup.3 +x.sup.4 +x.sup.5 +x.sup.6 +x.sup.7 +x.sup.8 +x.sup.9 +x.sup.10 (1)

and the 12-bit field GF(2.sup.12) can be generated by the irreducible polynomial

r.sub.12 (x)=1+x+x.sup.2 +x.sup.3 +x.sup.4 +x.sup.5 +x.sup.6 +x.sup.7 +x.sup.8 +x.sup.9 +x.sup.10 +x.sup.11 +x.sup.12. (12)

Every element in the field GF(2.sup.m) (where m=10, 12) can be represented by two m+1-bit symbols, for example, A.sub.1 =(a.sub.1,0, a.sub.1,1, .sub.. . . a.sub.m,m-1, 0) and A.sub.2 =(a.sub.2,0, a.sub.2,1, . . . , a.sub.2,m-1, 1), such that the compliment of A.sub.1 is equal to A.sub.2, and vice versa. If two such elements in the field GF(2.sup.m) are represented as A(x)=sum(i=0, . . . , l)a.sub.i x.sup.i and B(x)=sum(i=0, . . . , m) b.sub.i x.sup.i, then the multiplication of the elements A(x) and B(x) may be expressed as

A(x)B(x)mod(x.sup.m+1 +1). (3)

Thus, for i=0, Eq. (3) is reduced to x.sup.0 [a.sub.0 +a.sub.1 x+a.sub.2 x.sup.2 + . . . , +a.sub.9 x.sup.9 +a.sub.10 x.sup.10 ]*b.sub.o. For i=1, Eq. (3) becomes x[a.sub.0 +a.sub.1 x+a.sub.2 x.sup.2 + . . . +a.sub.9 x.sup.9 +a.sub.10 x.sup.10 ]*b.sub.1 mod(x.sup.m+1 +1), which can be represented as [a.sub.0 x+a.sub.1 x.sup.2 +a.sub.2 x.sup.3 + . . . +a.sub.9 x.sup.10 +a.sub.10 x.sup.11 ]*b.sub.1 mod(x.sup.m+1 +1) and is equal to [a.sub.10 +a.sub.0 x+a.sub.1 x.sup.2 +a.sub.2 x.sup.3 + . . . +a.sub.9 x.sup.10 ]*b.sub.1. Therefore, one cyclic shift of A(x) is xA(x), or (a.sub.10, a.sub.0, a.sub.1, . . . , a.sub.9), two cyclic shifts is x.sup.2 A(x), or (a.sub.9, a.sub.10, a.sub.o, a.sub.1, . . . a.sub.8), and so forth.

Another way of representing the product A(x)*B(x), then, is as b.sub.o A(x)+b.sub.1 xA(x)+b.sub.2 x.sup.2 A(x)+ . . . +b.sub.10 x.sup.10 A(x). Still referring to FIG. 1, the first product term "b.sub.o A(x)" has no shifts; the second product term "b.sub.1 xA(x)" corresponds to one shift of A(x) as performed by SU.sub.1 ; the third product term "b.sub.2 x.sup.2 A(x)" corresponds to two shifts of A(x) as performed by SU.sub.2 ; and each next term corresponds to a next higher shift number, with the final product term "b.sub.10 x.sup.10 A(x)" corresponding to ten shifts of A(x), as performed by SU.sub.10.

Referring to FIG. 2, the shifting circuitry 14 corresponding to each of the identical shifting units SU.sub.1, SU.sub.2, . . . , SU.sub.m-1, SU.sub.m, is shown. The shifting circuitry 14 has shifting unit input values 22 and shifting output values 24 interconnected by cross-connect lines 26. As can be seen from the figure, each of the inputs values a.sub.o through a.sub.m (where a.sub.o, a.sub.2, a.sub.3, . . . , a.sub.m may be bits of a field element, e.g., code word symbol or polynomial coefficient) "shifts" one place to a next higher position (i.e., next MSB position), until the mth input value, which cyclically shifts to the lowest (or LSB) position. For example, the shifting unit input value a.sub.0 is connected to the shifting unit output value a.sub.1 (an output of the shifting unit, but an input to the subsequent shifting unit), and the shifting input value a.sub.1 is similarly shifted to the shifting unit output value a.sub.2. The last shifting unit input value a.sub.m is cyclically shifted to the shifting unit output value a.sub.o. Consequently, if the shifting unit 14 in FIG. 2 is the first unit, SU.sub.1, then the once shifted A(x) provided by SU.sub.1 to SU.sub.2 is again shifted by the second unit SU.sub.2. That is, the a.sub.o and a.sub.m values that were shifted to a.sub.1 and a.sub.0, respectively, by SU.sub.1, are now shifted to a.sub.2 and a.sub.1, respectively, by SU.sub.2.

The logic gate (XOR, AND) count and associated gate delay for both a 10-bit (m=10) and a 12-bit (m=12) implementation of the single field multiplier 10 (FIG. 1) are illustrated in FIG. 3. For a 10-bit implementation, the total number of gates (XOR and AND gates) is 231. The associated delay is 5. For the 12-bit implementation, the total number of gates is 325 and the associated delay is 5.

Referring to FIG. 4, a shared field multiplier 30 shared by 10-bit and 12-bit fields is shown. As the shared field multiplier 30 includes many of the same components included in the single field multiplier 10 of FIG. 1, like reference numerals are used to indicate like elements. In contrast to the single field multiplier 10, which can only be used for one particular field, the shared-field multiplier 30 is adapted for control by a control line 32, which directs the multiplier 30 to operate on a first symbol size, e.g., 10-bits, or a second symbol size, e.g., 12-bits. The control line 32 is user-set (via, e.g., external control software, not-shown) to a predetermined position corresponding to the desired symbol size. In the present embodiment, one predetermined position selects a 10-bit symbol size and an alternate position selects a 12-bit symbol size. For each position or setting, the control line 32 controls the selection of circuitry within shared shifting units SU.sub.1, SU.sub.2, SU.sub.3, . . . , SU.sub.12 34, referred to collectively as "shared shifting circuitry".

With reference to FIG. 5, each shared shifting unit 34 includes a first logic device 40 shown as a multiplexer (MUX) and a second logic device 42 shown as an AND gate. Collectively, these logic devices are referred to as select circuitry 44. The select circuitry 44 is coupled to ones of the shared shifting unit's internal cross-connect (shifting) lines to direct the selection of shifting operations for each symbol size. Essentially, the select circuitry 44 configures the SU to either a 10-bit SU or as 12-bit SU in accordance with the control signal 32.

The MUX 40 receives as inputs a.sub.10 and a.sub.12, and the control line 32 as a select line. The output of the MUX 40 is connected to a.sub.o. The input a.sub.10 is also an input to the AND gate 42, which has as a second input the control line 32. When the control line 32 is in a first state (position "1", corresponding to a logic "0", for 10-bit), a.sub.11 -a.sub.12 are not used and a.sub.10, is connected to a.sub.0. When the control line 32 is in a second state (position "2", corresponding to a logic "1", for 12-bit), the a.sub.12 input is connected to the a.sub.o output. The a.sub.10 input is shifted to the a.sub.11 output via AND gate 42. The a.sub.11 input is connected to the a.sub.12 value at the output of the shared shifting unit 14.

Thus, by replacing the shifting units 14 in FIG. 1 with the shared shifting units 34 controlled by the control line 32 of FIG. 4, a shared field multiplier for both fields GF(2.sup.10) and GF(2.sup.12) is obtained. The total gate count and delay needed for the shared-field multiplier 30 of FIG. 4 is depicted in FIG. 6. In comparing the shared field multiplier 30 to the single 12-bit field multiplier 10, it can be appreciated that the gate count increases by only an additional twelve AND gates and twelve multiplexers (MUX), that is, one extra AND gate and MUX for each of the SUs, and the total delay is increased by one extra MUX delay. Therefore, the total increase in gate count for the share field multiplier is no more than 9%. However, the total delay time for the shared multiplier is 20% greater than that of the single field multiplier.

The cyclic shared field multiplier 30 described above must be operated with 13 bits. Therefore, the entire ECC system within which such a shared-field multiplier operates has to be carried out with 13-bit symbols, increasing the overall gate count of the ECC system as a result.

Other embodiments are contemplated. For example, the shared multiplier may be implemented using a composite (or "extended") field structure. Because the composite field requires 12 bits only, overall gate count is reduced from that of the cyclic implementation. However, the latency associated with the composite field implementation may be more than that of the cyclic shared-field multiplier of FIG. 4.

Extended Galois fields are known and well-defined. The earlier-mentioned Peterson and Weldon book, at p. 155, defines an extension field in the following manner: "A field formed by taking polynomials over a field F modulo an irreducible polynomial p(X) of degree k is called an extension field of degree k over F." Thus, the GF(2.sup.5) field may be extended to the GF((2.sup.5).sup.2) field, that is, the GF(2.sup.10) field, using a polynomial p(x) of degree 2, such as x.sup.2 +a.sub.1 x+a.sub.0, which is irreducible over GF(2.sup.5), such that a.sub.1, a.sub.0 are elements of GF(2.sup.5). Likewise, taking a primitive element .alpha..sub.6 =(3).sub.8, the GF(2.sup.6) field may be extended to GF(2.sup.12) using the polynomial p(x)=x.sup.2 +x+.alpha..sub.6.sup.42, which is irreducible over GF(2.sup.6).

Consider A(x) and B(x) as elements of the field GF(2.sup.10), where A(x)=A.sub.1 x+A.sub.0 and B(x)=B.sub.1 x+B.sub.0, and A.sub.1, A.sub.0 and B.sub.1, B.sub.0 are elements of the GF(2.sup.5) field. Multiplication of elements A=(A.sub.1, A.sub.0) and B=(B.sub.1, B.sub.0) in GF(2.sup.10) can be calculated by the Karatsuba-Ofman algorithm

AXB=(D+(A.sub.0 *B.sub.0), (A.sub.0 *B.sub.0)+(A.sub.1 *B.sub.1)) (4)

where A.sub.i, B.sub.i.epsilon.GF(2.sup.5) and D=(A.sub.0 +A.sub.1)*(B.sub.0 +B.sub.1).

Similarly, the multiplication of two field elements A=(A.sub.1, A.sub.0) and B=(B.sub.1, B.sub.0) in GF(2.sup.12) can be calculated by

AXB=(D+(A.sub.0 *B.sub.0), (A.sub.0 *B.sub.0)+(A.sub.1 *(B.sub.1 *.alpha..sub.6.sup.42) (5)

where A.sub.i, B.sub.i.epsilon.GF(2.sup.6) and D=(A.sub.0 +A.sub.1)*(B.sub.0 +B.sub.1). Since .alpha..sub.6.sup.42 =(10).sub.8, then

B.sub.1 *.alpha..sub.6.sup.42 =(b.sub.1,0, . . . b.sub.1,5)*.alpha..sub.6.sup.42 =(b.sub.1,3, b.sub.1,4, b.sub.1,5, b.sub.1,3 +b.sub.1,0, b.sub.1,4 +b.sub.1,1, b.sub.1,5 +b.sub.1,2). (6)

Eq. (6) can be obtained for GF(2.sup.6) using the multiplication illustrated in FIG. 9, as described below.

The operation of Eqs. (4) and (5) is simplified by reducing the product A(x)*B(x) modulus p(x), where p(x) is an irreducible polynomial of GF(2.sup.m) of degree k, and therefore may be derived in the following manner:

A(x)*B(x)=A(x)B(x)mod p(x)=(A.sub.1 x+A.sub.0)(B.sub.1 x+B.sub.0)mod p(x)=A.sub.1 B.sub.1 x.sup.2 +(s+A.sub.1 B.sub.1 +A.sub.0 B.sub.0)x+A.sub.0 B.sub.0 mod p(x)

where s=(A.sub.1 +A.sub.0)(B.sub.1 +B.sub.0)=A.sub.1 B.sub.1 +A.sub.1 B.sub.0 +A.sub.0 B.sub.1 +A.sub.0 B.sub.0

Letting A.sub.0 B.sub.0 =D.sub.0, A.sub.1 B.sub.1 =D.sub.1, s=D2, s.sub.2 =D.sub.1, s.sub.1 =D.sub.2 +D.sub.1 +D.sub.0, and s.sub.0 =D.sub.0, and using p(x)=x.sup.2 +p.sub.1 x+p.sub.o (where x.sup.2 mod x.sup.2 +p.sub.1 x+p.sub.0 =p.sub.1 x+p.sub.0) for GF(2.sup.10) and GF(2.sup.12), then

A(x)*B(x)=s.sub.2 x.sup.2 +s.sub.1 x+s.sub.0 mod p(x)

where p(x)=x.sup.2 +p.sub.1 x+p

0=(s.sub.2 x.sup.2 +s.sub.1 x+s.sub.0)mod x.sup.2 +p.sub.1 x+p

o=s.sub.2 p.sub.1 x+s.sub.2 p.sub.0 +s.sub.1 x+s

0=(s.sub.2 p.sub.1 +s.sub.1)x+(s.sub.2 p.sub.o +s

0)=(s.sub.2 +s.sub.1)x+(s.sub.2 +s.sub.0) if GF(2.sup.10)

where (s.sub.2 +s.sub.1)=D.sub.1 +D.sub.2 +D.sub.1 +D.sub.0 =D.sub.2 +D.sub.0 =C.sub.1

where (s.sub.2 +s.sub.0)=D.sub.1 +D.sub.0 =C

0=(s.sub.2 +s.sub.1)x+(s.sub.2.alpha..sup.42 +s.sub.0) if GF(2.sup.12)

where (s.sub.2 +s.sub.1)=C.sub.1

where (s.sub.2.alpha..sup.42 +s.sub.0)=C.sub.0

where .alpha..sup.42 is a constant multiplier

Based on the composite structure property discussed above, along with the equations (4) and (5), a shared field multiplier 70 for GF(2.sup.10) and GF(2.sup.12) is implemented as shown in FIG. 7. Referring to FIG. 7, the shared field multiplier 70 includes inputs (multiplicand) A.sub.0 and A.sub.1 72, (multiplier) B.sub.0 and B.sub.1 73, and output values (product) C.sub.0 and C.sub.1 74. Further included are base multipliers 76a, 76b, 76c (more generally, 76), output adders 78a and 78b, a constant multiplier 80, a constant multiplier select 82, input adders 83a, 83b and a control line 84. The control line 84 is connected to each of the base multipliers 76 and the constant multiplier select 82. The base multiplier 76a receives as inputs A.sub.0 and B.sub.0. The base multiplier 76b receives as inputs A.sub.0 +A.sub.1 (as summed by input adder 83a) and B.sub.0 +B.sub.1 (as summed by the input adder 83b). The base multiplier 76c receives as inputs A.sub.1 and the output of the constant multiplier select 82, which, under the control of the control line 84, selects the input B.sub.1 in 10-bit mode and the output of the constant multiplier (i.e., B.sub.1.alpha..sup.42 80 in 12-bit mode). The products generated by the base multipliers 76a and 76c are exclusive-ORed by the output adder 78b to produce output value C.sub.0. The products of the base multipliers 76a and 76b are exclusive-ORed by the output adder 78a to produce output value C.sub.1.

The base multipliers 76 of the shared-field multiplier 70 are implemented as shared field multipliers for GF(2.sup.5) and GF(2.sup.6). With a 5-bit field GF(2.sup.5) generated by the primitive polynomial x.sup.5 +x.sup.2 +1, multiplication of two field elements a=(a.sub.0, . . . , a.sub.4) and b=(b.sub.0, . . . , b.sub.4) can be calculated using a multiplication algorithm known as the Mastrovito algorithm, illustrated in FIG. 8. With reference to FIG. 8, d.sub.1.sup.(5) =a.sub.1 +a.sub.4, d.sub.2.sup.(5) =a.sub.0 +a.sub.3 and d.sub.3 =a.sub.2 +a.sub.4. For a detailed description of the Mastrovito multiplier algorithm, reference may be had to a paper by E. D. Mastrovito, entitled "VLSI Design for Multiplication Over Finite Field GF(2.sup.m)," Lecture Notes in Computer Science 357, pp. 297-309, Springer-Verlag, Berlin, March 1989.

Similarly, for the field GF(2.sup.6), which can be generated with an irreducible polynomial x.sup.6 +x.sup.3 +1, multiplication of two field elements a=(a.sub.o, . . . , a.sub.5) and b=(b.sub.0, . . . , b.sub.5) of GF(2.sup.6) can be calculated by the multiplication operation (again, using the Mastrovito multiplier algorithm) shown in FIG. 9, where d.sub.1.sup.(6) =a.sub.1 +a.sub.4, d.sub.2.sup.(6) =a.sub.0 +a.sub.3 and d.sub.4 =a.sub.2 +a.sub.5.

It is apparent from the calculations illustrated in FIGS. 8 and 9 that the field multipliers for GF(2.sup.5) and GF(2.sup.6) share the same d.sub.1 and d.sub.2 terms. Therefore, d.sub.1 can be defined by d.sub.1 =.sub.a.sub.1 +a.sub.4 and d.sub.2 defined by d.sub.2 =a.sub.0 +a.sub.3 for both of the multipliers.

Referring to FIG. 10, the base multiplier 76--a shared field multiplier for GF(2.sup.5) and GF(2.sup.6)--is based on the similarity of the two multiplications presented in FIGS. 8 and 9. Each base multiplier 76 includes the set of "a" inputs 72, the second set of "b" inputs 73, and a set of "c" outputs 82. Further included is a first compute circuit or "d compute logic" 86, a second compute circuit or "e compute logic" 88 and a third compute circuitry or "c.sub.i -compute logic" (where I=0 to 5) 90. Note that the control line 84 (from FIG. 7) is coupled to the c.sub.o compute logic 90a, the c.sub.2 compute logic 90c, the c.sub.3 compute logic 90d, the c.sub.5 compute logic 90f and the e compute logic 88.

Referring to FIG. 11, the d compute logic 86 includes adders (i.e., exclusive ORs) 100a through 100d. The adder 100a XORs a.sub.2 and a.sub.5 to produce d.sub.3.sup.(6). The adder 100b XORs a.sub.2 and a.sub.4 to produce d.sub.3.sup.(5). The adder 100c XORs a.sub.0 and a.sub.3 to produce d.sub.2. The adder 100d XORs a.sub.1 and a.sub.4 to produce d.sub.1.

Referring to FIG. 12, the e compute logic 88 includes selectors 102a, 102b, 102c and 102d, all coupled to the control line 84. When the control line 84 defines the 10-bit mode, the selector 102a operates to select input a.sub.2 as output e.sub.1, the selector 102b selects a.sub.3 as e.sub.2, the selector 102c selects a.sub.4 as e.sub.3 and the selector 102d selects a.sub.2 as e.sub.4. When the control line 84 selects the 12-bit mode, the selector 102a selects a.sub.3 as e.sub.3, the selector 102b selects a.sub.4 as e.sub.2, the selector 102c selects a.sub.5 as e.sub.3, and the selector 102d selects d.sub.3.sup.(6) as e.sub.4.

Referring to FIG. 13, the c.sub.o compute logic 90a includes six AND gates 104a, 104b, 104c, 104d, 104e, 104f, and a MUX 106. Also included are five XOR gates 108a, 108b, 108c, 108d, and 108e. The AND gate 104a receives as inputs b.sub.o and a.sub.o. The output of the AND gate 104a is connected to the adder 108a, which XORs that output to the output of AND gate 104b. The AND gate 104b logically ANDs inputs b.sub.3 and e.sub.1. The adder 108b XORs the outputs of AND gates 104c, which ANDs b.sub.2 and e.sub.2, and 104d, which ANDs b.sub.1 and e.sub.3. The XOR 108d receives the output of the AND 104e, which is coupled to b.sub.5 and d.sub.1, as well as the output of AND gate 104f, which receives as inputs b.sub.4 and the output of the mux 106. The mux 106 receives as inputs d.sub.1 and d.sub.3.sup.(6). The MUX 106 receives as a select the control line 84. When control line 84 has the 10-bit mode selected, the mux 106 selects d.sub.1. In the 12-bit mode, mux 106 selects d.sub.3.sup.(6). The XOR gate 108c XORs the outputs of the XOR gates 108a and 108b. The XOR gate 108d XORs the outputs of AND gates 104e and 104f. The XOR gate 108e XORs the outputs of the XOR gates 108c and 108d to produce output value c.sub.o.

Referring to FIG. 14, the c.sub.1 compute logic 90b includes six AND gates 120a, 120b, 120c, 120d, 120e and 120f. Also included are five XOR gates 122a, 122b, 122c, 122d, and 122e. The XOR gate 122e XORs the outputs of XORs 122d and 122e to produce c.sub.1. The XOR gate 122d XORs the outputs of the XOR gates 122a and 122b. The XOR gate 122a XORs the outputs of AND gates 120a and 120b. The AND 120a gate receives as inputs b.sub.1 and a.sub.0. The AND gate 120b receives as inputs b.sub.o and a.sub.1. The XOR gate 122b XORs the outputs of AND gates 120.sub.c and 120.sub.d. The AND gate 120c receives as inputs b.sub.4 and e.sub.1. The AND gate 120d receives as inputs b.sub.3 and e.sub.2. The XOR gate 122c XORs the AND gates 120e and 120f. The AND gate 120e is coupled to inputs b.sub.2 and e.sub.3. The AND gate 120f is coupled to inputs b.sub.5 and d.sub.3.sup.(6).

Referring to FIG. 15, the c.sub.2 compute logic 90c includes four MUXes 130a, 130b, 130c and 130d, all coupled the control line 84, six AND gates 132a, 132b, 132c, 132d, 132e, 132f, and six XOR gates 134a, 134b, 134c, 134d, 134e, and 134f. The XOR gate 134f XORs the outputs of XOR gates 134d and 134e to produce c.sub.2. The XOR gate 134e XORs the outputs of XOR gates 134b and 134c. The XOR gate 134b XORs the outputs of the AND gates 132a and 132b. The AND gate 132 a receives as inputs b.sub.2 and the output of the mux 130a, controlled to generate as an output a.sub.0 for 12-bit mode and d.sub.2 for 10-bit mode. The AND gate 132b receives as inputs b.sub.1 and the output of the mux 130b, which is controlled to select as its output the input a.sub.1 for 12-bit mode and the input d.sub.1 for 10-bit mode. The AND gate 132c receives inputs b.sub.o and a.sub.2. The AND gate 132d receives as inputs b.sub.5 and a.sub.3. The AND gate 132e receives as inputs b.sub.4 and the output of the mux 130c, which is controlled to select input a.sub.4 in 12-bit mode and the XOR sum produced by the XOR gate 134b of inputs a.sub.3 and d.sub.1 in 10-bit mode. The AND gate 132f receives as inputs b.sub.3 and the output of the mux 130d, which is controlled to select a.sub.5 in 12-bit mode and d.sub.3.sup.(5) in 10-bit mode.

Referring to FIG. 16, the c.sub.3 compute logic 90d includes a mux 140, which is coupled to and controlled by control line 84, six AND gates 142a, 142b, 142c, 142d, 142e, 142f, and five XOR gates 144a, 144b, 144c, 144d and 144e. The XOR gate 144e XORs the outputs of XOR gates 144c and 144d. The XOR gate 144c XORs the outputs of XOR gates 144a and 144b. The XOR gate 144a XORs the outputs of the AND gates 142a, which produces b.sub.5 *a.sub.1 and 142b, which generates a product from inputs b.sub.4 and the selected output of the mux 140--a.sub.2 in 10-bit mode and d.sub.3.sup.(5) in 12-bit mode. The AND gate 142c generates the product b.sub.0 *a.sub.3 and the AND gate 142d generates the product b.sub.1 *e.sub.4. The AND gate 142e generates the product b.sub.3 *d.sub.2 and the AND gate 142f produces the product b.sub.2 *d.sub.1.

Referring to FIG. 17, the c.sub.4 compute logic 90e includes six AND gates 150a, 150b, 150c, 150d, 150e, 150e, 150f, and five XOR gates 152a, 152b, 152c, 152d, and 152e. The XOR gate exclusive-ORs the outputs of XOR gates 152d and 152c. The XOR gate 152d XORs the outputs of XOR gates 152a and 152b. The XOR gate 152a XORs the outputs of the AND gates 150a, which has as its inputs b.sub.5 and a.sub.2, and 150b, which has for inputs b.sub.1 and a.sub.3. The XOR gate 152b, in conjunction with AND gates 150c and 150d, computes b.sub.0 *a.sub.4 +b.sub.2 *e.sub.4. The XOR gate 152c adds product b.sub.4 *d.sub.2 (from the AND gate 150e) and product b.sub.3 *d.sub.1 (from the AND gate 150f).

Referring to FIG. 18, the c.sub.5 compute logic 90f includes four muxes 160a, 160b, 160c, 160d, all coupled to the control line 84, six AND gates 162a-162f, as well as four XOR gates 164a-164d. The XOR gate 164e XORs the outputs of the XOR gates 164d and 164c. The XOR gate 164d XORs the outputs of XOR gates 164a and 164b. The XOR gate 164c XORs the outputs of AND gates 162e and 162f. The AND gate 162e receives as inputs b.sub.4 and d.sub.2. The AND gate 162f ANDs inputs b.sub.4 and the output of the mux 160d, which selects as that output input a.sub.5 if control line 84 selects 12-bit and input d.sub.1 if control line 84 selects 10-bit. The XOR gate 164a XORs the outputs of AND gates 162a and 162b, and the XOR gate 164b XORs the AND gates 162c and 162d. The AND gate 162a receives as inputs b.sub.2 and the output of the mux 160a, which is a.sub.5 for 10-bit symbol inputs and a.sub.3 for 12-bit symbol inputs (as determined by control line 84). The AND gate 162b receives as inputs b.sub.1 and the output of the mux 160b. The 160b mux output is determined by control line 84 to be a.sub.4 for 12-bit mode and a.sub.5 for 10-bit mode. The AND gate 162c receives as inputs b.sub.0 and a.sub.5. The AND gate 162d receives as inputs b.sub.3 and the output of the mux 160c. As with the other muxes, the output of mux 160c is selected by the control line 84. In 12-bit mode, the output of mux 160c is d.sub.3.sup.(6). In 10-bit mode, the output of mux 160c is a.sub.5.

The constant field multiplier 80 (from FIG. 7) is shown in detail in FIG. 19. Referring to FIG. 19 along with Eq. (6), the constant field multiplier 80 forms the product B.sub.1 *.alpha..sub.6.sup.42 by receiving constant multiplier inputs b.sub.1,0, . . . b.sub.1,5 170 and produces as outputs g.sub.o, g.sub.1, . . . , g.sub.5 172, which correspond to b.sub.1,3, b.sub.1,4, b.sub.1,5, b.sub.1,3 +b.sub.1,0, b.sub.1,4 +b.sub.1,1, b.sub.1,5 +b.sub.1,2, respectively As shown, b.sub.1,3 is XORed with b.sub.1,0 by a first XOR 174a, b.sub.1,4 is XORed with b.sub.1,1 by a second XOR 174b, and b.sub.1,5 is XORed with b.sub.1,2 by a third XOR 174c.

The gate count and delay for the base multiplier 76 is shown in the table of FIG. 20. The total number of gates is 85 and the total delay is 6.

The total gate count and delay for the shared field multiplier 30 (of FIG. 7) is provided in the table of FIG. 21. The total gate count is 288 and the associated delay is 8. In a two single field multiplier design, the gate count of the single field 10-bit multiplier is 75 AND and 95 XOR, and the gate count of the single-field 12-bit multiplier is 108 AND and 132 XOR. For a single chip design, the gate count increase for the shared-field multiplier will be 71% in comparison to a single-field 12-bit multiplier. In contrast, using the shared field multiplier shown in FIG. 7, the gate count increase is 30%, with an increase in latency of 15%.

The shared field multipliers 30, 70 of FIGS. 4 and 7, respectively, can be employed as either general or constant multipliers by conventional encoders and decoders. For example, and referring to FIG. 22, a simple, conventional encoder 200 includes constant Galois field multipliers 202 which multiply each of the coefficients of a generator polynomial G(x) by a polynomial coefficient corresponding to each code word symbol of a code word input 204. Collectively, the multipliers 202, along with shift register stages 206 and adders 208, operate to produce an encoded code word output 210 from the code word input 204. A detailed description of this type of encoder, along with alternative encoder implementations, all of which utilize field multipliers for fixed polynomial multiplication and/or division, can be found in the Peterson and Weldon book, as well as other texts.

In another example, and referring to FIG. 23, a conventional decoder shown as a Reed-Solomon decoder 220, may use a combination of general and constant field multipliers, both of which may be implemented as the shared field multipliers for handling either 10-bit or 12-bit field multiplication. The conventional decoder 220 for receiving an erroneous code word and producing a corrected code word includes a syndrome computation unit 222, an error locator polynomial generator 224, an error location computation (or root finding) circuit 226, and error value computation unit 228, and an error corrector 230. Control of each of the units is effected by a decoder control unit 232.

The decoder 220 typically uses general multipliers in performing algorithms of the error locator polynomial generator 224, or constant (fixed polynomial) field multipliers in the syndrome computation circuit 222 and error location computation circuit 226. Examples of such decoding circuits that employ constant field multipliers are described in a U.S. application Ser. No. 09/327,285, entitled "Determining Error Locations Using Error Correction Codes", in the name of Lih-Jyh Weng, incorporated herein by reference. Additional details of these circuits, along with general (polynomial) multiplications of the type used to generate error locator polynomials, for example, the well-known Euclidean and Berlekamp-Massey algorithms, can be found in the aforementioned book by Peterson and Weldon, as well as U.S. Pat. No. 5,107,503, issued to Riggle et al., also incorporated herein by reference, as well as many other sources.

Although the cyclic and composite shared field multipliers have been described with respect to a 10-bit/12-bit implementation, they may be suitably modified for use with field elements of other sizes. A cyclic shared field multiplier of the type described above could be designed for elements of other cyclic fields, e.g., 12-bit/18-bit or 18-bit/28-bit. Other values of m for cyclic Galois fields GF(2.sup.m) are discussed in the above-referenced Wolf paper. The composite shared field multiplier concept could be extended to other field element sizes as well, e.g., 12-bit/14-bit or 14-bit/16-bit, to name but a few combinations. Also, the shared field multiplier could conceivably be shared by more than two different field element sizes, e.g., a composite field multiplier could be designed to support three different field element sizes (such as 10-bit/12-bit/14-bit).

«Previous Next»
Efficient hybrid public key signature scheme Message recovery signature apparatus